Category Archives: Materials and Equipment

August 5, 2009: A pair of university spinoffs in Pennsylvania are receiving funding from the Pennsylvania NanoMaterials Commercialization Center to help their work in nanopolymers and nanofibers.

Philadelphia-based Arkema Inc. is getting $275,000 of funding from the Air Force Research Laboratory (AFRL), matched by Lehigh University, to develop and commercialize its block copolymer technology, called BlocBuilder, used to toughen epoxies for wind energy (e.g. more reliable wind blades) and strengthen electronic materials (e.g. higher resistance to crack formation). They are also exploring applications for adhesives, coatings, and composites.

Also receiving funding is nanoGriptech, a spinoff from Carnegie Mellon, which will use $200,000 in AFRL funding to commercialize its fibrous adhesive technology which mimics the nano- and micro-fibers that allows certain animals (e.g., geckos) to grip strongly and repeatedly on smooth and rough surfaces. Initial work will be to design, manufacture, select materials, and test the adhesives for new commercial sportswear applications.

August 3, 2009: Carbon nanotube maker SouthWest Nanotechnologies (SWeNT) and nanomaterials consultancy Chasm Technologies have established an application development center in the Boston area to help demonstrate for customers the feasibility of carbon nanotube coatings and printing applications, and stimulate demand for SWeNT’s CNT materials.

Single-wall and small diameter multi-wall carbon nanotubes exhibit extraordinary properties when incorporated into coating formulations, with promise seen in applications such as displays, touchscreens, sensors, LED lighting, and solar photovoltaic modules.

The center will utilize a variety of thin-film coating and patterning technologies, including rod coating, slot die coating, spray coating, ink jet printing, flexographic printing, screen printing and imprint lithography. Trials can be done at bench- (sheets) or pilot-scale (continuous lengths up to 12in. wide) accommodating a wide range of substrates. Customized coating formulations can be prepared on-site. The center also includes a wide range of test equipment to characterize coated product structures.

“Many commercial opportunities for [our] nanotubes were being held back because it was too difficult for our customers to integrate carbon nanotubes into industrial coating and printing processes,” according to Dave Arthur, SWeNT CEO and Chasm co-founder, in a statement. “The technical team at Chasm has in-depth experience developing coating and printing methods for various nanoparticles, and a superb laboratory for process development. SWeNT’s customers will be encouraged to visit the center to consult directly with the technical staff to make it much easier for them to fabricate and test prototypes utilizing carbon nanotube coatings.”

“Consistent material properties are essential to developing robust processing methods. SWeNT has manufacturing methods that are easily scalable to support the many large volume opportunities for these materials,” added Chasm co-founder Bob Praino.

At SEMICON West, Horacio Mendez, executive director of the SOI Industry Consortium, previewed a major study that compares the manufacturability, performance, and cost of 3D transistors vs. bulk. Ensuring companies in the process of making a decision about transitioning from bulk to SOI have access to information so they can make an educated decision, is a high priority of the Consortium, he notes.

Mendez also previews the group’s “Simply Greener” initiative to showcase major energy savings vs. bulk silicon, and discusses the role of the group:

July 27, 2009 – Matthias Meier, manufacturing engineering & automation at the Fraunhofer Institute, discusses his role as “coach” of the PV Equipment Standards task force in an interview at SEMICON West. SEMI released the new PV2-0709 standard at SEMICON West. Driven by the needs of solar PV manufacturers, the standard, which focuses on data acquisition and access, is expected to be widely adopted.

The key features of the standard are to allow access to data generated on production equipment for PV manufacturing — following substrates through the line, collecting all data generated on the way, using processes to establish quality measures, e.g. figure out where glitches occur in the production line and detecting them early.

There is a clamor to adopt such standards from all sides, notes Meier. Manufacturers complain that they have to specify systems for every factory, what the interfaces should be. Equipment suppliers need to build and maintain those interfaces. Software firms find it hard to integrate all the equipment. And now some initial manufacturing lines are now using at least part of the standard, he notes.

(July 22, 2009) MINNEAPOLIS &#151 The SMTA and Chip Scale Review magazine finalized the program for the 6th Annual International Wafer-Level Packaging Conference (IWLPC). The conference will be held October 27-30, 2009, at the Santa Clara Marriott Hotel in Santa Clara, CA. Registration is now being processed on-line.

The program includes five tutorials, expert panel discussions, distinguished keynote speaker, Advanced Packaging Editorial Advisory Board member Dr. Rao Tummala, and 18 tech sessions featuring a new track on MEMS WL and WLP.

IWLPC explores cutting edge topics in wafer-level packaging and IC/MEMS/MOEMS packaging, including 3D/Stacked/CSP/SiP/SoP and mixed technology packages. The event is sponsored by Dow Electronic Materials, Pac Tech USA, and Technic Inc. Read about last year’s IWLPC, with commentary from Terence Q. Collier, contributing editor.

For more information, visit www.iwlpc.com.

July 17, 2009 – At SEMICON West, SAFC Hitech unveiled details of its six-year-out (through 2014) materials roadmap for metalorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD) processes on silicon semiconductor substrates, outlining development paths for advanced memory and logic including barrier layers, interconnects, dielectrics and metals.

The roadmap is an update of one released in mid-2007, but “there are numerous variables that can affect the selection, timing of insertion point and volume demand for electronic materials,” noted Geoff Irvine, SAFC Hitech’s VP of business development, in a statement. “Through assessment, for example, if there are certain materials that have been adopted more rapidly than anticipated or adapted for an alternative application and, conversely, if there are some that may have seen a delay or reconsideration in use, our review process enables us to recast the materials requirements of the semiconductor industry and revise our roadmap accordingly.”

Of note in the company’s analysis is a shorter materials lifespan as advanced nodes bring in new materials to meet performance criteria, e.g., the rapid adoption of aluminum, hafnium and zirconium oxides, and mixed silicates, he noted. Materials for deposition and dielectrics in metal-insulator-metal capacitors for DRAM also illustrate this trend, added Ravi Kanjolia, the company’s CTO. “Precursor chemistries have transitioned rapidly from providing solutions for growing high quality conformal amorphous films of Al2O3 to HfO2 followed by ZrO2. Similar trends regarding timescales for the adoption and integration of new materials in other functional layers of the devices are now also being seen.”


SAFC Hitech’s materials roadmap. (Source: SAFC Hitech)
CLICK HERE to view larger image

The company says it will continue to focus on next-gen high-k for gate applications, high-k and ultrahigh-k dielectrics for capacitors, further development of metal gates, new electrode materials for DRAM, and copper barrier/seed materials. “Significant” progress also is being made in germanium antimony telluride (GST) precursors for use in high-volume phase change memory (PCM) applications, touted as a nonvolatile memory replacement candidate for NAND flash, the company said.

Semiconductor equipment manufacturers posted a book-to-bill ratio of 1.01 in June, according to VLSI Research. Dan Hutcheson, VLSI, reports. It was the first increase above parity since July 2008. Worldwide equipment bookings amounted to $2.5 billion in June, up 40% sequentially, but down 41% from the same month a year ago. Worldwide billings jumped 31% from the previous month to $2.4 billion, but were still a 57% lower from a year ago. Although bookings and billings remain well below normal levels, business activity is beginning to improve. Back-end suppliers, in particular, are seeing a considerable pick up in business activity amid soaring utilization rates at the subcontractors.

At the front-end, most of the equipment orders are still technology-related, driven primarily by the 3x and 4x nm ramp. In addition, the transition to DDR3 is finally picking up and is beginning to drive some orders in the memory sector, which had been lifeless for months.

2010 is expected to be better. First of all, Moore’s Law is not dead and for memory it’s on a much more sustainable rate of halving every 2 years. Asia’s attempt to make Hwang’s ‘law’ a law proved costly, but this has been essentially over since 2001. It was just that the memory makers hadn’t figured it out and over invested. That’s not a problem anymore.

When you look at the data, cost-per-bit has continued to decline and this year’s price/performance increases as demonstrated in VLSI Chip Price Performance Index (CPPI) is making memory profitable. But that profitability is highly dependent on continued scaling.

On the logic side, INTEL is more committed to scaling than ever. So are IBM and its partners, like GLOBALFOUNDRIES and TOSHIBA.

This summer’s upturn in equipment orders is being driven by the 3x nm ramp. Plus, 2x nm is hot on 3x’s heels. Lithography is well up to the task of making these transitions, as are CMP, implant, deposition, and etch. Assembly is being driven by the shift out of gold and into copper wire. Obviously, with gold prices continuing to kiss $1000 per ounce it makes loads of sense. Back in the day when gold went for $300/oz, contract package prices were around a penny a wire and the largest chunk of that penny was gold.

Improvements in wire bonders and other assembly equipment took that below half-a-penny, but gold prices have pushed costs back up. Copper wire is the only solution. Test is being driven by ever more complexity of mixed RF with baseband and memory as well as new generations of memory devices with new fault modes.

Capacity utilization at 45nm and below is at 90%, as it is for 300mm utilization. Test and Assembly utilization are similar for their advanced technologies. Averages for all three will be above 90% next month if the current trend continues.

Semiconductors have been on a fairly steady growth path since January. Inventory build-up has been readily consumed and is 35% below where it was at the peak, last September. The inventory-to-billings ratio has stayed below 1.5 since February, another good sign.

Electronics shipments are up 44% since January. Ironically, the economic downturn with its “staycations” is driving consumer demand. Surveys showed and now people have voted with their money that they are more willing to give up going out than they are willing to give up their high-speed Internet connections.

Then there’s been the netbook and more widespread availability of 3G mobile networks. Next year, the 4G build-out starts. Apple has proven that consumers want more data to their cell phones. The cell phone has become a mobile infotainment center, when you get your news, e-mail, tweets, and watch the latest YouTube videos. The smart phone has moved out of the executive jewelry category and into the mainstream.

This is what happened in the late 1990s with the cell phone and let’s not forget the personal computer, which kicked off demand for the VLSI era. Speaking of the PC, while others disagree, we believe Windows 7 will be an important driver. In the last decade or so, Window’s releases haven’t had the punch they had in the nineties. But Microsoft has never messed up a product launch as badly as they did with Vista. There should be a significant backlog of demand.

Finally, it looks like we will finally see Internet TV in the living room. NETFLIX is committed to making it the next movie delivery mode.

For more information, visit http://www.wesrch.com/weqEL1U7T7.

July 15, 2009 – Jan Vardaman discusses alternatives to 3D/TSV technologies for cost-sensitive applications, and makes the case for additional work to develop design guidelines and software, and test methodologies for 3D/TSV technologies.

There’s still a lot of work to be done in design, thermal, and test, she says. There’s been a lot of work done and progress made recently in the thermal field, she noted. But more needs to be done in the design area, so that software can be available to anyone who wants to use the technology (e.g. fabless companies who want design guidelines from their foundry). TSMC and others have made progress here (and IDMs like Intel and IBM have their own internal capabilities), but more needs to be done, she said.

As with any new technology (including 3D TSV), it has to be placed in the context of a cost/benefit analysis to be judged vs. current technologies, and only when determined to be a compelling reason to shift to a technology will it happen, she says. E.g., what can TSV offer that wire bonding cannot for cost-sensitive flash makers (who can thin a die down to ~30 microns with bonding)? DRAMs for server applications, on the other hand, probably will need to explore new technologies (TSV as well as things like vertical circuits) as wire bonding runs out of gas there. Decisions will be made on a case-by-case basis, she noted.

July 14 — The idea of thinning, stacking and interconnecting chips is not new: suppliers of memory and flash drives have successfully been doing that for years. The difference between the approach they typically use and the 3D integration that has become the buzzword of today is mostly related to how the chip-to-chip connections are made. The traditional approach is with wire bonding, which has many advantages: it uses the installed base of equipment, it’s low cost, and it’s well understood. Two- and four-chip wire-bonded stacks are common today, and stacks with nine or more chips have been produced.

The main problem with wire bonding is that long looping wires can lead to higher levels of resistance, capacitance, and inductance and other electrical performance issues. That’s not a problem for most memories today, but could pose a potential problem in the future and for special applications, such as the integration of memories with microprocessors. Wire bonding on very thin die can also be a challenge in that the force required can sometimes crack or break a die — far from ideal if that die were one of the last die in a multi-chip stack.

An alternative approach, where chips are thinned, stacked, and interconnected with through silicon vias (TSVs) fabricated with front-end-like processes (etch, dielectric deposition, and electroplating) offers great promise as a way to achieve higher levels of functionality in a smaller space, with higher performance and potentially lower cost than wire-bonded chip stacks.

This approach has been the focus of an on-line virtual forum, hosted by public relations firm MCA at www.semineedle.com/MCA3DIC. The panel, moderated by industry commentator Francoise von Trapp, consists of Robert Patti of Tezzaron Semiconductor, a semi-fabless memory supplier, Sitaram Arkalgud of SEMATECH, Paul Linder of EVG, Ricardo Borges of Synopsys, and Jean-Christophe Eloy of Yole Development, a market analyst firm.

One of the main focal points of the forum has been to define exactly where 3D integration is today in terms of industrialization. Patti of Tezzaron said that he is seeing a “huge increase” in customers trying their first 3D devices. “They range from complete test devices which covers a lot previous work in the industry, but allows the customer to get their own data, to very complex 3D logic and memory devices. We expect our customers alone to fabricate more new 3D devices in the next 12 months than all previous work combined. I’m sure that other 3D technology providers are seeing the same industry pull through today,” he said.

Paul Linder, EVG’s chief technology director, said we are at an early stage when looking at industrialization level. “Many pilot lines at manufacturing sites are getting online — a good change from years ago when 3D-IC was mostly a research topic,” he said.

With the exception of early adopters, such as CMOS image sensors, most companies are working on the qualification of specific process integration schemes, Linder added. “All of the new 3D process steps around TSV’s (litho, bonding, thinning, etching, and plating) are well-developed and can benefit from continuous improvement programs already.

“When it comes to process integration we see a lot of diversity out there and proprietary process flows. We think this is typical for revolutionary technologies and enables initially a competitive benefit to our customers. In the long run we expect that standardization will become more attractive to the users.”

The benefits of 3D

One of the clearest benefits of 3D integration, and why it could be quickly adopted into mainstream manufacturing is speed, noted Patti. “Scaling continues to make transistors faster, but wire, as we all know, just gets slower. Physics just conspires against us here. The improvement in transistor performance is tiny compared to the slowdown of the wire. To make wires faster, you need to make them shorter. 3D can do that far better than scaling and at a comparatively small cost,” he said.

3D offers benefits in power, density and cost, but these require new approaches, Patti noted. “Co-mingling of transistors and wire allows process separation leading to reduced costs — i.e., just build memory in the memory process, just build logic in a logic process,” he said. “SOCs put a huge burden on processing. If you need flash, DRAM, and a processor on the same chip, you have a fab nightmare.” The cost burden is huge, he pointed out — even though none of the functionality (flash, DRAM, or CPU) covers the entire chip, “the entire chip gets these processes applied to it. I like to say the foundry does offer a refund for under-utilized silicon area. With 3D, unecessary processing can be avoided, lowering cost and improving yield.”

Another advantage is density: Four layers of 45nm circuitry take about the same space as one 22nm device. “By virtually any measure, development cost, fab facility cost, even piece part, 3D wins.” Patti said.

A third advantage is power. “If we assume high-k gates, and lower transistor leakage, most of the power is left in the charging and discharging of the wire,” Patti said. “Make shorter wires [and] you get lower power. In our memories we make the wires half as long and we get a 40% reduction in per bit power.”

How 3D rescues Moore’s Law

The real advantage of 3D integration, however, is that it offers a way to stay on the path defined by Moore’s law without continued scaling, which is getting increasingly expensive. “I think in the end you need to look at what is the objective of scaling. Historically, it was performance, power, cost, and density. Performance was probably the driver for many years, at least for logic devices,” Patti said. “For DRAM it most certainly was cost. Today, it is safe to say, we get no performance improvement from scaling. Power isn’t improving. 3D can drive density faster than scaling. And the cost benefit from scaling is rapidly eroding. 22nm may be more costly than 45nm per transistor for sometime.”

But don’t get him wrong — he’s not predicting an end to scaling, rather a major slowdown. “Fractional node advances are going to be the norm moving forward. The next decade or two will belong to 3D integration, just as the last has been the domain of CMOS. The exploitation of 3D has barely started. The opportunities go far beyond just connecting together the bond pads,” he said.

Michael Fritze, program manager at DARPA, said he sees 3DIC as a potential means of making affordable SoCs, thus “enabling a whole new range of applications that are simply not economically viable today given the volumes required to justify a custom SOC design.” Fritze is also bullish on the potential of 3DIC for achieving ultralow-power electronics solutions, although he said serious design and architecture changes would be required to achieve this. “This is the key challenge: getting folks to start thinking about the novel architectures that would be capable of exploiting 3D IC benefits. This will require CAD/EDA tools before killer apps are identified — quite an economic challenge,” he noted. — P.S.

July 14 — The idea of thinning, stacking and interconnecting chips is not new: suppliers of memory and flash drives have successfully been doing that for years. The difference between the approach they typically use and the 3D integration that has become the buzzword of today is mostly related to how the chip-to-chip connections are made. The traditional approach is with wire bonding, which has many advantages: it uses the installed base of equipment, it’s low cost, and it’s well understood. Two- and four-chip wire-bonded stacks are common today, and stacks with nine or more chips have been produced.

The main problem with wire bonding is that long looping wires can lead to higher levels of resistance, capacitance, and inductance and other electrical performance issues. That’s not a problem for most memories today, but could pose a potential problem in the future and for special applications, such as the integration of memories with microprocessors. Wire bonding on very thin die can also be a challenge in that the force required can sometimes crack or break a die — far from ideal if that die were one of the last die in a multi-chip stack.

An alternative approach, where chips are thinned, stacked, and interconnected with through silicon vias (TSVs) fabricated with front-end-like processes (etch, dielectric deposition, and electroplating) offers great promise as a way to achieve higher levels of functionality in a smaller space, with higher performance and potentially lower cost than wire-bonded chip stacks.

This approach has been the focus of an on-line virtual forum, hosted by public relations firm MCA at www.semineedle.com/MCA3DIC. The panel, moderated by industry commentator Francoise von Trapp, consists of Robert Patti of Tezzaron Semiconductor, a semi-fabless memory supplier, Sitaram Arkalgud of SEMATECH, Paul Linder of EVG, Ricardo Borges of Synopsys, and Jean-Christophe Eloy of Yole Development, a market analyst firm.

One of the main focal points of the forum has been to define exactly where 3D integration is today in terms of industrialization. Patti of Tezzaron said that he is seeing a “huge increase” in customers trying their first 3D devices. “They range from complete test devices which covers a lot previous work in the industry, but allows the customer to get their own data, to very complex 3D logic and memory devices. We expect our customers alone to fabricate more new 3D devices in the next 12 months than all previous work combined. I’m sure that other 3D technology providers are seeing the same industry pull through today,” he said.

Paul Linder, EVG’s chief technology director, said we are at an early stage when looking at industrialization level. “Many pilot lines at manufacturing sites are getting online — a good change from years ago when 3D-IC was mostly a research topic,” he said.

With the exception of early adopters, such as CMOS image sensors, most companies are working on the qualification of specific process integration schemes, Linder added. “All of the new 3D process steps around TSV’s (litho, bonding, thinning, etching, and plating) are well-developed and can benefit from continuous improvement programs already.

“When it comes to process integration we see a lot of diversity out there and proprietary process flows. We think this is typical for revolutionary technologies and enables initially a competitive benefit to our customers. In the long run we expect that standardization will become more attractive to the users.”

The benefits of 3D

One of the clearest benefits of 3D integration, and why it could be quickly adopted into mainstream manufacturing is speed, noted Patti. “Scaling continues to make transistors faster, but wire, as we all know, just gets slower. Physics just conspires against us here. The improvement in transistor performance is tiny compared to the slowdown of the wire. To make wires faster, you need to make them shorter. 3D can do that far better than scaling and at a comparatively small cost,” he said.

3D offers benefits in power, density and cost, but these require new approaches, Patti noted. “Co-mingling of transistors and wire allows process separation leading to reduced costs — i.e., just build memory in the memory process, just build logic in a logic process,” he said. “SOCs put a huge burden on processing. If you need flash, DRAM, and a processor on the same chip, you have a fab nightmare.” The cost burden is huge, he pointed out — even though none of the functionality (flash, DRAM, or CPU) covers the entire chip, “the entire chip gets these processes applied to it. I like to say the foundry does offer a refund for under-utilized silicon area. With 3D, unecessary processing can be avoided, lowering cost and improving yield.”

Another advantage is density: Four layers of 45nm circuitry take about the same space as one 22nm device. “By virtually any measure, development cost, fab facility cost, even piece part, 3D wins.” Patti said.

A third advantage is power. “If we assume high-k gates, and lower transistor leakage, most of the power is left in the charging and discharging of the wire,” Patti said. “Make shorter wires [and] you get lower power. In our memories we make the wires half as long and we get a 40% reduction in per bit power.”

How 3D rescues Moore’s Law

The real advantage of 3D integration, however, is that it offers a way to stay on the path defined by Moore’s law without continued scaling, which is getting increasingly expensive. “I think in the end you need to look at what is the objective of scaling. Historically, it was performance, power, cost, and density. Performance was probably the driver for many years, at least for logic devices,” Patti said. “For DRAM it most certainly was cost. Today, it is safe to say, we get no performance improvement from scaling. Power isn’t improving. 3D can drive density faster than scaling. And the cost benefit from scaling is rapidly eroding. 22nm may be more costly than 45nm per transistor for sometime.”

But don’t get him wrong — he’s not predicting an end to scaling, rather a major slowdown. “Fractional node advances are going to be the norm moving forward. The next decade or two will belong to 3D integration, just as the last has been the domain of CMOS. The exploitation of 3D has barely started. The opportunities go far beyond just connecting together the bond pads,” he said.

Michael Fritze, program manager at DARPA, said he sees 3DIC as a potential means of making affordable SoCs, thus “enabling a whole new range of applications that are simply not economically viable today given the volumes required to justify a custom SOC design.” Fritze is also bullish on the potential of 3DIC for achieving ultralow-power electronics solutions, although he said serious design and architecture changes would be required to achieve this. “This is the key challenge: getting folks to start thinking about the novel architectures that would be capable of exploiting 3D IC benefits. This will require CAD/EDA tools before killer apps are identified — quite an economic challenge,” he noted. — P.S.