Category Archives: Materials and Equipment

Thin Wafer Processing


March 3, 2009

By Hans Hirscher, Ph.D. and Hans Auer, Oerlikon Systems
The demand for thin and ultrathin semiconductor devices grows continuously. Discrete and bipolar IC’s as well as devices for stacking or thin packages require thinner and thinner wafers. The challenge is to find a reliable processing method.

Not all thin wafer applications need backside processing. Some devices are ready for singulation when backgrinding is finished. It is only necessary for mechanical flexibility or minimized thickness for high package density. However, backside metallization is needed to manufacture ASICs, power devices, all types of mixed signal devices (e.g. BCD technology), microprocessors and other high-performance logic such as advanced DSP’s, as well as backside contacts in die stacking — all on increasingly thinner wafers.

The main applications for backside metallization (BSM) are:

  • to form a solder contact for an improved and reliable temperature drain
  • to create an electrical contact to the semiconductor (ohmic contact)
  • to contact a TSV with a UBM or RDL for chip stacking

    Backside processing begins with thin wafer handling, and the often-required edge handling on an ever shrinking width; the wafer must not be touched anywhere in the active frontside area. Especially with increasing wafer diameters, the transition from conventional batch processing to automated single wafer processing is a must. Manual thin wafer handling is a critical factor for breakage and reduced yield. Some process steps that addess these issues are available on Oerlikon’s CLUSTERLINE single wafer cluster tool. These include wafer degas, in-situ pre-etch, active thermal management, stress control, improved film performance and wafer cooling.

    When thin wafers below a certain critical thickness need to be processed, a wafer support system is required. However, these wafer support systems pose challenges to the backside processing since most of the time organic materials that require lower temperature limits are involved, and are often critical in when used in conjunction with high vacuum processes.

    Typical Applications and Processes/Layer Stack Function

    For backside metallization of discrete devices, the typical layer stack consists of
    three to four metal layers:

  • layer to Si wafer forming a good ohmic contact (Au, Au alloys, Al, Ti)
  • barrier and adhesion layer (Cr, Ti)
  • solder layer (Ag, Au, Ni, NiV)
  • protection or solder layer (Ag, Au, Au alloys)

    To assure good ohmic contact, a deposition at elevated temperature ( T> 300&degC ) is necessary to form interdiffusion or alloying with the silicon. The remaining three metal layers should be deposited at low temperature to avoid film stress and excessive bow to the wafer.

    Backside metallization to form a solder contact for an improved temperature drain is also a 3 metal system such as Ti- NiV- Ag.

    UBM or RDL for chip stacking typically consists of a Ti or TiW adhesion layer followed by Cu or Al as the conductive layer while some metal systems also employ 3 or more materials like Ti- NiV- Cu.

    Existing Wafer Support Systems
    The thinner the Si wafers are, the more flexible they are. Additionally, reducing the thickness also reduces the mass, which includes thermal mass. Consequently, temperature variations that occur during processing increase similarly.

    Several design solutions exist for wafer support systems (WSS). For example, mobile electrostatic carriers provide a glue-free method that replaces tape bonding/debonding with a charging decharging tool. Another uses a glass disc as a rigid carrier. The wafer is bonded to the glass by two layers of adhesive and a release layer. One wafer carrier solution uses a standard or slightly thinned wafer as a carrier with an adhesive layer. Separation is achieved by thermal release. A robust wafer carrier solution uses a rigid outer ring to keep a thin wafer rigid enough for handling and processing. Only the inner area of the wafer is thinned, leaving a stiff outer ring. And finally, the traditional tape carrier involves a “foil” type procedure uses a (standard) back grinding tape for handling and processing. Beyond those mentioned here, a number of specific designs developed for individual needs exist.

    There are pro’s and con’s that weigh differently for different applications to each of them. There does not seem to be a “one for all” solution nor an established standard. As the thin wafers undergo different process steps different specific carriers are needed. Even with the transportable ESC carrier method individual carriers are needed depending on the process (back grinding, implantation, wet etch for stress relief, back side metallization).

    The CLUSTERLINE platform (Figure 1) handles and processes bare thin wafers as well as wafers on carriers. Following a wafer through the tool, the different handling steps start in the wafer cassette. Wafers are carefully positioned, then mapped (located) in the load lock. Mapping is an especially critical step with thin wafers that tend to bow, and therefore require a specifically design mapping device.
    The robot end effector picks a wafer from the cassette, positions it onto the aligner, and then to the next process chamber. The wafer is then elevated to and from the process position by the chuck. Specific sensors assure that a wafer is safely positioned on the lift pins before being picked by the end effector, avoiding a potential wafer breakage. As the wafer is transported from chamber to chamber, its alignment is rechecked by sensors and corrected before placement in the next module. These elements combine to reliably handle thin wafers while bonding them to organic or glass carriers.


    Figure 1:Clusterline platform from Oerlikon

    Thermal Management
    A four-layer stack is typical for BSM processes. The WSS allows more easy handling of the substrates, but depositing metal layers remains a challenge in regards to thermal load to the substrate. All the presented WSS’s use adhesive interface materials, which reduce the thermal flow to the chuck. The following graphic shows this temperature gradient from the wafer through the WSS into the chuck.

    Figure 2 illustrates the situation for the mobile ESC. To improve thermal transfer, backside gas is injected into the interfaces. Adding up individual thermal resistivities, you find an effective heat transfer coefficient for the whole system. The delta in temperature across the WSS results in T = 106°C by applying an incoming power load of 0.5 W/cm2.


    Figure 2:Improving thermal transer using a mobile ESC.

    Compared to a wafer support system that uses adhesives or tape, k-values are comparable (100 and more). There is an unknown factor in the thermal conductivity of these plastic materials (including adhesives). In addition, it’s critical to properly apply these foils. In case of surface topography, which is common on the wafer frontside, the adhesive and tape may not enclose it completely. Temperature and vacuum conditions may generate bubbles and thus partially delaminate the foil which leads to hot spots on the wafer. Consequently, the thermal management in depositing film layers is an essentially important task. Oerlikon has developed a unique in-situ temperature measurement system that uses an optical fiber to look at the wafer backside through a window in the chuck. This allows total control of the wafer temperature during processing for development purposes, as well as temperature monitoring in production (Figure 3).

    Conclusion
    This single wafer cluster tool offers metallization of thin wafers down to a minimal thickness of approx. 100&#181m for 200mm wafers and a bow of 4mm. For 150mm wafers, the limit lies at approx. 70&#181m. When thinner wafers need to be processed, a wafer support system allows for backside. Special care must be taken for thermal management during sputter deposition forming the backside metal layer stack. In combination with the unique in-situ temperature measurement system such supported thin wafers can be run safely and reliably.

    Hans Hirscher, Ph. D. process engineering scientist, and Hans Auer, product marketing manager PVD, may be contacted at Oerlikon Systems, Balzers, Liechtenstein. www.oerlikon.com.

    • Mask costs are rising ever higher to support deep sub-wavelength imaging, and now represent a significant component of the cost of lithography, Mark Melliar-Smith, CEO of Molecular Imprints, tells SST senior technical editor Debra Vogler. He expects the trend will dramatically worsen over the next couple of years as the industry pushes down to sub-40nm dimensions, at which point double patterning will double the cost impact of masks. “EUV masks are likely to be even more expensive due to the new blank and inspection technologies required,” he notes.

    Imprint lithography is able to use the standard photomask technology of today and does not require double patterning, Melliar-Smith points out. “Recent results from companies such as DNP have shown that sub-25nm imaging is achievable today using standard industry mask processing equipment.”

    Hear more about the company’s work to develop a 1X mask infrastructure during Melliar-Smith’s interview, below.

    A quality-systems-based approach to drug manufacturing ensures compliance with cGMPs

    By David M. Bliesner, Delphi Analytical Services

    In January 2001, the U.S. Food and Drug Administration (FDA) issued the Compliance Program Guidance Manual (CPGM) 7356.002 titled “Drug Manufacturing Inspections (Pilot Program).” This manual provided guidance to FDA personnel for conducting inspections of pharmaceutical manufacturing sites in an efficient and structured fashion.1 The objective of this manual was to implement a quality systems-based approach to enforcing 21 CFR parts 210 and 211, the current Good Manufacturing Practice (cGMP) regulations.2 In February 2002, FDA formally adopted this guidance manual and in August of that same year announced the Pharmaceutical cGMPs for the 21st Century Initiative. This initiative explained the agency’s intent to integrate quality systems and risk management approaches into all its existing programs, the goal of which was to encourage industry to adopt more modern and innovative technologies. Subsequently, in September 2006, FDA issued guidance to the industry entitled “Quality Systems Approach to Pharmaceutical CGMP Regulations.”3 This guidance document built upon the principles delineated in CPGM 7356.002 and bridged the gap between cGMPs and the current industry understanding of quality systems.

    The guidance describes in a straightforward manner a comprehensive quality systems model for manufacturing drugs, which, if properly implemented, ensures not only compliance with the cGMPs but ensures manufacturers provide high-quality drug product to patients and prescribers. The bottom line is that a quality systems-based approach to drug product manufacturing is just good business. As in CPGM 7356.002, the guidance document describes an inspectional model that divides the operations of pharmaceutical manufacturing into six systems. These include the quality system, the packaging and labeling system, the production system, the facilities and equipment system, the materials system, and the laboratory control system. The diagram shows the relationship among these six systems. Note that the quality system provides the basis for the other five manufacturing systems that are linked and function within it.

    Of these five “inner” systems, the laboratory control system remains perhaps one of the most difficult to understand and master and leads to numerous quality failures. A cursory review of warning letters listed on the FDA web site (http://www.fda.gov/foi/warning.htm) shows that the laboratory is rarely not part of the regulatory action.

    To continue reading this article, click here

    Tim Farrell, distinguished engineer at the semiconductor R&D center at IBM, discusses joint work with Mentor Graphics to implement comprehensive computational scaling. The two companies have been working together since the 130nm node; last September (9/17/08), they announced a development program for computational lithography at the 22nm node.

    It is IBM’s intent to look to computation scaling to take the industry to the next couple of process nodes. One of several challenges at 16nm, noted Farrell, is that electromagnetic field effects will be unavoidable; advances in the mask fabrication process will be required to address them.

     

    February 20, 2009: The US Environmental Protection Agency will, beginning in March, enforce a requirement that companies file premanufacture notices if they manufacture or import carbon nanotubes, according to a summary of an article in the Bureau of National Affairs’ Daily Environment Report.

    The report quotes Jessica Barkas, an attorney from the EPA’s Chemical Control Division, as saying the agency is placing conditions — such as development of toxicity data, requiring carbon nanotubes to be embedded in a polymer or metal structure and requiring workers to use protective equipment — on firms that want to make new nanoscale chemicals.

    Lynn Bergeson, an attorney speaking at a nanotech law conference this week, said the EPA considers carbon nanotubes to be “chemical substances distinct from graphite or other allotropes of carbon listed on the [Toxic Substances Control Act] Inventory.”

    Barkas also said the EPA will eventually shift from its “current focus of collecting information to a focus of controlling risks.”

    Feb. 17. 2009 – University research consortium Semiconductor Research Corp. has brought onboard European nanoelectronics R&D consortium IMEC to join work in creating “environmentally friendly” processes and materials for advanced semiconductor manufacturing.

    The memorandum of understanding (MOU), combining the materials and process strengths of SRC’s university reach with IMEC’s deep submicron IC process technology/devices, will target two objectives: creation of leading-edge technologies that protect the environment, and more effective processes for lowering the costs of chip manufacturing. Work will be conducted between IMEC and the joint SRC/SEMATECH Center for Environmentally Benign Semiconductor Manufacturing (CEBSM), a group started up in 1996 by the U. of Arizona (lead institution), MIT, Stanford, and UC-Berkeley (and now also including Cornell, Arizona State, MIT’s Lincoln Labs, and Maryland).

    The proposed first phase of the project will focus on sustainable cleaning and surface preparation of new materials and nanostructures, including integration of new channel and gate materials (e.g., Ge and III/V precursors), and establishing options for minimizing emissions and decreasing usage of chemicals, water, and energy. Also addressed will be in-line and real-time approaches for monitoring efficacy of nanostructure cleaning processes.

    A second phase will explore sustainable high-performance material planarization processes, aiming to advance design and feasibilty of process options that eliminate release and discharge of nanoparticles in manufacturing waste streams.

    Gains made in advancing semiconductor technology (speed, performance, scaling) have also placed greater demand on maintaining environmental aspects in the form of ever-cleaner methods and materials, noted Larry Sumney, president and CEO of SRC, in a statement. “By joining forces with CEBSM’s experts, we will be able to complement our advanced semiconductor scaling research with ESH aspects already at a very early stage of researching new processes and materials for the next-generation IC technologies,” added IMEC president/CEO Gilbert Declerck.

    Feb. 17, 2009: Scanning headlines from Japan this week: the Mirai project’s blazing SRAM simulations; Toshiba and Fujitsu’s HDD handoff, Renesas’ rebellious union; and what might be the next fullerene.

    Mirai vaults SRAM sim over the “brick wall”

    Japan’s Mirai project (Millennium Research for Advanced Information Technology) and software firm Jedat say they have devised a simulation tool that predicts SRAM chip operation much faster than conventional methods, without requiring prototypes and paving the way to better yields, notes the Nikkei Business Daily.

    Three years ago Mirai launched a “Robust Design of Transistor” project to figure out manufacturing processes and design structures that overcome the “Red Brick Wall” of transistor variability, which increases as circuit dimensions are scaled down and is a limiting factor in system chip integration. Part of their work involved evaluating variability in such robust transistors, using a “test element group” (TEG) on a 200mm wafer with 65nm-based SRAMs; measuring characteristics of each transistor determined normal distribution of variation, which could then be plotted independently by chipmaker and manufacturing technology used.

    Combining these data and the information about the actual SRAM structure, Mirai came up with a method to precisely simulate a 256kbit SRAM’s operations, predicting the chip’s behavior to the degree of the chip’s actual measurements. But the simulation was “extremely time-consuming,” the paper notes.

    Enter Jedet, which says it can accelerate the process through a proprietary method called “sample screening through boundary learning,” which reduces the amount of data needing to be processed. The result is a SRAM simulation tool that generates results 600× faster than the conventional Monte Carlo method of semiconductor device simulation. For designers, this means they will be able to use the TEGs, not fabricated SRAM prototypes, to analyze transistor variability and predict SRAM operations, and correct design flaws at the process development stage, thus resulting in better yields once chips are manufactured.

    Toshiba buying Fujitsu’s HDD ops

    Toshiba is said to be purchasing Fujitsu’s hard-disk drive operation; neither firm indicated a monetary value for the transaction that is slated to close by the June quarter, but reports suggest a pricetag of ¥30B-¥40B (US ~$330M-$430M).

    Under proposed terms, Toshiba will take a ~80% stake in the entity, which comes with production facilities in Thailand and the Philippines, and should absorb it entirely as a wholly owned unit within a year or two, notes Japan’s Nikkei daily.

    For Toshiba, the move boosts its production footprint and lowers procurement costs for items such as magnetic heads and disks, the paper notes. The company also will utilize Fujitsu’s high-speed data read/write technology for its solid-state drives, an area in which it projects sales surpassing ¥100B/year by fiscal 2010. Fujitsu’s strong position in servers offers inroads here too, the paper notes. Overall, the Toshiba+Fujitsu HDD operation will command about 20% market share (they ranked 4th and 6th, respectively, according to data cited by the paper).

    For Fujitsu, the deal (and a simultaneous sale of magnetic disk production to Showa Denko) spells the end of its magnetic head production and hard-drive related hardware. It will take a ¥30B writedown for the sale to Toshiba (split evenly between facilities/assets and personnel, the Japanese paper notes), pushing net losses to roughly ¥50B for the fiscal year ending in March, vs. a ¥48B profit in the previous fiscal year.

    Renesas breaking union ranks?

    A rebellious move from Renesas Technology’s labor union concerning springtime “shunto” pay negotiations could have reverberations across other unions and industries across Japan, according to the Nikkei daily.

    Renesas workers won’t join the Electrical Electronic & Information Union’s unified demand for a >¥4500 monthly wage hike, the paper reports. The chipmaker is projected to lose about ¥200B (US ~$2.18B) in the current fiscal year.

    The 8000-strong Renesas union is a core member of the influential industrial trade union umbrella group, the paper notes — thus, others including Oki Electric’s union are seen likely to follow suit.

    The move is uncommon but not unprecedented, particularly in these times. Similarly, Mitsubishi Motors Corp.’s union won’t demand a payscale raise, in opposition to the Confederation of Japan Automobile Workers’ Unions stance on springtime wage negotiations.

    Cheaper, flexible organic memory via inkjet

    Nissan Chemical Industries and Kyushu U. have codeveloped a process to fabricate organic memory devices from inkjet printing, with application seen in smart tags, reports the Nikkei Business Daily.

    The material is a polystyrene-gold dust combination of nanoparticles deposited by inkjet onto a substrate “sandwiched” between Al thin-film electrodes. Data stored as “on” and “off” states are variably set by exposing the material to different voltages; three 5V pulses sets it to a low-resistance state, while a >10V pulse sets it to a high-resistance “off” state. The gold particles make contact with the branched ends of the polystyrene resin’s molecular structure, enabling stable resistance value so the device can function as nonvolatile memory and retain data. The devices when fabricated are said to cost a tenth of that of silicon memory, the paper notes.

    Only 2500b/cm2 is achievable now, but Nissan Chemical aims to improve this before market readiness, seen in fiscal 2010. The bendable devices can be printed onto films such as food wrapping, conceivably recording information to aid delivery and traceability. The company also wants to add an antenna to make a contactless smart tag akin to an RFID device that can be controlled with radio signals to read/write data from an external unit.

    Nippon Mining strips FPD film biz

    Seeing no demand rebound on the horizon and thus no profitability, Nippon Mining & Metals says it will exit the market for chip-on-film substrates for flat-panel televisions sometime this year, according to the Nikkei daily.

    For about five years the company has produced and shipped samples of a double-layer copper foil laminate on plastic film upon which can be mounted semiconductor devices. But demand has slumped in step with sales of flat-panel TVs as well as prices for the materials.

    A new carbon substance?

    Reseachers at Tohoku U. say they’ve discovered via computer simulation a brand-new substance made entirely of carbon atoms, joining well-known structures like fullerenes and carbon nanotubes. Results are published in the current issue of Physical Review Letters.

    The new substance, a three-dimensional structure comprised of rings of 10 carbon atoms, is similar to that of a geometrically proposed structure called a “K4” crystal; Evaluations by supercomputers using “first principles calculations” method show the structure’s metallic properties should conduct electricity. Prof. Tadafumi Adschiri et al. are currently testing synthesis of the substance; their work is sponsored by the Japan Science and Technology Agency.

    The list of substances made solely of carbon is a short one: diamond, graphite, amorphous carbon, and more recently fullerenes and carbon nanotubes. The new substance has a 3D crystal structure like diamond, and is the first to also have metallic properties. A group led by Tadafumi Adschiri, a professor of chemical engineering, has begun testing synthesis of the substance. (It’s worth noting that the fullerene, too, led a hypothetical mathematical existence until it was proven to exist in nature as the C60 molecule.)

    February 13, 2009: NanoInk has introduced its next generation Dip Pen Nanolithography system for desktop nanofabrication, the DPN 5000.

    Having evolved from the popular NSCRIPTOR DPN System, this new instrument brings greater control and performance to the world of desktop nanofabrication, the company announced in a news release.

    The company said the DPN 5000 offers versatile nanopatterning capabilities coupled with high-performance AFM imaging for immediate characterization of the deposited patterns. NanoInk has developed a variety of custom MEMS-based ink delivery devices, allowing a wide range of materials to be deposited under precisely controlled conditions.

    System highlights include a new, ultra-low noise scanner with closed loop flexure technology to produce accurate and repeatable nanoscale patterns. For subsequent imaging of substrates, a low coherence laser with a reduced laser spot size assures high quality lateral force imaging. In addition, NanoInk’s enhanced lithography software, InkCAD 4.0, includes improved control of tip-based patterning, along with nanoscale mapping and positioning, allowing users to precisely position multiple features even when created from different materials.

    The company said the DPN 5000 comes fully equipped with a full range of enabling MEMS based ink delivery consumable items. Manufactured in NanoInk’s MEMS facility, these DPN patterning tools include single probes, 1D passive probe arrays, individually actuated Active Pen Arrays, 2D probe arrays with up to 55,000 pens (2D nano PrintArray), Inkwells for coating tips, and substrates to be written upon. These devices allow researchers to rapidly create nanostructures using numerous materials including proteins, DNA, nanoparticles, and polymers.


    NanoInk’s DPN 5000 Desktop NanoFabrication System. (Image courtesy of NanoInk)

    By Laurie Balch, principal analyst, Gary Smith EDA

    Feb. 10, 2009 – A year ago, all signs pointed to 2008 being a pretty good year for the EDA market — it was coming off of two consecutive years of 10% growth, and showing signs of fairly robust (albeit a bit lower) demand. Few could have imagined that 2008 would wrap up as the worst year by far in recent memory; initial numbers show a precipitous -16.6% overall decline.

    A major factor in this huge drop-off in market size was the abrupt deterioration of economic conditions over the course of the year. As economic uncertainties intensified and spread throughout the electronics industry, EDA users began to rapidly scale back their spending as demand for their own products became more fragile. Consequently, three of the top four EDA vendors (Cadence, Mentor Graphics, and Magma) have experienced substantial declines in revenue. Only Synopsys has managed to maintain positive growth in 2008 — a rather impressive feat in keeping its head above water this long.

    However, a weak market wasn’t the main reason for the miserable 2008 — the severity of the slide in revenue can be attributed to an accounting mess at Cadence. After restating its earnings, Cadence is poised for a revenue decline of well over 40% in 2008. The company’s “confusion” in recognizing revenue from a number of subscription license sales caused a very significant hiccup to its top-line performance.

    Cadence’s unsuccessful attempt to acquire Mentor Graphics was another key contributor to its lousy financial results. We believe that the company’s corporate leadership had been banking on the takeover of Mentor to cover its mismanagement of business fundamentals. Its core business health was likely in far more serious trouble than anyone had guessed, and the Mentor bid was a desperate attempt to regain some market strength. The accounting and management debacle has cost Cadence its top marketshare ranking (now behind both Synopsys and Mentor), and it now faces a tough road ahead to recover its former leadership spot.

    Is a recovery in sight?

    Given that the overall economy is presently deep in the throes of recession, the EDA industry isn’t yet on the cusp of an upturn, and it won’t begin seeing positive growth until the electronics industry is ready to open its wallets again. We anticipate the downturn will likely last until 3Q09, at which point EDA spending will start to gradually improve, coinciding with the broader economic recovery as confidence returns and investment dollars flow once more.

    The forecast picture is bleak through 2009 (see figure). After a -16.6% decline in 2008, the EDA market is forecast to scrape by with only about 1% growth in 2009. Once semiconductor industry growth becomes less uncertain, EDA growth should accelerate and head back into a healthy range in 2010 (10%) and 2011 (12%). Spending on design tools will once more become a priority; the need for advanced design technology is just too great in this era of rapidly shrinking IC design features and burgeoning gate counts. Note that the projected compound annual growth rate through 2013 is a mere 3.8%, due to the massive market fall-off in the near term of the forecast period.


    Worldwide EDA market forecast through 2013. Product and maintenance revenue in US $M. (Source: Gary Smith EDA)

    Future market growth drivers

    Apart from the general macroeconomic conditions, what is driving the future prospects for the EDA market is development of cutting-edge design technologies that will enable the electronics industry to take advantage of the most advanced design methodologies, processes, and materials. Though new tools have been introduced in the past few years, many methodology transformations remain yet to be introduced. Therefore, it is incumbent on the EDA industry to maintain its focus on fully developing this next generation of design tools.

    It’s no surprise that design-for-manufacturing (DFM) tools are a key element of the current EDA growth phase. This segment has become increasingly important as designs migrate to the 65nm and 45nm process nodes, where manufacturability issues become more difficult and DFM is critical to achieving successful design closure. The latest DFM issues now also require CAD tools to handle parallel processing and concurrent algorithms. These capabilities aren’t minor improvements to today’s CAD tools — they necessitate a complex and complete rewrite of today’s CAD tools that takes years of EDA development work, on top of the effort required by IC designers to implement new CAD technologies.

    The frontend of the IC design flow is also currently in the midst of an inflection point. The evolution of the electronic system level (ESL) design methodology is a bit thornier problem to address. Because an ESL-based methodology involves bridging between IC designers, system designers, and embedded software designers — groups with traditionally different design needs and tool budgets — developing a full-fledged ESL flow is no small task. Creating a full suite of ESL technologies will be a necessary step for EDA to keep adequately serving electronics designers through future semiconductor generations.

    ESL is very much in the early adopter stage, and relatively few commercial tools have emerged to date. Engineering teams are beginning to employ formal ESL tools already, but there’s much more development still to come. Even those that do use ESL technologies are only using them in a very limited fashion so far — which means there is lots of room for ESL growth ahead.

    Laurie Balch is principal analyst at Gary Smith EDA. She was previously research director in Gartner Dataquest’s design and engineering group, tracking market trends in EDA, semiconductor automated test equipment (ATE), and design-for-test (DFT). E-mail: [email protected]

    February 9, 2009: The Institute of Materials Science, based in Hanoi, is selling carbon nanotubes at half the price of international competitors, according to a report in theVietNamNet news site.

    The report said the institute’s lab can produce 100g-300g of carbon nanotubes per day, with production costs of around $0.06 per gram compared to $1 per gram elsewhere in the world.

    The article quotes Phan Ngoc Minh, the institute’s deputy director, as saying that it is difficult to commercialize carbon nanotubes in Vietnam. Minh and his team have found their first customers in the Hai Duong Pumping Machine Company and the Hung Yen Technological Teacher Training University, according to the report.