The Acoustic Surface Profile (ASP) module from Sonoscan allows its C-SAM acoustic microscopes to reveal the external surface topography of a device at the same time as its internal features. It reportedly requires no additional scanning time because profile data is taken at the same time as the acoustic image data. If a part is tilted, ASP corrects for tilt before profiling the surface.
ASP can be used to measure warpage of plastic integrated circuits, flip chips, substrates, circuit boards, etc., without any sample preparation. ASP works by collecting acoustic surface data and displaying it as a color-coded image, with each color corresponding to a topographical distance measurement. The sensitivity of the ASP is in the micron range and is not dependant upon the surface smoothness, color, or optical characteristics. ASP is available as anoption on new C-SAM acoustic microscope systems as well as a retrofit to many systems acquired over the last few years. Sonoscan, Inc. Elk Grove Village IL www.sonoscan.com
Category Archives: Materials and Equipment
(March 25, 2008) San Jose, CA — SEMI has reported that worldwide sales of semiconductor manufacturing equipment totaled $42.77 B in 2007, representing a year-over-year increase of 6%. The data is available in the Worldwide Semiconductor Equipment Market Statistics (SEMS) Report, now available from SEMI.
(March 25, 2008) Elk Grove Village, IL — Sonoscan has introduced a new capability for its line of C-SAM acoustic microscopes that reveals the external surface topography of a device at the same time as its internal features. Known as the acoustic surface profile (ASP) module, this important mode can be used to measure warpage of plastic integrated circuits, flip chips, substrates, circuit boards, etc., without any sample preparation.
Mar. 25, 2008 – Worldwide sales of semiconductor manufacturing equipment increased about 5.7% in 2007, almost entirely due to a spending splurge by Taiwan firms and to a lesser extent Korea, and underpinned by extensive memory investments and the continued ramp of 300mm wafer manufacturing, according to the latest data from SEMI.
As a region, Taiwan spent more than anyone else in 2007, increasing investments by nearly 46% to $10.64B, taking the top spot from Japan, which showed minimal growth during the year (1.1%, $9.31B). Korea moved up to third place with 4.8% growth ($7.35B), while China surged 26.2% (to $2.92B), in spending. Other regions saw their investments shrink to varying degrees: the US (-10.6%, $6.55B), which slipped to fourth among global regions; Europe, which continued to lose ground (-18.2%, $2.94B) after falling 8% in 2006; and Rest-of-World (-17.9%, $3.05B), which aggregates Singapore, Malaysia, Philippines, and other areas of Southeast Asia, plus smaller global markets.
By technology, growth was seen in sales of wafer processing equipment (11%) and assembly/packaging (15%), but there was softness in between in the test equipment sector (-21%). Other frontend equipment, including those used for mask/reticles, fabrication facilities, and wafer manufacturing, collectively increased about 2%.
Other notable trends in the data, called out by SEMI:
– The total $42.75B in capital equipment sales is the second highest ever
– China’s new equipment market is now approaching that of Europe in terms of size
– The data covers seven major semiconductor producing regions and 23 product categories.
SEMI had already suggested that preliminary chip tool sales from North American suppliers rose about 3.2% in 2007 to $18.50B, though orders dropped -9.6% to $16.63B.
by Katherine Derbyshire, Contributing Editor, Solid State Technology
Mar. 24, 2008 – It’s convenient to visualize the image created by a photomask as a binary array of bright and dark regions. Yet in the era of subwavelength lithography, scattering around mask features actually creates a grayscale image. Intensity at the center of a bright area is near maximum, intensity at the center of a dark area is near zero, but the areas in between are likely to have a smoothly varying intensity profile, with Gaussian distributions replacing sharp-edged delta functions. As a result, resist contrast defines the features actually transferred to the wafer. Above a given exposure threshold, photoacids in positive tone resist remove protection molecules, rendering the resist soluble in developer. The cleared, “bright” areas of the resist pattern are those in which exposure intensity exceeds this threshold.
Lithographers use a variety of mask enhancement features to control optical scattering and maximize image resolution. Generally speaking, though, bright areas of the mask tend to become wider due to diffraction effects, while dark areas tend to become narrower. Attempts to compensate for this behavior tend to reduce the contrast between light and dark areas, and thus the available dose margin.
When positive imaging is used to print narrow trenches, most of the mask area is dark, while the trenches appear as bright lines. Diffraction at the edges of the trench regions tends to degrade the resolution of these features. In negative imaging of narrow trenches, on the other hand, most of the mask area is bright, improving contrast at the edges of the dark trench regions.
Traditionally, Shinji Tarutani and other researchers at Fujifilm Electronic Materials Research Laboratories explained in a presentation at the recent SPIE Advanced Lithography Meeting, achieving high resolution with negative imaging has been difficult. To achieve a high dissolution rate in alkaline developer, negative tone resists incorporate polar and hydrophilic groups. Yet the cross-linking reaction which captures the exposed image may not destroy these groups. Rather, their presence can allow developer to penetrate the resist film, leading to pattern swelling, bridging, and other defects.1
Instead, Tarutani explained, the Fujifilm group focused on negative development of conventional positive-tone resist. They found that an appropriate organic solvent can attack the acid-labile groups found in unexposed areas of positive tone resist. Under these conditions, the contrast in dissolution rates between exposed and under-exposed regions depends on the molecular weight and structure of the resist. Increasing the molecular weight slows the penetration of organic solvent, reducing the dissolution rate. By using a bright mask with negative developer, the group achieved linewidth roughness (LWR) of 4.2nm in 32nm trenches (128nm pitch). Positive developer was unable to resolve these features (see Figure 1).
Figure 1: Linewidth roughness in 32nm trenches at 128nm pitch, imaged with (a) positive tone and (b) negative tone development. LWR is 4.2nm in (b). (Image courtesy Fujifilm Electronic Materials)
Though high-resolution patterning of narrow trenches is helpful, the ability to use both negative and positive development for the same resist raises even more interesting possibilities. If negative development clears the “dark” areas of the areal image, while positive development clears the “bright” areas, what about the gray regions in between?
As the Fujifilm group showed, it is possible to tune the resist imaging threshold so that some regions lie below the exposure threshold for positive development, but above the threshold for negative development. These gray areas remain intact after both positive and negative development. As shown in Figure 2, such regions occur at one-half the photomask pitch, placing an untouched resist column on either side of each mask feature. The effect is to double the pitch frequency, and thus the density of lines and spaces.
Figure 2: Pitch frequency doubling with double development. (a) regions are cleared by positive development, (b) regions by negative development, leaving (c) regions as the final resist pattern. (d) illustrates the mask pattern, while (e) and (f) are the exposure thresholds for positive and negative development, respectively. (Image courtesy Fujifilm Electronic Materials)
Double patterning is often proposed as a way to improve resolution without investing in more expensive exposure tools or more complex photomasks. For example, one proposed pitch frequency doubling scheme places a spacer on either side of a patterned hard mask. When the hard mask is etched away, the remaining spacer captures the desired pattern.
The key challenge for most double patterning approaches is cost. The spacer-based approach adds additional deposition and etch steps. Other schemes can achieve a wider variety of patterns by using two different photomasks, but the additional exposure adds even more expense. From a cost perspective, Fujifilm’s use of double development looks very promising indeed.
So far, however, the work remains at the feasibility study stage. Initial results obtained 120nm pitch line and space patterns, using 0.75 NA ArF dry exposure. Extrapolating this result to 1.35 NA immersion exposure would give 33nm half-pitch resolution, but such fine patterns have not yet been printed. — K.D.
Reference
1 Shinji Tarutani, Hideaki Tsubaki, and Shinichi Kanna, “Development of materials and processes for double patterning toward 32nm node 193nm immersion lithography process,” Proc. SPIE vol. 6923 paper no. 14 (2008; in press).
March 19, 2008 — /SAN JOSE, CA/ — North American-based manufacturers of semiconductor equipment posted $1.23 billion in orders in February 2008 (three-month average basis) and a book-to-bill ratio of 0.93 according to the February 2008 Book-to-Bill Report published today by SEMI. A book-to-bill of 0.93 means that $93 worth of orders were received for every $100 of product billed for the month.
The three-month average of worldwide bookings in February 2008 was $1.23 billion. The bookings figure is about 8 percent greater than the final January 2008 level of $1.14 billion, but 12 percent less than the $1.40 billion in orders posted in February 2007.
The three-month average of worldwide billings in February 2008 was $1.32 billion. The billings figure is about 3 percent greater than the final January 2008 level of $1.28 billion, but about 8 percent less than the February 2007 billings level of $1.42 billion.
“The three-month average for North American bookings and billings improved slightly in February, however they remain at levels below those reported last year,” says Stanley T. Myers, president and CEO of SEMI. “Though current inventory and utilization rates are at healthy levels, device manufacturers are being conservative in their Capex spending.”
The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.
Visit www.semi.org
by Katherine Derbyshire, Contributing Editor, Solid State Technology
Conferences like the recent SPIE Advanced Lithography conference focus on the leading edge — e.g.,EUV, double patterning, immersion lithography — yet process technologies remain commercially important long after the leading edge has moved on. In a presentation to investors, ASML CEO Eric Meurice noted that KrF-based lithography is used in more than 30% of the layers in 65nm node DRAMs. That number is likely to increase in the coming years as KrF displaces i-line exposure, itself used for about 40% of 65nm node DRAM layers. While these relatively mature technologies are not used for performance-critical applications, they still have a substantial effect on manufacturing yield and cost.
According to Plamen Tzviatkov, business director for advanced photoresists at Fujifilm Electronic Materials, fabs are especially interested in simplifying their KrF processes. A leading-edge process might use several different resists, optimized for different pattern structures: one for isolated lines, one for dense lines, one for contact hole arrays. The resist stack might include a bottom antireflective coating (BARC) in addition to the imaging layer itself. Yet these additional layers add cost and process complexity. Each resist increases the number of chemicals and process recipes that the fab must manage, while each unique process recipe complicates the scheduling of both wafer tracks and steppers.
Thus, Tzviatkov said, resist suppliers like Fujifilm are developing resists that can serve multiple process layers. For example, the company’s GKR5212 resist can print 220nm contact holes, dense line/space patterns, and isolated lines [see Fig. 1].
Similarly, in ion implant applications using thin resists, the GKRS-6757A resist can print dense lines, isolated lines, and isolated trenches with 125nm critical dimensions, while not requiring a BARC layer [see Fig. 2]. Innovations like these can substantially reduce the cost of KrF processes.
That’s not to say that the leading edge is not important, however. As fabs contemplate device production with immersion lithography, requirements for immersion resists are coming into focus. During early immersion development, fabs and exposure tool suppliers worried about lens contamination due to leaching of resist components into the immersion fluid. Tool suppliers mandated the use of resist topcoats. Yet leaching is a chemical problem, Tzviatkov pointed out, and is one that chemical companies like Fujifilm can and should address. Fujifilm took a topcoat-free approach to immersion resists, thereby simplifying the resist process and reducing chemical costs.
Yet merely avoiding leaching is not enough to produce a successful resist. To match dry lithography’s performance, an immersion resist must achieve comparable imaging results while avoiding such immersion-specific defects as watermarks and pattern collapse. Tzviatkov attributes Fujifilm’s success in this area to a proprietary “magic additive” that allows effective optimization of the resist’s surface properties.
Immersion resist development has been especially challenging because resist requirements have been something of a moving target. Exposure tool suppliers only recently released leaching specifications. Measurement standards for immersion defects have yet to be established, Tzviatkov said, so results presented by different laboratories cannot be compared. Though researchers are making progress, the ultimate destination remains somewhat unclear.
In the end, both mature and leading-edge processes have the same goals: superior imaging performance with minimal defects at the lowest possible cost. As processes mature, superior imaging becomes routine, allowing fabs to focus on defects and costs. To prosper, suppliers must make the transition along with them. — K.D.
March 19, 2008 — As nanotechnology aids in improving the performance of wireless handsets, the market for nanotech-enabled wireless components is expected to grow rapidly. Pioneer Consulting’s latest report, entitled, “Nanotechnology in Wireless Handsets,” forecasts that the market for nanotech-enabled components in wireless handsets will grow at a CAGR of 70% from 2007 to 2012 and will reach $15 billion by the end of 2012.
Among the various handset components, the largest market share will be for batteries, followed by displays, processors, and memories. According to the report, the only components that are currently using nanotechnology include RF and display modules, while the other components will undergo a phased introduction between now and 2012.
Aditya Kaul, senior analyst of the emerging wireless practice at Pioneer, says, “Although the short-term investments required for introducing nanotechnology into handset components are huge, the stakeholders in the handset industry will need to focus on the long-term advantages that nanotechnology has to offer.”
Kaul adds that “the cost-benefit analysis of the various nanoprocesses and nanomaterials leads us to believe that improved performance of handset components outweighs the initial investment risks taken by stakeholders. In the long-run, the incremental process and material improvements coupled with the large economies of scale will lead to lower Bill of Material costs, allowing for a subsequent ROI.”
Some of the nano processes and materials included in the report are carbon nanotubes, buckyballs/fullerenes, spintronics and quantum dots. Other product-specific nanomaterials included are hydrocarbon fuel membranes, electron based LEDs, and bulk acoustic oscillators.
(March 19, 2008) San Jose, CA — North American-based manufacturers of semiconductor equipment posted $1.23 billion in orders in February 2008 (three-month average basis) and a book-to-bill ratio of 0.93, according to SEMI’s February 2008 Book-to-Bill Report published today. A book-to-bill of 0.93 means that $93 worth of orders were received for every $100 of product billed for the month.
March 19, 2008 — Tegal Corporation has received an order for a Tegal 6540 plasma etch tool from the Pennsylvania State University. The Tegal 6540 system will be installed in the Penn State Nanofabrication Laboratory, a National Science Foundation National Nanotechnology Infrastructure Network site, where the plasma etch tool will be used to perform research on complex oxide materials.
Lead zirconate titanate (PZT), which is one of several complex oxide materials being studied at Penn State, is a piezoelectric material useful for fabricating MEMS devices such as wireless communication switches in next-generation cell phone handsets, and medical ultrasound transducers for diagnostic imaging.
According to Theresa Mayer, associate director, Materials Research Institute, and professor of electrical engineering, “Penn State University has extensive experience in the deposition, etching, characterization, and integration of complex oxide thin films for piezoelectric, pyroelectric, tunable dielectric, and electro-optic device applications. The Nanofabrication Laboratory at Penn State offers our academic and industrial users unique access to these advanced processing capabilities. The Tegal 6540 plasma etching system that we purchased will add significant new strengths—for example, the etching of thick PZT—to our growing suite of complex oxide device fabrication systems.”
The Tegal 6540 is a high-density plasma etch tool featuring the HRe- reactor, and Tegal’s patented dual-frequency RF power technology and magnetic plasma confinement. The system is a critical enabler for etching noble metal electrode and capacitor materials, including PZT, as well as other ferroelectric, magnetic, high-K dielectric, compound semiconductor, and interconnect materials.