(June 4, 2007) RESEARCH TRIANGLE PARK, N.C. — Nextreme appointed Paul A. Magill, Ph.D., as VP of marketing and business development, citing his entrepreneurial experience and background in electronics packaging and thermal management. Magill has founded several companies, such as Unitive and Avo Photonics.
Category Archives: Materials and Equipment
By Mark Danna, Owens Design, Fremont, California, USA
Much has been written recently about the escalating cost of R&D funding required by semiconductor equipment OEMs in order to stay on the IC development trajectory required by the ITRS and Moore’s Law. The gap in what is required and what can be supplied, based on the current OEM business model, has shown that this deficit could be as high as $9.3 billion by the year 2010 [1]. Unfortunately, the main focus of conversation has been on the deficit itself with little said about potential solutions to the problem other then slowing down the pace driven by Moore’s Law. If we believe this to be an accurate data point, there must be a revolutionary change in the way equipment OEMs conduct business today.
Not only must OEMs optimize the use of their internal resources, they must also look outside their own four walls for innovative solutions; they must learn from the examples of others who have already taken on this challenge and drastically reduced R&D costs by making innovative changes to the way business is conducted. Early attempts at reducing R&D costs, such as the formation of consortia and alliances such as SEMATECH have helped. In fact, it can be shown that SEMETECH has had considerable impact on slowing the growth rate of R&D costs [2]. However, do to the overall size of the gap in necessary spending, this approach has not proven to be the complete answer.
Core vs. commodity technology
R&D spending is 4
May 31, 2007 – A trio of semiconductor equipment firms have made a range of moves to shore up their balance sheets, boost capital and return profits to shareholders, through several transactions involving shares and convertible notes.
Confident in its ability to churn our profits, ASML says it will return about 960 million euros (US $1.29 billion) to its shareholders through a capital repayment (2.04 euros/share, or ~$2.75), in combination with an 8/9 reverse stock split that will reduce the number of outstanding ordinary shares by 11%. “ASML has clearly shown its ability to be profitable throughout industry cycles and generate cash above its operational needs,” said company CFO Peter Wennink, in a statement, adding that the company has determined that its debt-to-equity ratio “could be further optimized and have undertaken initiatives to address that issue.” Few details of the proposed payout or share reduction plan were disclosed, other than that shareholders will vote on the proposal at an extraordinary general meeting on July 17.
Marketwatch scanned the investor landscape, reporting that investors warmly received the news. The near-billion-euro return was nearly twice what Victor Bareno of SNS Securities had expected, and “combined with the increase in leverage, it underlines management’s focus on shareholder value and their confidence in capacity to generate positive cash flow throughout the cycle,” Bareno wrote in a research note. Merrill Lynch’s Jonathan Crossfield pointed out the move smartly allows ASML to reduce share capital without having to pay Dutch withholding tax, as it would have to do in a straight share buyback, according to Marketwatch. And Dutch broker Kempen & Co. noted the cash return will help ease pressure on the company’s shares which had been built up in anticipation of a weak 2Q07.
Meanwhile, Brooks Automation also wants to return money to its shareholders following the sale of its software division to Applied Materials, and so will use much of that ~$120 million in cash for a modified “Dutch Auction” to purchase about 6 million shares of its common stock, representing about 8% of total outstanding shares. Under terms of the offer, shareholders can tender some or all of their shares at a price between $16.50 and $19.00/share net without interest, representing a maximum 12.4% premium. Edward Grady, president/CEO of Brooks Automation, said the plan reflects the company’s belief that its stock “represents an attractive investment opportunity,” and a desire to support shareholders through a tender offer that “provides an efficient way […] to sell all or a portion of their shares as compared to market transactions.”
Elsewhere, Kulicke & Soffa Industries Inc. is proposing a $100 million offering of convertible subordinated notes due 2010, of which $40 million will be used to purchase its own shares, and the balance to retire part of other notes due in 2008. Overallotments could add another $10 million aggregate principle to the placement, which is private and not open to the general public. The notes will rank equally with existing 0.5% convertible subordinated notes due 2008 and 1.0% convertible subordinated notes due 2010, and will pay interest semi-annually, convertible upon satisfaction “of certain conditions,” the company stated.
By Tom Cheyney, Small Times Senior Contributing Editor
May 31, 2007 — A particularly compelling discussion among panelists from industry and academia at the NSTI Nanotech 2007 conference (May 21 – 24 in Santa Clara, Calif.) examined technical barriers to — and recent advancements in — nanomanufacturing. The frank exchange centered on successful integration of nanoelements with micro/nano structures and devices, and challenges to scaling up nanotech products to commercial volumes.
Several panelists emphasized the importance of drawing on the know-how of other industries, especially the semiconductor-manufacturing sector, to accelerate nanoproducts’ progress into production and the marketplace. Pointing to the chipmaking industry as “a good model to use,” MEMS industry consultant Roger Grace declared, “We need to learn from past experiences, we have to build on what we know.”
The creation and implementation of industry standards, support of R&D efforts, roadmapping, and establishment of a dedicated equipment, metrology, and packaging supplier infrastructure were among the lessons that nanomanufacturers could learn from the semiconductor community, according to Grace.
“The semiconductor model is the only one that will work for nanotechnology, with the exception of self-assembly,” said Brent Segal, COO/cofounder of Nantero. “Nanotechnology is mostly physical chemistry,” adding later that “the enemy of semiconductors is dirt. Even with the diversity of nanotechnologies, contamination control and reliability remain issues.” He mentioned that Nantero has successfully integrated its carbon nanotube-enabled NRAM devices into CMOS process flows in the Gresham, OR, chip fab operated by its partner (originally LSI Logic, now ON Semiconductor), without adding any new tools to the production line.
“How do you organize nanowires on a substrate?” asked Loucas Tsakalakos, staff scientist with GE Global Research. He reiterated the importance of understanding the controlled synthesis of “ordered nanostructures” and other fundamentals, citing materials incompatibility, alignment and positioning (vertically and horizontally), arbitrary patterns, and other technical challenges to “heterogeneous, multiscale materials and device” integration and manufacturability.
Several panelists identified metrology equipment as a “key bottleneck for advancing nanotechnology,” offering their views of specific tools and methods that have room for improvement.
Tsakalakos said that contact resistance needs to more accurately and repeatably measure nanowires, in order to determine their actual properties. Nantero’s Segal noted the challenge of measuring grain boundaries and other small structures of importance in “molecular-scale engineering.” Ahmed Busnaina, panel moderator and director of the NSF Center for High-Rate Nanomanufacturing (CHN) at Northeastern University, would welcome techniques and tools for in situ, fast measurement of defects and other anomalies over large areas, but “doesn’t see a good solution on the horizon.”
Busnaina and fellow professor Harry Stephanou of the University of Texas (Arlington) pointed out the great variety of applications and materials — and their relative immaturity — in the nano realm as well as the fragmentation of the micro/nano markets.
Stephanou urged “universities to do more than just research,” chiding higher-education institutions for the “lack of evolution in PhD programs” in the area of entrepreneurial skills. He also cited the “difficulties of having standard tools” and with the tools themselves, which makes it “less clear to know how to set up a [nano] fab,” as well as the complexities of “establishing a packaging infrastructure” because of the inherent diversity of nanotechnologies and materials.
Busnaina agreed that there is common ground between semiconductors and emerging nanoelectronics devices, but said the nanomaterials side has some key differences with the chip world, noting that specific applications have a great impact on how to develop and determine processes.
He said CHN tries to “bridge the gap between scientific research and the creation of commercial products” with the implementation of “processes and tools that will enable high-rate, high-volume, bottom-up precision manufacturing.” Part of the center’s nanoprocess standardization efforts focuses on the creation and development of what Busnaina calls “nanotemplates,” which will facilitate “guided self-assembly of nanoelements,” such as single-walled carbon nanotubes and polymers.
May 23, 2007 – Heavier capex in 1Q from several large IDMs helped push up sales as well as orders for semiconductor manufacturing equipment from North America-based suppliers, according to the latest monthly data from SEMI.
Billings in April came in just a hair under $1.60 billion, up 11.3% vs. March and 10.4% higher than April 2006. Orders were about the same level at $1.595 billion, up 12.4% month-on-month but down a fraction (-0.5%) from a year ago. The book-to-bill ratio was an even-parity 1.0, meaning that $100 worth of orders were received for every $100 of product billed for the month.
In a research note, Bill Ong, analyst with American Technology research, noted that frontend equipment bookings and shipments outpaced demand for backend tools: 12%-13% sequential growth vs. 7%-8% for backend. Memory firms are still driving the industry, and DRAM capacity pullbacks are being offset by pickup in flash capacity, and though some memory orders have been pushed out into 2H07 (the latest rumor points to Samsung) “a modest return” of foundry investments has dampened overall declines, he noted, adding that fluctuations in quarterly bookings merely reflect varied process tool lead times.
“End market demand and the memory bit demand and supply imbalances will ultimately drive capital spending needs near-term,” Ong wrote, but he believes the bookings climate will improve for frontend tool suppliers with a seasonal recovery in chip unit demand and foundry re-ordering. Meanwhile, backend toolmakers, who wallowed in a trough in 2H06, “have started to see modest signs of strength near-term as test and assembly utilization rates are increasing.”
Stanley Myers, SEMI president/CEO, said in a statement that “Updated figures also show relative equilibrium of orders and shipments over the past few months, reflecting continued market stability for North American providers of chip making equipment.” That’s just about word-for-word the same comments he made last month, after SEMI unexpectedly updated its data to fix inaccuracies, ultimately showing that actual levels of demand in both January and February were significantly lower than previously estimates, off by as much as 10%-15%.
On a quarterly basis, SEMI says overall worldwide equipment billings reached $10.75 billion, up 4% sequentially and 12% year-on-year, though bookings growth was mixed (-5% Q-Q, +6% Y-Y). Korea showed particular strength in sales, up 39% both Q-Q and Y-Y, and China also impressed with 31% Q-Q and 71% Y-Y growth. Most other regions saw flat to single-digit declines Q-Q, while Y-Y growth by region was a mixed bag.
Of particular note is the continued slide of demand from Europe: just $780 million in tool sales in 1Q07, -10% Q-Q and -16% Y-Y. And with Chinese demand continuing to surge, Europe finds itself in serious danger of finally hitting bottom, becoming the smallest worldwide market for global chip tools — only $130 million ahead of China (a 20% gap), vs. a 2.4x gap ($540 million) just one year ago.
Ong noted in his research note that frontend equipment “appears to be stabilizing” while backend tools are “showing signs of a recovery.” Sustainability of memory orders and end-market demand remains a concern, he wrote, but a decline in bookings in 1Q07 was less severe than in previous cycles, suggesting equipment companies have become better at managing their capacities and staying profitable. “We continue to expect the aggregate bookings to improve in 2H07 with foundry orders returning and offsetting the memory order pause,” he wrote.
North American equipment bookings, billings — Apr 2006-Apr 2007
Month…….Billings…….%M-M………%Y-Y……….Bookings……..%M-M……..% Y-Y………B:B…………
……………..(3-mo. avg.)………………………………….(3-mo.avg.)……………………………………..
Apr’06…………..1448.5…….8.2%……..16.9%……….1602.4…….15.7%…….60.4%……..1.11
May’06………….1452.6…….0.3%……..19.8%……….1619.0……..1.0%…….59.5%……..1.11
June’06………..1557.4…….7.2%……..35.2%……….1782.3…….10.1%…….71.7%……..1.14
July’06…………..1637.9…….5.2%……..51.9%……….1734.6…….-2.7%…….72.2%……..1.06
Aug’06…………..1742.8…….6.4%……..65.1%……….1729.7…….-0.3%…….69.6%……..0.99
Sep’06…………..1672.8……-4.0%……..53.7%……….1639.2…….-5.2%…….66.6%……..0.98
Oct’06…………..1562.9……-6.6%……..36.4%……….1468.6……-10.4%…….34.3%……..0.94
Nov’06…………..1486.1……-4.9%……..26.0%……….1426.5…….-2.8%…….30.5%……..0.96
Dec’06…………..1482.3……-0.2%……..21.1%……….1497.2……..5.0%…….31.0%……..1.01
Jan’07…………..1448.0……-2.3%……..15.0%……….1445.8…….-3.4%…….17.9%……..1.00
Feb’07………….1423.0……-1.3%……..11.3%……….1398.1…….-3.1%……..8.3%……..0.98
Mar’07(f)……….1436.4……..0.9%……….7.3%………..1419.6………1.5%………2.5%……..0.99
Apr’07(p)………1598.5……11.3%……..10.4%……….1595.2…….12.4%……-0.5%……..1.00
WaferNEWS source: SEMI
Worldwide semiconductor equipment billings, 1Q06-1Q07
(Revenues in US $M)
Region………………..1Q07………………..vs. 4Q06 (%)………………..vs. 1Q06 (%)
Europe……………………0.78………………..0.86 (-10%)………………..0.92 (-16%)
China……………………..0.65………………..0.50 ( 31%)………………..0.38 (71%)
Japan……………………..2.27………………..2.29 ( -1%)………………..2.33 (-3%)
North America…………1.79……………….1.92 (-7%)…………………..1.80 (0%)
Korea……………………..2.47………………..1.78 (39%)………………..1.77 (39%)
Taiwan……………………2.01………………..2.10 (-4%)………………..1.59 (26%)
ROW……………………….0.79………………..0.89 (-12%)………………..0.79 (0%)
TOTAL……………………10.75……………..10.34 (4%)…………………..9.58 (12%)
by Bob Haavind, Editorial Director, Solid State Technology
A ConFab session on “Capital Equipment: Alternative Financing Models” was kicked off by Craig Ignaszewski, director of capital equipment procurement, IBM, with discussion of the rationale for leasing vs. buying equipment.
Increasing complexity in chipmaking creates greater risk of technological change and obsolescence, which can be mitigated by leasing, he explained. In some cases, equipment is not strategic, but may be useful for a short-term bubble in the market, or a new area with an uncertain future. Leasing makes sense here as well.
Once favorable operating lease treatment is negotiated, there are other benefits to the corporation, according to Ignaszewski: It accelerates the timing of free cash flow, allows alternate sources of funding, and may optimize the tax position.
Leasing also preserves operating and financial flexibility, he added. An agreement should include an early buyout option, as well as a purchase option at the end of the lease. This might include “item-by-item” selection for accessories, add-ons, or parts of a total system. There should also be a substitution capability, he suggested.
IBM also has other alternatives to leasing or buying equipment, he said. Sometimes the company works in joint development programs or does beta evaluations of new tools. Collaboration sometimes involves sharing of development expenses. The company also uses sale-leaseback arrangements, primarily for IBM-owned manufacturing equipment.
Other leasing options were discussed by Zvi Lando, VP at Applied Materials’ Israel operation.
“Metrology and inspection equipment may be the most suitable for leasing,” Lando suggested.
Metrology equipment is usually designed to operate through at least two nodes. But upgrades often can improve the equipment performance, and may be capable of carrying it through a third node. Leasing arrangements can be structured, he explained, to incorporate future upgrades. — B.H.
May 23, 2007 — Nanophase Technologies, developer of nanomaterials and advanced nanoengineered products, has filed a Form S-3 with the Securities and Exchange Commission to register 2,000,000 shares of its common stock. Nanophase plans to sell the shares primarily to raise capital to fund acquiring and installing equipment and expanding its facilities to support anticipated increases in nanomaterials volume, and for general corporate purposes.
Joseph Cross, Nanophase’s President and CEO, noted that “production equipment needs to be in place 3-6 months before the orders can be filled and there is a lengthy procurement and build cycle for custom equipment. Recognizing this, the management team and the board of directors believes it is prudent to secure capital during 2007. We plan to use the capital generated from the sale of securities for corporate purposes, including, without limitation, funding equipment and facilities required for expected growth.”
May 22, 2007 – Intel Corp. says that its future processors, starting with its 45nm line utilizing high-k dielectrics and metal gates (HK+MG), will incorporate 100% lead-free packaging designs, including pin grid array, ball grid array and land grid array. Next year the company plans to transition its 65nm chipsets also to 100% lead-free technology.
The chipmaker says it will use a tin/silver/copper alloy to get the last 5% of lead out of its solder joints, which connect the silicon die to the packaging substrate, using what it refers to as a “secret sauce” implementation method.
“Intel is taking an aggressive stance toward environmental sustainability, from the elimination of lead and a focus on greater energy efficiency of our products to fewer air emissions and more water and materials recycling,” said Nasser Grayeli, VP and director of assembly test technology development, Intel’s technology and manufacturing group, in a statement.
By Phil LoPiccolo, Editor-in-Chief, Solid State Technology
While the semiconductor industry continues to promise ever higher rewards — with compound annual growth rates in the high single digits for many years to come — few companies will be able to survive the increasing risks of competing in the market unless they form novel heterogeneous manufacturing alliances, similar to the research partnerships that have proven successful in managing escalating R&D costs. That was the message delivered by The ConFab’s keynote speaker Ajit Manocha, EVP and CMO of NXP, who kicked off the event on Monday and set the tone for three days of top-level executive discussions on a range of issues facing the semiconductor industry.
In his opening address, Manocha painted a picture of a rapidly expanding semiconductor market expected to nearly double in revenues this decade, from $204 billion in 2000 to $400 billion in 2011 (according to data from IC Insights and World Semiconductor Trade Statistics). “Not too many industries can provide that kind of growth,” he said, adding that among factors fueling growth is the fact that the amount of semiconductor content in electronic devices will also have risen dramatically during this period, from 10.7% in 1990 to 24.5% in 2011 (see Fig. 1, above).
Another trend that bodes well for the future is that the industry is becoming increasingly segmented, Manocha noted. There are more than 300 distinct markets, including general-purpose sectors such as memory, MPUs, optoelectronics, discretes, and analog devices, which currently make up about two-thirds of the market. Application-specific sectors such as wireless and wired communications, data processing, consumer, and automotive segments account for the remaining third (see Fig. 2, below).
Economic challenges
On one hand, this kind of application fragmentation is a positive growth factor because it means that there’s a great deal of innovation occurring, Manocha said. However, it also presents challenges to manufacturers in that it means smaller product volumes and, in the consumer era, shorter product lifecycles. Moreover, there’s a great deal of fragmentation in terms of the sheer number of competitors, many of whom account for a relatively small percentage of industry revenues. Of more than 150 chipmakers, the top 50 garner 75% of total revenues, while the middle 50 account for 20%, and the bottom 50 account for only 5%. And of all manufacturers, only three companies have annual revenues greater than $10 billion. Moreover, the same patterns hold true for both foundries and semiconductor equipment suppliers. Given this landscape, “textbooks would predict consolidation” across the supply chain through acquisition of smaller- and medium-size companies, Manocha said.
A host of other challenges, most of which have arisen only in the last decade, also threaten all but the largest firms, Manocha pointed out. Chief among these is the rising cost of fabs. In the 1990s, 200mm fabs cost about $1 billion, he noted, but today a new 300mm facility costs some $5 billion. Beyond that, prices for equipment are soaring; EUV scanners for 32nm technology, for example, will cost about $40 million apiece, he said. Also, today’s processes entail high costs associated with high-k and low-k material integration, software development, intellectual property protection, product design, test, DFM, and DFX — factors that did not exist in the last decade.
R&D and design costs have also skyrocketed in the past decade. In 2000, total R&D expenditures were about 12.7% of total industry revenues; that is seen topping 17% in 2007, and reaching nearly 20% of revenues by 2011. Moreover, if the development cost of a single 65nm or 45nm product is tens of millions of dollars, and if the revenues over the life of the product need to be 10x the R&D investment to achieve ROI, many products will have to generate revenue streams of hundreds of millions of dollars, hardly trivial in a fragmented application space.
Added to these challenges, the semiconductor business cycles will continue to undergo extreme fluctuations. Some reports claim that the demand swings will be less pronounced than in the past, Manocha said, but while it’s true that the semiconductor demand curve will now begin to track the same general pattern as the electronics equipment growth, the industry’s swings will still be an order of magnitude more pronounced than the fluctuations in the electronic industry, as well as in the world’s GDP.
Toward a new manufacturing model
So what’s the best strategy for survival in this complex semiconductor ecosystem? For one thing, it’s clear that “companies can no longer afford to play alone,” Manocha said. In fact, NXP has recently adopted an “asset-light” foundry model under which it will outsource all advanced CMOS chip production beyond 90nm to foundry giant TSMC. The foundry partnership addresses Manocha’s bottom-line concern that manufacturing has become extremely difficult with respect to capital intensity. Indeed, it may be possible for mid-tier manufacturers to raise $5 billion to build a 300mm, 100,000 wafers/month fab to compete against high-volume chipmakers bringing in >$10 billion a year, he said — but when medium size companies cannot fill 300mm megafabs with product, it will lead to massive losses that they don’t have the depth of resources to absorb.
While NXP is driving the homogenous foundry partnership model with its asset-light strategy, Manocha’s personal view is that in the coming decades this kind of partnership will evolve into a heterogeneous model to include many more players, including not only foundries but also other IDMs, fabless companies, materials and equipment suppliers, hardware and software designers, EDA firms, and even assembly and test companies and other elements in the IC supply chain.
Manocha’s vision is that this heterogeneous approach will become a complex business model that extends the type of alliances that have proven successful in managing R&D costs into the realm of manufacturing. In R&D, forming alliances among diverse players to share the costs makes sense, he said, and in manufacturing it will make even more sense going forward.”
In one possible scenario, such collaboration could take place between IDMs, fabless companies, and foundries, so that the IDMs and fabless companies could provide product designs and product load, or demand, for the foundries, while the foundries could provide process technology, Manocha explained. The partnership could also extend to equipment suppliers to provide the tools and ensure that they are performing to the best of their ability, and even to leasing, venture capital, and private equity companies to provide funding.
An added advantage from this kind of model is that a balanced portfolio of companies working together can complement each other to offset business cyclicality. A manufacturing alliance with a microprocessor manufacturer, a memory company, and several niche product players, for example, could counter demand cycles so that if one business were down one quarter, others might still be strong, so demand as a whole would not fall below the break-even point, Manocha explained. In addition, the participating companies also can benefit from economies of scale. NXP’s experience with joint ventures has been that partnerships are more effective in limiting utilization swings, and hence show better profitability over time, he said, pointing to TSMC with its staggering profit margins as a prime example.
The overall message is clearly written on the wall: “It’s time for a paradigm shift in the manufacturing business model to bring together heterogeneous companies to share the risks and potential rewards,” Manocha said. If you don’t share the risk, there’s hardly any reward, he said, but if you do share the risks, and if the alliances are managed and nurtured properly, the result can be highly rewarding for all members. — P.L.
May 17, 2007 – A Japanese firm says that adding carbon nanotubes to antistatic rubber, used to make test benches and transport trays, can improve the strength of the base material and prevent particles from scattering around the cleanroom, notes the Nikkei Business Daily.
Antistatic rubber is typically made by mixing powdered carbon with a melt of resins of polypropylene and other materials, with the final material containing ~20% carbon to help guide electricity through the rubber and prevent static charges from building up. But that much carbon content cuts the polypropylene’s strength in half, and the powdered carbon particles can loosen and scatter around the factory.
To solve this problem, Takiron Co. is mixing carbon nanotubes in with the resin melt (with precisely controlled mixing speed, time, and temperature), where the CNTs’ long thin shapes tangle to create conduits for the electricity. And the CNTs take up a lot less volume than powdered carbon (<5% vs. ~20%), which doesn't lower the strength of the polypropylene, and the CNTs don't scatter around.
Though the new CNT-rubber mixture costs 3-4x as much as conventional products, Takiron is hoping to convince customers that the fewer particles scattered around means an easier time keeping cleanrooms clean, the paper notes. The company also expects to sell the new material to other industries where static discharges are a serious concern, such as chemical factories and gas stations. A commercial version is planned for two or three years.