Category Archives: Materials and Equipment

Alpha and Omega Semiconductor Limited (AOS) (Nasdaq: AOSL), a designer, developer and global supplier of a broad range of power semiconductors and power ICs, today introduced the TO-Leadless (TOLL) package in combination with 40V Shield-Gate Technology (SGT) to provide the highest current capability in its voltage class. The TOLL package has the highest current capacity because of AOS’ innovative technology which utilizes a clip to achieve the 400A DC at 25°C capability. The TOLL packaging technology offers very low package resistance and inductance due to the clip technology in comparison to other TO-Leadless packages using standard wire-bonding technology which enables improved EMI performance.

The AOTL66401 (40V) has a 30% smaller footprint compared to a TO-263 (D2PAK) package, including having higher current carry capability that enables the designer to reduce the number of devices in parallel. This new device offers a higher power density in comparison to existing solutions, and is ideally suited for industrial BLDC motor applications and battery management to reduce the number of MOSFETs. The AOTL66401 has a 0.7mOhm max rating at 10Vgs with a maximum drain current of 400A at 25°C and 350A at 100°C case temperature. The pulsed current is rated at 1600A, which is limited by the maximum junction temperature of 175°C.

“With the significant performance improvement, the TOLL with clip technology is a robust package which enables low package parasitics reducing EMI. The AOTL66401 simplifies new designs with the higher current density to enable savings in overall system cost due to a reduced number of devices in parallel. AOS’ TOLL package is best suited for high power applications,” said Peter H. Wilson.

IC Insights’ September Update to The McClean Report shows that as a result of a 51% forecasted increase in the China pure-play foundry market this year (Figure 1), China’s total share of the 2018 pure-play foundry market is expected to jump by five percentage points to 19%, exceeding the share held by the rest of the Asia-Pacific region. Overall, China is forecast to be responsible for 90% of the $4.2 billion increase in the total pure-play foundry market in 2018.

Figure 1

With the recent rise of the fabless IC companies in China, the demand for foundry services has also risen in that country.  In total, pure-play foundry sales in China jumped by 26% last year to $7.5 billion, almost triple the 9% increase for the total pure-play foundry market.  Moreover, in 2018, pure-play foundry sales to China are forecast to surge by an amazing 51%, more than 6x the 8% increase expected for the total pure-play foundry market this year.

Although all of the major pure-play foundries are expected to register double-digit sales increases to China this year, the biggest increase by far is forecast to come from pure-play foundry giant TSMC.  Following a 44% jump in 2017, TSMC’s sales into China are forecast to surge by another 79% in 2018 to $6.7 billion. As a result, China is expected to be responsible for essentially all of TSMC’s sales increase this year with China’s share of the company’s sales more than doubling from 9% in 2016 to 19% in 2018.

As shown in Figure 2, much of TSMC’s sales surge into China has come over the past year, with 2Q18 sales into the country being almost double what they were in 3Q17.  A great deal of the company’s recent sales surge into China has been driven by increased demand for custom devices going into the cryptocurrency market.  It turns out that many of the large cryptocurrency fabless design firms are based in China and most of them have been turning to TSMC to produce their advanced chips for these applications.  It should be noted that TSMC includes its cryptocurrency business as part of its High-Performance Computing segment.

Figure 2

While TSMC has enjoyed a great ramp up in sales for its cryptocurrency business over the past year, the company has indicated that a slowdown is expected for this business in the second half of this year.  It appears that the demand for cryptocurrency devices is highly dependent upon the price for the various cryptocurrencies (the most popular of which is Bitcoin).  As a result, the recent plunge in the price for Bitcoins (going from over $15K per Bitcoin in January of this year to less than $7K in September), and other cryptocurrencies as well, is lowering the demand for these ICs.  Moreover, since TSMC realized from the beginning that the cryptocurrency market was going to be volatile, the company did not adjust its capacity plans based on the recent strong cryptocurrency demand and does not incorporate cryptocurrency business assumptions into its forecasts for future long-term growth.

Today KLA-Tencor Corporation (NASDAQ : KLAC ) announced two new defect inspection products designed to address a wide variety of integrated circuit (IC) packaging challenges. The Kronos™ 1080 system offers production-worthy, high sensitivity wafer inspection for advanced packaging, providing key information for process control and material disposition. The ICOS™ F160 system examines packages after wafers have been diced, delivering fast, accurate die sort based on detection of key defect types—including sidewall cracks, a new defect type affecting the yield of high-end packages. The two new inspection systems join KLA-Tencor’s portfolio of defect inspection, metrology and data analysis systems that help accelerate packaging yield and increase die sort accuracy.

KLA-Tencor’s new Kronos™ 1080 wafer inspection system and ICOS™ F160 die sorting and inspection system are designed to address a wide variety of IC packaging challenges.

“As chip scaling has slowed, advances in chip packaging technology have become instrumental in driving device performance,” said Oreste Donzella, Senior Vice President and Chief Marketing Officer at KLA-Tencor. “Packaged chips need to achieve simultaneous targets for device performance, power consumption, form factor and cost for a variety of device applications. As a result, packaging design has become more diverse and complex, featuring a range of 2D and 3D structures that are more densely packed and shrinking in size with every generation. At the same time, the value of the packaged chip has grown substantially, along with electronics manufacturers’ expectations for quality and reliability. To meet these expectations, packaging manufacturers, whether in the back end of a chip manufacturing fab or in an outsourced assembly and test (OSAT) facility, have demanded more sensitive, cost-effective inspection, metrology and data analysis—and more accurate identification of bad parts. Our engineering teams have developed the new Kronos 1080 and ICOS F160 systems to serve the electronics industry’s growing needs for production-worthy defect detection for a wide variety of packaging types.”

The Kronos 1080 system is designed to inspect advanced wafer-level packaging process steps, providing information on the full range of defect types for inline process control. Advanced packaging technology necessarily includes ever-smaller features, higher-density metal patterns, and multi-layer redistribution layers—all of which have increasing inspection requirements that demand innovative solutions. The Kronos system achieves its industry-leading performance through multi-mode optics and sensors and advanced defect detection algorithms. The Kronos system also introduces FlexPoint™, an advanced technology derived from KLA-Tencor’s leading inspection solutions for IC chip manufacturing. FlexPoint focuses the inspection system on key areas within the die where defects would have highest impact. Flexible wafer handling enables the inspection of high-warp wafers, frequently encountered in a package type called fan-out wafer-level packaging—an established type for mobile applications and an emerging technology for networking and high-performance computing.

After wafer-level packages are tested and diced, the ICOS F160 performs inspection and die sorting. Manufacturers of high-end packages, such as those used for mobile applications, will benefit from new capability to detect laser-groove, hairline and sidewall cracks. These cracks result from a change in the materials used to insulate the dense on-chip metal routing to facilitate increased speed and reduced power consumption. The new material is brittle, making it susceptible to cracks during wafer dicing. Sidewall cracks are notoriously difficult to detect, as they lie perpendicular to the top of the die and are not detectable using traditional visual inspection. Another major advantage of the ICOS F160 system, beneficial to many packaging types, is its flexibility: input and output modes can be wafer, tray or tape. The system is easily changed from one configuration to another. Its automatic calibrations and precision die pickup facilitate increased tool utilization in high volume manufacturing environments.

The Kronos 1080 and ICOS F160 systems are part of KLA-Tencor’s portfolio of packaging solutions designed to address inspection, metrology, data analysis and die sorting needs for a variety of IC packaging types.

SEMI today announced that all legal requirements have been met for the ESD (Electronic Systems Design) Alliance to become a SEMI Strategic Association Partner.

Full integration of the Redwood City, California-based association representing the semiconductor design ecosystem is expected to be complete by the end of 2018. The integration will extend ESD Alliance’s global reach in the electronics manufacturing supply chain and strengthen engagement and collaboration between the semiconductor design and manufacturing communities worldwide.

As a SEMI Strategic Association Partner, the ESD Alliance will retain its own governance and continue its mission to represent and support companies in the semiconductor design ecosystem.

The ESD Alliance will lead its strategic goals and objectives as part of SEMI, leveraging SEMI’s robust global resources including seven regional offices, expositions and conferences, technology communities and activities in areas such as advocacy, international standards, environment, health and safety (EH&S) and market statistics.

With the integration, SEMI adds the design segment to its electronics manufacturing supply chain scope, connecting the full ecosystem. The integration is a key step in streamlining SEMI members’ collaboration and connection with the electronic system design, IP and fabless communities. The Strategic Association Partnership will also enhance collaboration and innovation across the collective SEMI membership as ESD Alliance members bring key capabilities to SEMI’s vertical application platforms such as Smart Transportation, Smart Manufacturing and Smart Data as well as applications including AI and Machine Learning.

“The addition of ESD Alliance as a SEMI Strategic Association Partner is a milestone in our mission to drive new efficiencies across the full global electronics design and manufacturing supply chain for greater collaboration and innovation,” said Ajit Manocha, president and CEO of SEMI. “This partnership provides opportunities for all SEMI members for accelerated growth and new business opportunities in end-market applications. We welcome ESD Alliance members to the SEMI family.”

“Our members are excited about becoming part of SEMI’s broad community that spans the electronics manufacturing supply chain,” said Bob Smith, executive director of the ESD Alliance. “Global collaboration between design and manufacturing is a requirement for success with today’s complex electronic products. Our new role at SEMI will help develop and strengthen the connections between the design and manufacturing communities.”

All ESD Alliance member companies, including global leaders ARM, Cadence, Mentor, a Siemens business, and Synopsys, will join SEMI’s global membership of more than 2,000 companies while retaining ESD Alliance’s distinct self-governed community within SEMI.

By Laith Altimime

In a bid to reinvigorate Europe’s electronics strategy and strengthen the region’s position in key emerging technologies, European electronics industry CEOs in June called on public and private actors to accelerate collaboration at the European Union and national levels. The CEO’s proposed new strategic actions include creating a European Design Alliance to pool the expertise of design houses and forming an electronics education and skills task force consisting of representatives from industry, research, European institutions, member states and SEMI.

The business executive’s calls – embodied in “Boosting Electronics Value Chain in Europe,” a report submitted to Mariya Gabriel, Commissioner for Digital Economy and Society, of the European Commission – come as global competition in the electronics industry intensifies. The document highlights Europe’s need to buttress its position amongst others in artificial intelligence (AI), autonomous driving and personalized healthcare – applications that rely on new semiconductor architectures, materials, equipment and design methodologies.

The European semiconductor industry plans to pour more than 50 billion EUR into technology development and innovation by 2025, deepening its investments in research, innovation and manufacturing to help drive Europe’s digital transformation.

For its part, SEMI, as the industry association connecting the electronics value chain, is well-positioned to bring together member companies and public actors to address key challenges facing the sector. This year in April, SEMI announced that Electronics System Design Alliance (ESD Alliance) will join SEMI, adding key electronics design companies to SEMI membership and unlocking the full potential of collaboration between electronics design and manufacturing.  With the ESD Alliance, SEMI adds the product design segment to the electronics supply chain, streamlining and connecting the full ecosystem. The integration also promises to support the industry coordination required to develop specialized (AI) chips used in various smart applications.

SEMI Europe is also accelerating its education and workforce development activities. SEMI Europe this year created its Workforce Development Council Europe, chaired by Emir Demircan, SEMI Europe’s senior manager of public policy, based in Brussels. The council is designed to connect electronics industry human resources representatives with members to evolve best practices in hiring that help Europe gain, train and retain world-class talent.

Other SEMI Europe workforce development activities include the following:

  • SEMI member forums across Europe are helping young talent with career opportunities in the semiconductor industry.
  • In November, SEMICON Europa will host a Career Café where STEM students will explore careers in electronics design and manufacturing.
  • With the participation of representatives from the European Commission, SEMI Europe’s Industry Strategy Symposium in April focused on strategies for attracting more skilled workers into electronics design and manufacturing.

Looking ahead, semiconductor sales is forecast to reach USD 1 trillion by 2030. The global semiconductor industry is at the heart of a new era of connectivity, developing breakthrough solutions for ascendant data-driven technologies such as AI and Internet of Things (IoT). SEMI Europe’s role in strengthening the region’s position in the global electronics industry to help drive this extraordinary growth is critical. SEMI Europe will continue to foster public-private partnerships to tackle industry challenges that are too big, too risky and too costly for companies and government institutions to address alone.

Contact: Laith Altimime, President, SEMI Europe, [email protected] ; Emir Demircan, Sr Manager Public Policy, [email protected]

Originally published on the SEMI blog.

A new manufacturing technique uses a process similar to newspaper printing to form smoother and more flexible metals for making ultrafast electronic devices.

The low-cost process, developed by Purdue University researchers, combines tools already used in industry for manufacturing metals on a large scale, but uses the speed and precision of roll-to-roll newspaper printing to remove a couple of fabrication barriers in making electronics faster than they are today.

Roll-to-roll laser-induced superplasticity, a new fabrication method, prints metals at the nanoscale needed for making electronic devices ultrafast. Credit: Purdue University image/Ramses Martinez

Cellphones, laptops, tablets, and many other electronics rely on their internal metallic circuits to process information at high speed. Current metal fabrication techniques tend to make these circuits by getting a thin rain of liquid metal drops to pass through a stencil mask in the shape of a circuit, kind of like spraying graffiti on walls.

“Unfortunately, this fabrication technique generates metallic circuits with rough surfaces, causing our electronic devices to heat up and drain their batteries faster,” said Ramses Martinez, assistant professor of industrial engineering and biomedical engineering.

Future ultrafast devices also will require much smaller metal components, which calls for a higher resolution to make them at these nanoscale sizes.

“Forming metals with increasingly smaller shapes requires molds with higher and higher definition, until you reach the nanoscale size,” Martinez said. “Adding the latest advances in nanotechnology requires us to pattern metals in sizes that are even smaller than the grains they are made of. It’s like making a sand castle smaller than a grain of sand.”

This so-called “formability limit” hampers the ability to manufacture materials with nanoscale resolution at high speed.

Purdue researchers have addressed both of these issues – roughness and low resolution – with a new large-scale fabrication method that enables the forming of smooth metallic circuits at the nanoscale using conventional carbon dioxide lasers, which are already common for industrial cutting and engraving.

“Printing tiny metal components like newspapers makes them much smoother. This allows an electric current to travel better with less risk of overheating,” Martinez said.

The fabrication method, called roll-to-roll laser-induced superplasticity, uses a rolling stamp like the ones used to print newspapers at high speed. The technique can induce, for a brief period of time, “superelastic” behavior to different metals by applying high-energy laser shots, which enables the metal to flow into the nanoscale features of the rolling stamp – circumventing the formability limit.

“In the future, the roll-to-roll fabrication of devices using our technique could enable the creation of touch screens covered with nanostructures capable of interacting with light and generating 3D images, as well as the cost-effective fabrication of more sensitive biosensors,” Martinez said.

Silicon Labs (NASDAQ: SLAB), a provider of silicon, software and solutions for a smarter, more connected world, announces two new executive appointments. Daniel Cooley has been named Senior Vice President and Chief Strategy Officer. In this new role, Mr. Cooley will focus on Silicon Labs’ overall growth strategy, business development, new technologies and emerging markets. Matt Johnson, a semiconductor veteran with more than 15 years of industry experience, joins Silicon Labs as Senior Vice President and General Manager of IoT products. Both executives will report to Tyson Tuttle, CEO.

Mr. Cooley has led Silicon Labs’ IoT business for the past four years. Under his leadership, the company built an industry-leading portfolio of secure connectivity solutions, with IoT revenue now exceeding a $100 million per quarter run rate. Mr. Cooley joined Silicon Labs in 2005 as a chip design engineer developing broadcast audio products and short-range wireless devices. Over the years, he has served in various senior management, engineering and product management roles at the company’s Shenzhen, Singapore, Oslo and Austin sites. The new role leverages Mr. Cooley’s proven talents in strategy and business development.

Mr. Johnson will lead Silicon Labs’ IoT business including the development and market success of the company’s broad portfolio of wireless products, microcontrollers, sensors, development tools and wireless software. Mr. Johnson has a track record of growing revenue and leading large global teams, and he brings a deep understanding of analog, MCU and embedded software businesses to Silicon Labs. Previously, he served as Senior Vice President and General Manager of automotive processing products and software development at NXP Semiconductors/Freescale, as well as SVP and General Manager of mobile solutions at Fairchild Semiconductor.

“With these executive appointments, we are expanding our ability to execute on large and growing market opportunities in the IoT,” said Tyson Tuttle, CEO of Silicon Labs. “Together, these two talented leaders will help Silicon Labs scale the business to the next level and focus on future growth.”

Boston Semi Equipment (BSE), a global semiconductor test handler manufacturer and provider of test automation technical services, introduced today its Zeus gravity feed solution for handling pressure MEMS devices that require pressure and vacuum stimulus during testing. The system is an enhanced capability for BSE’s existing pressure MEMS handling solution and enables MEMS test cells to apply pressure and vacuum in a single test cycle.

“Our innovative design for applying a pressure stimulus to devices under test enabled us to easily integrate a vacuum stimulus,” said Kevin Brennan, vice president of marketing for BSE. “This solution is unique in the industry. Our customers can already test MEMS devices faster using the Zeus handler, and now they can test with both vacuum and pressure stimuli in a single pass through the handler. This capability is a significant boost to productivity, making Zeus-based MEMS test cells a highly cost-effective solution for pressure MEMS testing.”

The Zeus is a tri-temperature handler that can be configured with up to eight test sites. Cold temperature testing is achieved using LN2 or a BSE-designed, two-stage chiller, the MR2. The Zeus offers the features and performance needed by today’s test cells at a more affordable price point.

Bruker Corporation today announced that it has acquired JPK Instruments AG (JPK), located in Berlin, Germany. In 2017, JPK Instruments had revenue of approximately 10 million Euro. JPK provides microscopy instrumentation for biomolecular and cellular imaging, as well as force measurements on single molecules, cells and tissues. JPK adds in-depth expertise in live-cell imaging, cellular mechanics, adhesion, and molecular force measurements, optical trapping, and biological stimulus-response characterization to Bruker. Financial details of the transaction were not disclosed.

Over the past five years, Bruker has developed a life science microscopy business that specializes in advanced technologies for neuroscience, live-cell imaging, and molecular imaging, which will be further augmented by JPK’s advanced technologies and applications. Bruker’s existing fluorescence microscopy techniques include performance-leading multiphoton microscopy, swept-field confocal microscopy, super-resolution microscopy, and single-plane illumination microscopy.

“We have been making a substantial investment in advanced technologies for life science imaging, and have built up a portfolio of fluorescence microscopy products that enable biologists in research areas that require deep, fast imaging at high resolution and at low phototoxicity,” commented Dr. Mark R. Munch, President of the Bruker NANO Group. “JPK’s products and applications capabilities nicely augment our current techniques.”

Anthony Finbow, Chairman at JPK, added: “The combination of these two businesses will enable further significant advances in life science imaging and drive the state of the industry. I am delighted that we have been able to achieve this result for JPK and for Bruker.”

“The business we have built aligns well with the new strategic direction of Bruker in life science microscopy, and we are very pleased to join them,” said Dr. Torsten Jaehnke, a JPK founder and CTO. “We plan to realize a number of valuable synergies going forward.”

JPK’s BioAFM and optical tweezer product families span a range of techniques, from imaging of biological samples to characterizing biomolecular and cellular force interactions. Its NanoWizard 4 BioScience AFM combines atomic force imaging with advanced optical fluorescence imaging and super-resolution microscopy for the ultimate combination in image resolution for molecules, membranes, and live cells. In addition, the ForceRobot enables single-molecule force spectroscopy for investigating receptor-ligand interactions or small molecule-protein binding interactions. The CellHesion product brings quantitative force measurement to live cells and tissues, enabling insights in cell-substrate and cell-cell interactions. Lastly, JPK’s NanoTracker optical tweezer provides an all-optical means for molecular and cellular force experiments.

JPK’s offerings and life science applications expertise are synergistic with Bruker’s existing portfolio of advanced fluorescence microscopy products. Bruker’s Ultima family of multiphoton microscopes features proprietary photoactivation and photostimulation capabilities and deeper penetration into biological tissues, enabling advanced brain slice and intra-vital studies. Bruker’s Opterra swept-field scanning confocal fluorescence microscope provides unique live-cell imaging capabilities with unsurpassed dynamic observation of fast cellular events. Additionally, the Vutara super-resolution single-molecule localization (SML) microscope utilizes patented Biplane Imaging technology to provide high-speed, 3D super resolution for multicolor live-cell imaging and visualization of chromosome conformation. With a leading series of single plane illumination products, such as the MuVi SPIM and InVi SPIM, Bruker offers unique performance and easiest-to-use light sheet instruments featuring the combination of low phototoxicity and high-speed imaging. The combined microscopy portfolio of the two companies will enable a unique range of correlative measurements for emerging life science applications.

Optimized stepping, based on parallel analysis of die placement errors and prediction of overlay errors, can increase lithography throughput by more than an order of magnitude and deliver commensurate reductions in cost of ownership. The productivity benefits of optimized stepping are demonstrated using a test reticle with known die placement errors.

KEITH BEST, Director of Lithography Applications Engineering, Rudolph Technologies, Inc., Wilmington, Mass.

Fan out wafer and panel level packaging (FOWLP/ FOPLP) processes place individual known good die on reconstituted wafer (round) or panel (rectangular) substrates, providing more space between die than the original wafer. The additional space is used to expand (fanout) the die’s I/O connections in order to create a pad array large enough to accommodate solder balls that will connect the die to the end-use substrate.The processes used to create these redistribution layers (RDL) are similar to wafer fabrication processes, using patterns defined by photolithography, with feature sizes typically ranging from a few micrometers to tens of micrometers. The placement and reconstitution molding processes introduce significant die placement errors that must be corrected in the photolithography process to ensure accurate overlay registration among the multiple vias and distribution layers that are built up to form the RDL. The errors can be measured on the lithography tool, but this significantly impacts throughput as the measurement process for each die may take as much or more time than the exposure itself.

Current best-practice methods employ an external metrology system to measure the displacement of each die. This metrology data is converted into a stepper correction file that is sent to the lithography stepper tool, eliminating the need to measure displacement on the stepper and more than doubling stepper throughput. An important enhancement to this method, optimized stepping, varies the number of die per exposure based on a predictive yield analysis of the displacement measurements, potentially multiplying throughput 20X or more. Results obtained using a test reticle that includes intentionally displaced die pads, vias, and RDL features typical of an FOWLP/FOPLP process confirm the validity of the approach.

Introduction

Die placements on reconstituted wafer or panel substrates include translational and rotational placement errors. The pick and place process itself introduces initial error. Additional error is created in the mold process and by instability of the mold compound through repeated processing cycles. As a result, the position of the die must be measured before each exposure in the lithog- raphy system to ensure sufficient registration with the underlying layer.

Displacement errors can be measured in the lithography tool, but the measurements are slow, typically taking as much time as the exposure. Moving the measurement to a separate system and feeding corrections to the stepper can double throughput.

Optimized stepping adds predictive yield analysis to the external measurement and correction procedures and increases the number of die included in the exposure field up to a user-specified yield threshold. FIGURE 1 illustrates the exposure/measurement loop. The measurement and analysis are repeated after each layer is exposed, calculating a new set of corrections. In addition to corrections, the software engine analyzes the displacement errors to predict yield (based on a user desig- nated limit for acceptable registration error) for multiple die exposure fields of varying sizes. The method requires tight integration of the stepper and measurement system with the controlling software.

With RDL features currently reaching sizes as small as 2μm, die placement measurements and pattern overlay registration requirements are also continuing to tighten. The speed of the measurement/correction/prediction calculation for each wafer/panel is also an important consideration. It must be faster than the exposure time to avoid becoming the throughput limiting step. Note that this requirement refers to the total exposure for multiple die per field which can be much less than the time needed to expose each die individually. The metrology system used in this work (Firefly system, Rudolph Technologies) can meet these challenges and measure placement errors for >5,000 die on a 510mm x 515mm panel in less than 10 minutes.

The stepper must be able to accept externally generated corrections for translation, rotation, and magnification.

It must also have a large exposure field and the ability to automatically select different images from the reticle (masking blades), changing the size of the field for each exposure. The stepper used in this work was the JetStep system from Rudolph Technologies.

The third critical piece of the optimized stepping loop is the software engine (Discover software, Rudolph Technol- ogies) which calculates displacement corrections and predicts yield for various multi-die exposure configura- tions. It also enables statistical process control (SPC) and controls genealogy.

Balancing yield and throughput

Optimized stepping uses a reticle that includes multiple exposure fields each comprising die arrays of different sizes. In FIGURE 2 the arrays range from a single die to an 8 X 8 array of 64 die. On a wafer containing random displacement errors, the smallest overlay error will be achieved by aligning the exposure pattern for each die individually. However, this accuracy comes at a high cost of reduced throughput. Optimized stepping analyzes the measured displacement errors and calculates the number of die that will meet a designated overlay error limit for various field sizes. It then selects the combination of fields that maximizes throughput. In operation, the stepper automatically selects the correct reticle image and adjusts the field size to expose the selected array.

The yield prediction algorithm (FIGURE 3) uses a recursive splitting procedure that initially predicts yield for the largest available field. If the prediction does not meet user-defined yield requirements, it splits the field and re-evaluates the prediction, repeating this cycle for decreasing field sizes until all exposures yield satisfactory results. The user designates an aggressiveness factor (larger values mean more aggressive splits) and specifies yield requirements in an exposure shot pyramid that determines the number of failures allowed for each available field size.

Results

Optimized stepping was evaluated using a test reticle with multiple field sizes containing die that included pads, vias and RDL structures typical of FOWLP/FOPLP. The patterns included predefined offsets in some of the structures for feed forward measurement testing. Application of the corrections calculated from the die placement error measurements yielded overlay errors of < +/-3μm (FIGURE 4).

Productivity vs. yield

FIGURE 5 illustrates the potential benefits of optimized stepping applied to a panel process. In the example the panel contains approximately 4,500 die. A conventional serial process, with placement errors measured on the stepper, takes a little over six hours, including three hours for measurement and three hours for exposure. Making the measurements outside the stepper in parallel with the exposure halves the cycle time per panel to three hours, and the exposure time becomes the throughput limiting step. The third case is optimized for productivity, using larger field sizes and more relaxed yield requirements. It reduces cycle time to less than 10 minutes. The final case balances throughput against more stringent yield require- ments and results slightly higher cycle times that are still nearly an order of magnitude shorter than the conventional serial process of the first case.

Conclusion

Optimized stepping can increase lithography throughput by more than an order of magnitude and deliver commensurate reductions in cost of ownership. The method also provides a means to balance productivity (throughput) against yield, adding an extra dimension of flexibility for optimizing profitability. Optimized stepping requires a stepper that can use externally calculated corrections and automatically change field size and reticle position. The metrology system must have sufficient accuracy and speed (faster than the accelerated exposure time). The control software must be able to predict yields based on measured displacement errors and control the stepper. Using a test reticle with known displacement errors, we have verified the accuracy of the metrology system and correction procedures and demonstrated the productivity benefits of optimized stepping.

KEITH BEST is Director of Lithography Applications Engineering, Rudolph Technologies, Inc., Wilmington, Mass.