Category Archives: Materials and Equipment

CyberOptics Corporation, a global developer and manufacturer of high precision 3D sensing technology solutions, will demonstrate the first wireless sensor to combine leveling, vibration and Relative humidity (RH) measurement in an all-in-one device at SEMICON Taiwan in Taipei, September 2-4, 2015 in booth #426.

For semiconductor equipment diagnostics, qualification or preventative maintenance, the wireless, real-time, all-in-one WaferSense and ReticleSense Auto Multi Sensors (AMS) speed leveling, vibration and Relative Humidity (RH) measurement to help save time and expenses while increasing yields.

The WaferSense Auto Multi Sensor (AMS) can travel through virtually any tool with its thinner and lighter form factor and can also operate at higher temperatures for greater versatility. The ReticleSense Auto Multi Sensor (AMSR) incorporates the same combination of measurement capabilities in a reticle shaped form factor to travel anywhere a reticle travels. For these individual measurements in semiconductor fab processes, legacy methods are not real-time, can be complicated or inefficient, and can be costly when tools need to be taken off-line for various processes.

“Semiconductor fabs worldwide have relied on CyberOptics’ wireless, real-time measurement devices to improve yields and equipment uptime. Several Semiconductor OEM standards require the use of WaferSense and ReticleSense devices as the best known method (BKM) for various applications,” said Ferris Chen, Director of Sales, CyberOptics, Asia. “CyberOptics has combined two of proven measurement technologies, leveling and vibration, and added a new RH measurement capability into an all-in-one Auto Multi Sensor. This combination device provides equipment and process engineers even more convenience and saves even more time.”

SEMICON Taiwan 2015 opened today starting a three-day event drawing over 43,000 attendees from electronics manufacturing. Held 2-4 September, SEMICON Taiwan represents the huge Taiwan business potential with Taiwanese chipmakers and Outsourced Semiconductor Assembly and Test (OSAT) firms spending over $20 billion in the next two years on equipment and materials.

2015 is the 20th anniversary of SEMICON Taiwan and now draws more than 700 exhibitors and more than 43,000 attendees.  Over 500 will attend the SEMICON Taiwan Leadership Gala Dinner, one of the most important executive events for the high-tech industry in Taiwan.

SEMICON Taiwan features co-located events and technology theme pavilions focusing on IC design, MEMS, 3D-ICs, advanced packaging/testing, sustainable manufacturing, and secondary equipment.

Highlights of this year’s show include:

  • Executive Summit: With the theme “Conversation between Nobel Prize Laureate and Distinguished Leaders in Taiwan,” executives from Executive Yuan, Etron Technology, ASE Group, and NCTU will share their unique perspectives with Prof. Shuji Nakamura, 2014 Nobel Prize winner.
  • Market Trends Forum: Forum features speakers from Beijing Gaohua Securities, IDC Asia/Pacific, UBS Investment Bank, Sanford C. Bernstein, TechSearch, and SEMI, with moderation by TSMC.
  • CFO and Investor Summit: With the theme, “An Exciting Period of Growth and Mergers in the Semiconductor Industry,” the event features speakers from TSMC, DBS, National Tsing Hua University, imec, and Taiwan M&A and Private Equity Council, with moderation by EQUVO.
  • Memory Executive Summit: The Summit includes presenters from Everspin, imec, Inotera Memories, and ITRI.
  • SiP Global Summit 2015: With a strong focus on heterogeneous integration through System-in-a-Package (SiP) technology, the event features more than 20 industry leaders who will share their insights and solutions on 3D-IC, Through Silicon Via (TSV), 2.5D-IC with silicon interposer, and embedded substrate technologies. More than 500 industry professionals from around the world are expected to attend.
  • Advanced Packaging Technology Symposium: Presenters will cover market trends, product applications, and packaging/assembly solutions to advanced equipment and material development, and testing and reliability – covering the most advanced technology development directions for 3D-IC.
  • Sustainable Manufacturing Forum: Experts will address a wide variety of environment, health, safety (EHS) and sustainability topics that affect high-tech manufacturing.
  • Semiconductor Materials Forum: This is the newest forum — features topics including front-end materials for advanced semiconductor devises, advanced materials solutions for 10nm and beyond, challenges for local material manufacturers, and novel materials, and activities for advanced packaging.

For more information and online registration, visit the SEMICON Taiwan website: www.semicontaiwan.org

SEMI, the global association serving the electronics supply chain, today announced the appointment of Laith Altimime as president of SEMI Europe, effective October 1, 2015. Altimime will report directly to SEMI’s CEO, Denny McGuirk, and will lead SEMI’s activities in Europe and Middle East and North Africa (MENA).

Altimime has more than 25 years of experience in the semiconductor industry with the majority spent in Europe.  Most recently, he was senior director of business development at imec. Prior to this, Altimime held leadership positions at Altis/Infineon/Qimonda, KLA-Tencor, Communicant Semiconductor AG, and NEC Semiconductors.  He has deep experience driving multi-cultural globally dispersed teams to achieve ambitious goals in competitive and technically demanding markets.  Altimime holds a Bachelor’s of Science (Honors) degree in applied physics and semiconductors electronics from Heriot-Watt University in Scotland.

Altimime will have overall responsibility for SEMI Europe’s events, programs, membership, advocacy, and collaborative forums.  He will also be responsible for strategic development and world-class service of relationships with SEMI members as well as industry, government, academia and other local associations and constituents in Europe.  As SEMI is a global association, Altimime will provide navigation, support, and services to SEMI’s members from all regions that have electronics supply chain interest in Europe.

“Laith’s deep technical and leadership experience in semiconductor manufacturing and semiconductor equipment companies, as well as his experience at imec, make him an exceptional fit for leading SEMI Europe. Not only is imec a world-leading research center in nanoelectronics with global industrial partnerships, but it an important partner of SEMI,” said Denny McGuirk, president and CEO of SEMI.  “Laith is well positioned to lead SEMI Europe in the vibrant and rapidly evolving technology development and manufacturing ecosystem.”

“I wish Laith lots of success in his new role as president of SEMI Europe. Laith’s deep knowledge of semiconductors ─ the industry, the eco system, technology, roadmaps and strategies ─ make him extremely suited to advance the European semiconductor industry in these challenging times. I would like to thank Laith for his valuable contributions at imec and I’m looking forward to collaborate with him in strengthening Europe’s semiconductor ecosystem as President of SEMI Europe” said Luc Van den hove, President and CEO, imec.

At the 65th IEEE ECTC, several companies presented advances in thermos-compression bonding.

BY PHIL GARROU, Contributing Editor

Jie Fu of Qualcomm discussed “Thermal Compression Bonding for Fine Pitch Solder Interconnects.” Mass reflow-based interconnects, using either solder bump or Cu-column on bond on lead are the typical low-cost flip chip assembly approaches used by industry. These interconnects face challenges related to shorting and non-wets at sub 100μm pitches.

Transitioning below 100μm pitch requires a new approach, such as thermos- compression flip chip (TCFC). While TCFC provides higher accuracy bonding and allows for use of smaller solder cap which enables tighter FC pitch, it also presents new challenges. The major challenges for TCFC bonding include lower throughput and control of non-conductive paste (NCP) voids.

Overall, bond head ramp rate, temperature uniformity, peak temperature and dwell time must be fine-tuned in tandem to compensate for manufacturing tolerances and to get the desired end of line solder joint structure. In addition, controlling the temp exposure for the NCP material before NCP cure is critical to enable a robust TCFC solder joint. Too much thermal exposure and the NCP begins to cure prior to solder melting, which can leading to NCP entrapment and unreliable TCFC solder joints. Laminate surface finish is also an important variable.

In a similar study Cho and co-workers at GlobalFoundries presented “Chip Package Interaction Analysis for 20-nm Technology with Thermo-Compression Bonding with Non-Conductive Paste.” Strong market demand for finer pitch interconnects to enable higher I/O counts in a smaller form factor is driving another transition from conventional MR bonding process to thermo-compression bonding using non-conductive paste (TC-NCP). FEA simulation results for TC-NCP vs mass reflow show that TCNCP has significantly reduced thermomechanical stress at the ULK level and the bump level.

Horst Clauberg of K&S discussed “High Productivity Thermo- compression Flip Chip Bonding.” There is tremendous effort by IDMs, OSATs, materials suppliers and equipment suppliers to bring thermos-compression bonding to commercial reality. The most significant technical challenges have for the most part been solved and limited commercial production is taking place. However, relatively low throughput and high equipment cost create adoption resistance, especially in the all-important consumer market.

Thermocompression bonding can be segmented into two different processes. The first process differentiation is whether the underfill is pre-applied before the semiconductor chip is mounted or not. Pre-applied underfill comes either as a film applied to the die or as a paste applied to the substrate. In both cases the underfill must not only create a void-free bond, but also provide flux to remove oxide on the solder caps. The alternative process is thermocompression – capillary underfill (TC-CUF) where the die is underfilled in the same way as standard flip chip, except that the underfill process is much more challenging because of the more narrow bondline of a typical thermocompression bonded device. In TC-CUF, flux can be applied either by dipping the die into flux before bonding, or applying flux to the substrate.

Doug Hiner in a joint presentation between Qualcomm and Amkor presented “Multi-Die Chip on Wafer Thermo-Compression Bonding Using Non-Conductive Film.” Non-conductive films have been in development as a replacement to the liquid preap- plied underfill materials used in fine pitch copper pillar assembly.

Several assembly methods are available for chip on wafer assembly including: (1) traditional chip attach with mass reflow (MR) and capillary underfill (CUF), (2) thermo-compression bonding (TCB) of copper pillar interconnects using noncon- ductive paste (NCP) underfill (TCB+NCP), and thermocom- pression bonding of copper pillar with non-conductive film (NCF) underfill (TCB+NCF).

The TCB+NCP process carries concerns with the underfill time on stage which prevents the dispensing of the NCP material across the wafer prior to the chip bonding process. This constraint effects process costs significantly. The TCB+NCF process to date have not met the cost/benefit needs of the industry. NCF assembly provides significant improve- ments in the design rules associated with die to package edge, die to die, and fillet size. The NCF process also resolves the time on stage concerns associated with the NCP process by laminating the NCF material to the bonded die instead of to the interposer or receiving wafer surface.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that the company is experiencing strong demand for its automated 300mm polymer adhesive wafer bonding systems. Over the past 12 months, the company’s order intake has doubled for these systems, including the EVG 560, GEMINI and EVG 850 TB/DB series of wafer bonders. This includes multiple system orders from leading foundries and outsourced semiconductor assembly and test (OSAT) providers headquartered in Asia. Much of the increase in demand is being fueled by advanced packaging applications, where manufacturers are ramping up production of CMOS image sensors as well as vertically stacked semiconductors incorporating 2.5D and 3D-IC through silicon via (TSV) interconnect technology.

According to market research and strategy consulting firm Yole Developpement, the equipment market for 3D-IC and wafer-level packaging (WLP) applications is expected to grow significantly, from $933 million in 2014 to $2.6 billion in 2019 (total revenue), at a compound annual growth rate of 19 percent over the next five years*. Adhesive wafer bonding plays a critical role in supporting these applications.

Automated adhesive wafer bonding enables high yields on stacked devices
Adhesive wafer bonding is a technique that uses an intermediate layer (typically a polymer) for bonding two substrates, which is an important process technology for advanced packaging applications. The main advantages of using this approach are low temperature processing, surface planarization and tolerance to wafer topography. For CMOS image sensors, polymer adhesive bonding provides a protective barrier between the surface of the image sensor and the glass cover wafer. For 3D-IC TSV applications, polymer adhesive bonding plays an important role in temporary bonding and debonding applications, where product wafers are temporarily mounted on carriers with the aid of organic adhesives to enable reliable thinning and backside processing.

For both CMOS image sensor and stacked memory/logic applications, fully automated wafer bonding solutions are essential to support manufacturers’ migration to larger (300mm) wafer substrates to lower their overall cost of production. For example, minimizing total thickness variation (TTV) of the adhesive layer after bonding is crucial in defining the final product thickness tolerance. This ultimately has an impact on enabling thinner wafers and devices, which in turn enableshigher interconnect densities and lower TSV integration costs. EVG’s automated wafer bonding systems provide superior control of TTV and other parameters through repeatable wafer-to-wafer processing and integrated inline metrology to monitor TTV throughout the bonding process. As a result, manufacturers are increasingly turning to EVG to support their automated wafer bonding needs.

“We’ve truly entered the era of 3D-ICs, with demand for TSV wafers rising on a number of fronts—from CMOS image sensors for smart phone cameras and automotive surround view imaging, to 3D stacked memory and memory-on-logic to support high-performance, high-bandwidth applications such as networking, gaming, data centers and mobile computing,” stated Hermann Waltl, executive sales and customer support director at EV Group. “Automated wafer bonding is a critical process for supporting the volume manufacturing needs of CMOS image sensor and semiconductor device makers addressing these applications. EVG has invested years in the development of wafer bonding technology to make it a critical value-add solution for the advanced packaging market. Our breadth of knowledge in wafer bonding equipment and processes—along with our strong network of supply chain partners—has positioned us well to anticipate future industry trends and develop new solutions that meet our customers’ emerging production requirements.”

By Taylor Sholler, SEMI

With trade policy dominating headlines in recent weeks, all eyes were on Maui in the waning days of August as trade ministers from twelve nations convened for perhaps the final time to finalize the Trans-Pacific Partnership (TPP).  Such a pact between Pacific Rim economies would account for 40 percent of the world’s GDP.  However, last-minute hurdles on dairy, autos, and drug provisions proved to be the negotiators’ undoing and ministers left Hawaii with the promise of at least one more round of exhaustive deliberations in the fall.

Such is the pathway for a multilateral agreement like the TPP.  By all accounts, significant progress has been made but getting 12 countries to concur on a high-standard agreement to reduce both tariffs and non-tariff barriers has been arduous to say the least.  The business community remains optimistic nonetheless and will continue to support TPP conclusion— key for the U.S. SEM industries which export 80% of their products— later this year.

Conversely, a sector-specific trade agreement is a bit more straightforward and industry welcomed news just a week earlier that an agreement-in-principle was reached on the expansion of the Information Technology Agreement (ITA).  Originally agreed to in 1996, the ITA fosters free trade in tech and has sorely needed an update to account for the vast progress made through industrial innovation.  While this effort was not without its own obstacles, World Trade Organization (WTO) members came to an agreement in Geneva on July 24th to cut tariffs on more than 200 ICT products after more than three years of negotiations.

This deal between more than 50 nations is seen a major victory for the global economy and the semiconductor equipment and materials industries in particular. SEM-related items account of more than a dozen of the products on the expansion list, including machines and apparatus to manufacture boules, wafers, semiconductor devices and flat panel displays among other products of interest to SEMI members.

WTO trade ministers will now take the list back to their respective capitals for domestic consultations.  By November 1st, participating members must submit a draft schedule detailing their plans for national implementation.  The process should culminate during the WTO’s 10th Ministerial Conference in Nairobi in December 2015, with tariff elimination slated to begin July 2016.

The expanded agreement represents 97 percent of world trade in information technology products—an estimated $1.3 billion annual market.  However, the deal also contains a commitment to work to tackle non-tariff barriers in the IT sector, and to keep the list of products covered under review to determine whether further expansion may be needed to reflect future technological developments.

In what was already been a successful year for trade liberalization, negotiators should soon celebrate implementation of the largest WTO-driven tariff elimination deal in 19 years.  The process has breathed fresh life into the promise of sectoral trade pacts driven by market demand and targeted negotiations.  SEMI has worked closely with ITA negotiators throughout the process to ensure the inclusion of SEM items in the expanded list and this is something we hope to replicate in other market opening accords like the Environmental Goods Agreement as well.

The semiconductor supply chain is comprised of the most innovation and technologically advanced products in the world and trade agreements like the ITA play an exceedingly helpful role in the advancement of our industry.  WTO Director-General Roberto Azevedo and trade negotiators around the world should be commended for their persistence on this important expansion effort. SEMI will continue to support the great work happening in Geneva and elsewhere to remove barriers to trade and improve business operations for our members.

For a complete list of items included in the expanded ITA, please visit:  https://ustr.gov/sites/default/files/ITA-expansion-product-list-2015.pdf

For those with trade-specific questions or concerns, SEMI maintains a dedicated international policy staff, led by Jonathan Davis, Global Vice President of Advocacy ([email protected]).

Easily manufactured, low cost, lightweight, flexible dielectric polymers that can operate at high temperatures may be the solution to energy storage and power conversion in electric vehicles and other high temperature applications, according to a team of Penn State engineers.

Researcher holds flexible dielectric material. Pull out shows boron nitride nano sheets. Credit: Qing Wang, Penn State

Researcher holds flexible dielectric material. Pull out shows boron nitride nano sheets. Credit: Qing Wang, Penn State

“Ceramics are usually the choice for energy storage dielectrics for high temperature applications, but they are heavy, weight is a consideration and they are often also brittle,” said Qing Wang, professor of materials science and engineering, Penn State. “Polymers have a low working temperature and so you need to add a cooling system, increasing the volume so system efficiency decreases and so does reliability.”

Dielectrics are materials that do not conduct electricity, but when exposed to an electric field, store electricity. They can release energy very quickly to satisfy engine start-ups or to convert the direct current in batteries to the alternating current needed to drive motors.

Applications like hybrid and electric vehicles, aerospace power electronics and underground gas and oil exploration equipment require materials to withstand high temperatures. The researchers developed a cross-linked polymer nanocomposite containing boron nitride nanosheets. This material has high-voltage capacity for energy storage at elevated temperatures and can also be photo patterned and is flexible. The researchers report their results in a recent issue of Nature.

This boron nitride polymer composite can withstand temperatures of more than 480 degrees Fahrenheit under the application of high voltages. The material is easily manufactured by mixing the polymer and the nanosheets and then curing the polymer either with heat or light to create crosslinks. Because the nanosheets are tiny — about 2 nanometers in thickness and 400 nanometers in lateral size, the material remains flexible, but the combination provides unique dielectric properties, which include higher voltage capability, heat resistance and bendability.

“Our next step is to try to make this material in large scale and put it into a real application,” said Wang. “Theoretically, there is no exact scalability limit.”

STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, announced today the promotion and appointment of Dr. Han Byung Joon  as Co-President and Chief Executive Officer for the Company, together with Mr Tan Lay Koon.

Mr. Tan Lay Koon and Dr. BJ Han will both report to the Board and be jointly responsible for the management, strategy and performance of the Company.

“I am pleased that Dr BJ Han will be serving as Co-President and Chief Executive Officer with Mr Tan Lay Koon. Dr BJ Han is an experienced and effective leader who has served as our Chief Technology Officer and Head of Global Sales and Advanced Technology Marketing. I look forward to his continued contribution and leadership with Mr Tan Lay Koon,” said Mr Wang XinChao, Chairman of the Board, STATS ChipPAC.

Dr. BJ Han has been the Company’s Chief Technology Officer since 1999. He is also responsible for Advanced Technology Marketing and is the Head of Global Sales for the Company. Prior to joining us, Dr. Han worked at Anam Semiconductor, AT&T Bell Labs and IBM. He received his Doctorate from Columbia University and attended Harvard Business School’s Executive Advanced Management Program.

Within the photolithography equipment market reaching $150M in 2014, advanced packaging applications experienced the strongest growth. Yole Développement (Yole)estimates that more than 40 systems have been installed in 2014, with a compound annual growth rate (CAGR) representing 10 percent between 2014 and 2020. In the meanwhile, MEMS photolithography equipment looks set for 7 percent CAGR and LEDs 3 percent.

Yole released last month its technology & market analysis dedicated to the manufacturing process, photolithography. Under this analysis entitled “Photolithography Equipment & Materials for Advanced Packaging, MEMS and LED Applications”, the “More than Moore” market research and strategy consulting company proposes a comprehensive overview of the equipment and materials market dedicated to the photolithography step. Yole’s analysts performed a special focus on the advanced packaging area. They highlighted the following topics: current and emerging lithography technologies, technical specifications, challenges and technology trends, market forecast between 2014 and 2020, market shares and some case studies.

yole packaging july

“The advanced packaging market is very interesting and is growing dynamically as it includes many different players along the supply chain,” said Claire Troadec, Technology & Market Analyst at Yole. It encompasses outsourced assembly at test firms (OSATs), integrated manufacturers (IDMs), MEMS foundries and mid-stage foundries.
In comparison, even if the MEMS & Sensors industry is growing at a fast pace, components are also experiencing die size reduction due to strong cost pressure in the consumer market. Consequently wafer shipments are not following the same trend as unit shipments. Lastly, LED equipment growth is back to a normal rhythm, after big investments made in recent years.

Advanced packaging has very complex technical specifications. Warpage handling as well as heterogeneous materials represent big challenges to photolithography. Due to aggressive resolution targets in advanced packaging, performance must be improved. The current minimum resolution required is below 5µm for some advanced packaging platforms, like 3D integrated circuits, 2.5D interposers, and wafer level chip scale packaging (WLCSP). A lot of effort is being made to reduce overlay issues due to shifting dies and obtain vertical sidewalls for flip-chip and WLCSP. Although steppers are already well established in the packaging field, new disruptive lithography technologies are also emerging and could contribute to market growth from 2015-2016.

“Huge business opportunities in the advanced packaging market are therefore driving photolithography equipment demand,” highlighted Amandine Pizzagalli, Technology & Market Analyst at Yole. “Given the high growth rate of this market, there is no doubt that already established photolithography players and new entrants will be attracted,” she added.

yole packaging july fig 2

SEMI today announced the fourth annual European 3D Summit. Entitled “European 3D Summit 2016: Above and Beyond TSV,”  the advanced semiconductor Summit will take place on January 18-20, 2016 in Minatec in Grenoble, France.

The 2016 SEMI European 3D Summit will include a wide scope of 3D integrated circuit topics beyond Through-Silicon-Via (TSV) technology – with talks on FO-WLP/ e-WLB, Embedded Die, and 3D alternative technologies. Keynote and invited speakers will present their approaches and strategies for 3D Integration technologies, with specific attention on current adoption for applications such as memory, mobile, automobiles, wearables and more.

The increasing implementation of 3D technology in microelectronics devices has reshaped the electronics market. SEMI will highlight the latest business challenges and opportunities with a market briefing where 3D and packaging industry experts will present business and market insights. Up to 30 companies working in the 3D sector will have the opportunity to exhibit their technologies at the 3D Summit exhibition.

SEMI will provide attendees networking opportunities throughout the event, including lunches, coffee breaks, a gala dinner and a complimentary one-on-one business meeting service. New this year: SEMI will offer attendees a chance to visit the Minatec Showroom, to learn about the latest innovations being developed in the Grenoble tech hub.

The  European 3D Summit steering committee includes executives from: ams AG, BESI, CEA-Leti, Evatech, EV Group, Fraunhofer-IZM, imec,  Scint-X,  SPTS, STMicroelectronics and SUSS Microtec.

Please visit www.semi.org/European3DSummit to register as an attendee or book a booth as an exhibitor.