Category Archives: Materials and Equipment

Deca Technologies, an electronic interconnect solutions provider to the semiconductor industry, today announced that it has shipped its 100-millionth component. The company attributes this milestone to strong demand from portable electronics manufacturers for wafer-level chip scale packages (WLCSP) manufactured using Deca¹s unique, integrated Autoline production platform, which is designed to achieve faster time-to-market at lower cost.

Leveraging advanced Autoline volume production technologies from SunPower Corp., a solar technology and energy services provider, Deca achieved this milestone by addressing cycle time and capital cost challenges that semiconductor device manufacturers have struggled with using the conventional approach to WLCSP manufacturing.

Demand for WLCSP is being driven by manufacturers of wireless connectivity, audio and power management components for the handset and wearable electronics markets. Demand fluctuations in these markets can lead to challenges in managing inventories. Customers have found that Deca’s unique approach helps them better manage their inventories and reduce their working capital.

“Congratulations to the Deca team on achieving this significant milestone,” said Brent Wilson, senior vice president of the Global Supply Chain Organization at ON Semiconductor. “Deca’s innovative technologies and focus on customer service have made the company a valuable part of our supply chain. We look forward to continued shared success in the future.”

“Reaching 100 million units is an important milestone for Deca because it validates our unique approach to WLCSP manufacturing,” said Chris Seams, CEO of Deca Technologies. “Based on the demand forecasted by our customers, we anticipate passing the half-billion mark in unit shipments this year.”

“As a customer of Deca Tech, Cypress has used the fast New Product Introduction capability of Deca to streamline its back-end process and achieve cycle times of fewer than three days for full turnkey wafer-level packaging, test and singulation,” said T.J. Rodgers, president and CEO of Cypress Semiconductor Corp. “We are even more pleased with Deca as our subsidiary,” Rodgers continued. “The company’s quick ramp to the 100-million-unit milestone is proof of the value proposition that we envisioned when we invested in this market.”

Scientists from Dynaloy, LLC and EV Group will explain a new, one-step cleaning process for removing negative dry film and negative spin-on film photoresist on April 24, 2014 at the SEMATECH Surface Preparation and Cleaning Conference in Austin, Texas. Authors from Dynaloy include Technology Manager Kim Pollard, Chemist Travis Acra, and Chemical Engineer Richard Peters.

Known as CoatsClean technology, this approach to cleaning represents an improvement in process technology because it uses fewer chemicals, shortens process times, enables high wafer-to-wafer consistency, and offers process flexibility. All of these advantages come together in this process that has its own tool, the newly developed EVG-300RS.

During the presentation, researchers will explain in detail how the CoatsClean technology process works. First, coat the wafer with a small amount of a specially formulated cleaner, then heat the formulation on the wafer, and finish with a rinse. Local point-of-use heating offers flexibility by allowing different wafer types to be cleaned with the same tool in the same bowl, eliminating the cost and time involved in setting up transitions. This process works on several different wafer types for both 200mm and 300mm wafers.

“Unlike spray processes that require large quantities of liquid for cleaning, CoatsClean technology is less expensive because it involves comparatively small amounts of cleaning solution. This factor creates a lower cost of ownership and a decrease in cost per clean, two important considerations within the industry,” said Pollard.

This new process also saves time by dramatically reducing the risks associated with bath immersions that use the same liquid for multiple batches. By using small quantities of fresh liquid for each clean, CoatsClean technology allows for a consistent process that protects the pre-clean integrity of the wafer.

The presentation during SEMATECH will feature compelling visual evidence of how well CoatsClean technology removes photoresists and residue. During testing, researchers used a wet acid-based etch step to remove the copper field metal, a sensitive indicator for resist removal quality. They found no detectable irregularities in the optical microscopy images after copper field metal etching. Instead, they saw complete resist removal and a compatible copper surface finish.

Mentor Graphics Corp. today announced that its IC design to silicon solution has achieved certification for TSMC’s Design Rule Manual (DRM) and SPICE model version 1.0 for its 16nm FinFET process. The certification includes tools in the Calibre physical verification and design-for-manufacturing (DFM) platform, as well as the Olympus-SoC place and route system, the Pyxis custom IC design platform, and Eldo SPICE simulator. Mentor also successfully demonstrated a complete 16nm FinFET digital flow using the Olympus-SoC and Calibre products and the ARM Cortex-A15 MPCore processor as the validation vehicle. The Mentor 16nm solutions are available now to support customers as they transition from test chips to full production 16nm FinFET design efforts.

The Olympus-SoC place and route system enables efficient design closure with complete support for all 16nm FinFET double patterning (DP), DRC and DFM rules, fin grid alignment for macros and standard cells, and Vt min-area rules support. The new flow also supports low-voltage hold time fixing, interconnect resistance minimization, signal EM fixing, MiM Cap extraction to address timing impact, and enhanced pin accessibility and routability.

The Calibre nmDRC platform supports design teams to ensure their designs meet process requirements.  The SmartFill capability in Calibre YieldEnhancer, along with the other Mentor DFM products, Calibre LFD™ and Calibre CMPAnalyzer, were enhanced to meet TSMC-specified requirements for filling, lithography, and CMP simulations for 16FF.

The TSMC 16nm design kit offering for Mentor provides reliability checks based on the Calibre PERC™ product. This enables customers to analyze and correct issues like electrostatic discharge (ESD) and latch-up at both IP and full chip level using a common platform and set of checks regardless of the IP source.

To ensure accurate circuit simulation of FinFET devices, Mentor collaborated with TSMC on enhancement and certification of the high-performance Calibre xACT 2.5D and 3D extraction product, and FinFET device models in the Calibre nmLVS product.

The Pyxis custom IC design platform is extended to handle fin grids and provide a fin grid display, and to support guard rings, MOS abutment rules and design rule-driven (DRD) layout. The Eldo simulator has been upgraded to provide accurate FinFET device and circuit level modeling based on the latest BSIM-CMG and TMI models from TSMC.

“We’ve worked closely with TSMC to ensure our tools are ready for 16nm FinFET technology, including ongoing efforts with TSMC to optimize Calibre rule decks for the best turnaround time,” said Joseph Sawicki, vice president and general manager of the Design to Silicon division at Mentor Graphics. “By jointly evolving our products to handle 16nm FinFET requirements, we minimize the learning curve and allow designers to leverage TSMC’s offering to create differentiated value in their products.”

“The longstanding working relationship between TSMC and Mentor has allowed us to address the design requirements of 16nm FinFET, while continuing to deliver production ready solutions against an aggressive technology roadmap,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “At each new node we are proving once again that ecosystem collaboration under Open Innovation Platform is critical to driving innovation for the semiconductor design industry.”

SEMI reports that the worldwide semiconductor photomask market was $3.1 billion in 2013 and is forecasted to reach $3.3 billion in 2015. After contracting 3 percent in 2012 the photomask market increased 1 percent in 2013. The mask market is expected to grow 3 percent sequentially over the next two years. Key drivers in this market continue to be advanced technology feature sizes (less than 45 nm) and increased manufacturing in Asia-Pacific. Taiwan remains the largest photomask regional market for the fourth year in a row and is expected to be the largest market for the duration of the forecast.

Revenues of $3.1 billion place photomasks at 14 percent of the total wafer fabrication materials market, behind silicon and semiconductor gases. By comparison, photomasks represented 18 percent of the total wafer fabrication materials market in 2003. Another trend highlighted in the report is the emerging importance of captive mask shops. Captive mask shops, aided by intense capital expenditures in 2011 and 2012 and a weakening Yen in 2013, gained market share at merchant suppliers’ expense, with captive mask suppliers accounting for 49 percent of the total photomask market last year, up from 42 percent in 2012. Captive mask shops represented 31 percent of the photomask market in 2003.

A recent SEMI published report, Photomask Characterization Summary, provides details on the 2013 Photomask Market for seven regions of world including North America, Japan, Europe, Taiwan, Korea, China, and Rest of World. The report also includes data for each of these regions from 2006 to 2015 and summarizes lithography developments over the past year.  For more information on SEMI, visit www.semi.org.

The global semiconductor materials market decreased 3 percent in 2013 compared to 2012 while worldwide semiconductor revenues increased 5 percent. Revenues of $43.5 mark the second consecutive year of contraction for the semiconductor materials market.

Total wafer fabrication materials and packaging materials were $22.76 billion and $20.70 billion, respectively. Comparable revenues for these segments in 2012 were $23.44 billion for wafer fabrication materials and $21.36 billion for packaging materials. For the second year in a row, substantial declines in silicon revenue, advanced substrates, and bonding wire contributed to the year-over-year decrease to the total semiconductor materials market.

For the fourth consecutive year, Taiwan was the largest consumer of semiconductor materials due to its large foundry and advanced packaging base, despite not experiencing any annual growth. The materials market in North America also remained flat year-over-year. The materials markets in China and Europe increased in 2013, benefiting from strength in wafer fab materials. The materials market in Japan contracted 12 percent, with markets also contracting in South Korea and Rest of World. (The ROW region is defined as Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets.)

2012-2013 Semiconductor Materials Market by World Region
(Dollar in U.S. billions; Percentage Year-over-Year)

Region

2012*

2013

% Change

Taiwan

8.97

8.96

0%

Japan

8.24

7.29

-12%

South Korea

7.22

6.94

-4%

Rest of World

7.17

6.76

-6%

China

5.50

5.70

4%

North America

4.75

4.75

0%

Europe

2.95

3.07

4%

Total

44.80

43.46

-3%

Source: SEMI April 2014

Note: Figures may not add due to rounding.

* 2012 data were revised based on the recently released Global Semiconductor Packaging Materials Outlook- 2013/2014.

Altatech, a subsidiary of Soitec, has received an order from the University of Washington in Seattle for an AltaCVD chemical vapor deposition (CVD) system whose unique combination of capabilities allows users to develop new process materials with high added value. The Altatech’s CVD system will be installed at the university’s Washington Nanofabrication Facility (WNF), where it will be used by both internal and external researchers in fabricating a broad range of semiconductor-based devices including leading-edge CMOS transistors, MEMS, ICs built with the latest in through-silicon-via (TSV) technology, advanced LEDs and solar cells.

Altatech’s pulsed CVD systems are currently used extensively in R&D and pilot production facilities throughout Europe; however, the University of Washington’s order represents the first such system to be delivered to a North American university R&D and pilot production facility. The university’s acquisition of the AltaCVD system, along with recent installations of an advanced deep reactive ion etcher (DRIE) and a plasma-enhanced CVD (PECVD) tool, provides the capability to assemble an electroplated TSV fill process.

Commenting on the tool’s capabilities, Dr. Michael Khbeis, acting director of the WNF, claims, “The AltaCVD system provides a unique capability that enables researchers to deposit conformal metal films for TSV applications as well as metal oxides and nitrides for high-k dielectrics and piezoelectric materials. The higher deposition rate enabled by pulsed CVD makes ALD (atomic layer deposition) films a tractable solution for scale-up paths toward high-volume manufacturing for our researchers and industrial clients. This ensures a viable pathway from academia to real economic impact in our region.”

“Extending the use of our CVD systems into this acclaimed user facility in North America continues to demonstrate the widely recognized advantages of our pulsed deposition technology,” said Jean-Luc Delcarri, general manager of Soitec’s Altatech subsidiary. “We are very pleased to add the University of Washington to the growing list of our CVD equipment adopters.”

Altatech will support its AltaCVD installation at the University of Washington from its U.S.-based business and service operation center.

The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform ALD for exceptional 3D coverage at deposition rates matching those of more conventional CVD techniques. This allows superior stoichiometry control while creating highly conformal thin and thick films, which cannot be achieved using many of today’s existing technologies.

Altatech’s system design combines a unique vaporizer technology, gas/liquid panel integration, dual-channel showerhead and chamber design. The combination of Altatech’s proprietary reactor design and precursor introduction path with pulsed liquid injection and vaporization enables nanoscale control of film thickness, uniformity, composition and stoichiometry in complex materials.

Polymer materials are usually thermal insulators. But by harnessing an electropolymerization process to produce aligned arrays of polymer nanofibers, researchers have developed a thermal interface material able to conduct heat 20 times better than the original polymer. The modified material can reliably operate at temperatures of up to 200 degrees Celsius.

The new thermal interface material could be used to draw heat away from electronic devices in servers, automobiles, high-brightness LEDs and certain mobile devices. The material is fabricated on heat sinks and heat spreaders and adheres well to devices, potentially avoiding the reliability challenges caused by differential expansion in other thermally-conducting materials.

IMG_0695

“Thermal management schemes can get more complicated as devices get smaller,” said Baratunde Cola, an assistant professor in the George W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology. “A material like this, which could also offer higher reliability, could be attractive for addressing thermal management issues. This material could ultimately allow us to design electronic systems in different ways.”

The research, which was supported by the National Science Foundation, was reported March 30 in the advance online publication of the journal Nature Nanotechnology. The project involved researchers from the Georgia Institute of Technology, University of Texas at Austin, and the Raytheon Company. Virendra Singh, a research scientist in the Woodruff School, and Thomas Bougher, a Ph.D. student in the Woodruff School, are the paper’s co-first authors.

The new interface material is produced from a conjugated polymer, polythiophene, in which aligned polymer chains in nanofibers facilitate the transfer of phonons – but without the brittleness associated with crystalline structures, Cola explained. Formation of the nanofibers produces an amorphous material with thermal conductivity of up to 4.4 watts per meter Kelvin at room temperature.

The material has been tested up to 200 degrees Celsius, a temperature that could make it useful for applications in vehicles. Solder materials have been used for thermal interfaces between chips and heat sinks, but may not be reliable when operated close to their reflow temperatures.

“Polymers aren’t typically thought of for these applications because they normally degrade at such a low temperature,” Cola explained. “But these conjugated polymers are already used in solar cells and electronic devices, and can also work as thermal materials. We are taking advantage of the fact that they have a higher thermal stability because the bonding is stronger than in typical polymers.”

The structures are grown in a multi-step process that begins with an alumina template containing tiny pores covered by an electrolyte containing monomer precursors. When an electrical potential is applied to the template, electrodes at the base of each pore attract the monomers and begin forming hollow nanofibers. The amount of current applied and the growth time control the length of the fibers and the thickness of their walls, while the pore size controls the diameter. Fiber diameters range from 18 to 300 nanometers, depending on the pore template.

After formation of the monomer chains, the nanofibers are cross-linked with an electropolymerization process, and the template removed. The resulting structure can be attached to electronic devices through the application of a liquid such as water or a solvent, which spreads the fibers and creates adhesion through capillary action and van der Waals forces.

“With the electrochemical polymerization processing approach that we took, we were able to align the chains of the polymer, and the template appears to prevent the chains from folding into crystals so the material remained amorphous,” Cola explained. “Even though our material is amorphous from a crystalline standpoint, the polymer chains are highly aligned – about 40 percent in some of our samples.”

Though the technique still requires further development and is not fully understood theoretically, Cola believes it could be scaled up for manufacturing and commercialization. The new material could allow reliable thermal interfaces as thin as three microns – compared to as much as 50 to 75 microns with conventional materials.

“There are some challenges with our solution, but the process is inherently scalable in a fashion similar to electroplating,” he said. “This material is well known for its other applications, but ours is a different use.”

Engineers have been searching for an improved thermal interface material that could help remove heat from electronic devices. The problem of removing heat has worsened as devices have gotten both smaller and more powerful.

IMG_0728

Rather than pursue materials because of their high thermal conductivity, Cola and his collaborators investigated materials that could provide higher levels of contact in the interface. That’s because in some of the best thermal interface materials, less than one percent of the material was actually making contact.

“I stopped thinking so much about the thermal conductivity of the materials and started thinking about what kinds of materials make really good contact in an interface,” Cola said. He decided to pursue polythiophene materials after reading a paper describing a “gecko foot” application in which the material provided an estimated 80 percent contact.

Samples of the material have been tested to 200 degrees Celsius through 80 thermal cycles without any detectable difference in performance. While further work will be necessary to understand the mechanism, Cola believes the robustness results from adhesion of the polymer rather than a bonding.

“We can have contact without a permanent bond being formed,” he said. “It’s not permanent, so it has a built-in stress accommodation. It slides along and lets the stress from thermal cycling relax out.”

In addition to those already mentioned, co-authors of the paper included Professor Kenneth Sandhage, Research Scientist Ye Cai, Assistant Professor Asegun Henry and graduate assistant Wei Lv of Georgia Tech; Prof. Li Shi, Annie Weathers, Kedong Bi, Micheal T. Pettes and Sally McMenamin in the Department of Mechanical Engineering at the University of Texas at Austin; and Daniel P. Resler, Todd Gattuso and David Altman of the Raytheon Company.

A patent application has been filed on the material. Cola has formed a startup company, Carbice Nanotechnologies, to commercialize thermal interface technologies. It is a member of Georgia Tech’s VentureLab program.

eInfochips, a semiconductor and product engineering company, today launched design services for chips based on 16nm geometry.  The comprehensive suite of services includes Netlist to GDSII, Sign-off, and Design for Testability. eInfochips is one of the few engineering services companies in the world capable of delivering 16nm chip designs which reduce a chip’s power consumption by half, while improving performance by one-third over 28nm technology.

According to Frank Berry, Senior Analyst at IT Brand Pulse, “Transitioning to 16nm technology is risky and expensive. Engineering services organizations with 16nm design expertise will play an important role in helping product companies mitigate the risk, and reduce the cost of the transition.”

16nm chips will power a new generation of products that are smaller, require less power and run faster. A recent TSMC report suggests that 16nm FinFET technology will achieve 55 percent power reduction and 35 percent higher speed as compared to the standard 28nm HK/MG planar process.

In conjunction with TSMC’s announcement to support volume production at 16nm, eInfochips says it is taping-out 16nm FinFET chips for a leading semiconductor design company. That means the eInfochips design team possesses rare hands-on experience using leading EDA Tools across the silicon development cycle. The eInfochips team is also one of the few that have addressed implementation, flow enhancement (including double patterning) and Design Rule Check (DRC) errors at 16nm geometry.

“Mastering chip design at smaller geometries can only be achieved through hands-on experience.” said Parag Mehta, Chief Marketing and Business Development Officer at eInfochips. “Today, eInfochips is one of the few companies in the world that can say they have experience at 16nm.”

By Dr. Phil Garrou – Contributing Editor

The annual IMAPS Device Packaging Conference in Ft. McDowell, AZ is always a source for the latest packaging information.

Ron Huemoeller, Sr VP at Amkor indicated that they are seeing customer programs using 2.5D silicon interposers to create mixed node modules, i.e. only the circuits that require it are moving to 14nm while the rest of the circuits are remaining on a separate chip using a legacy 28nm process. Reportedly this results in a lower cost solution.

Speaking of lower cost, Tezzaron / Novati CTO Bob Patti addressed the interposer cost issue head on during a panel session when he commented that silicon interposers at Novati today will cost you 25 cents per sq. mm but they see a path to eventually get the cost down to 2 cents per sq mm.

During Qualcomm’s Steve Bezuk keynote talk on mobile packaging he noted that 7B smartphones are expected to be shipped between 2013 and 2017. With handset thickness quickly approaching 6mm and the battery and screen not shrinking, the package and board must absorb all the z direction miniaturization. Thinner substrates have been achieved so far by using thinner cores . To avoid warpage suppliers have used lower and lower CTE core materials. Since that has now run out of steam they will now be looking for low CTE materials with higher modulus to maintain stiffness.

Bzuk’s comment on 2.5/3D that “…we are not yet sure what the substrate material should be (Si, laminate or glass) or where it will be coming from…” is a sober reminder that mobile will likely not be the initial driver for TSV based technologies.

Bryan Black, Sr Fellow at  AMD brought some good news for the 3D community when he stated “Die stacking is catching on in FPGAs, Power Devices, and MEMs but there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!” He predicts that we will see 3X the bandwidth/watt using stacked memory.

AMD

As we have mentioned in previous blogs Black predicts the SiP of tomorrow will be separately optimized / manufactured  functions  stacked on an interposer. While the busses needed to connect these functions will be complex, Black is convinced that this is doable . Black indicates that AMD and partner Hynix are currently looking  for partners to develop such products.

AMD 2

Brandon Prior of Prismark reported a major move to 0.4mm pitch by 2018 (28% of all CSP/WLP) but notes that challenges remain for assembly yield and PCB routing for 0.35mm and below.  Prismark predicts that performance DDR will adopt flip chip at all of the major memory suppliers with 5B units being shipped by 2018.

Prismark

 

MKS Instruments, Inc., a global provider of technologies that enable advanced processes and improve productivity, today announced it has agreed to purchase the assets of Granville-Phillips, a division of Brooks Automation, Inc., for $87 million in cash.

Granville-Phillips is a global provider of vacuum measurement and control instruments to the semiconductor, thin film and general industrial markets, with sales of approximately $30 million in 2013. Granville-Phillips was founded in 1954, and operated as an independent company until its acquisition by Helix Technology in 1998. It became part of Brooks Automation through the merger of Helix and Brooks in 2005.

“We are very pleased to announce this acquisition,” commented Gerald G. Colella, Chief Executive Officer and President of MKS Instruments. “Granville-Phillips is an ideal complement to our vacuum gauge business, and is a business that we highly respect and know well. While we are the leader in direct pressure measurement, they are a well-regarded leader in indirect vacuum gauges, with a premium brand and an excellent reputation for quality, reliability and performance. The acquisition is well aligned with our stated strategy to grow our core semiconductor business, while diversifying into other high growth advanced markets.”

Jack Abrams, Senior Vice President Global Sales, said, “We believe we have numerous opportunities to grow the Granville-Phillips business, leveraging our existing sales channels and expanding our product portfolio. We believe we can offer a broad range of advanced vacuum gauges that will be highly responsive to the needs of customers in our served markets.”

“We see the potential for both revenue and cost synergies as we integrate Granville-Phillips into MKS,” continued Mr. Colella. “Their profitability and cash flow metrics are aligned with our own operating model, and we expect the acquisition to be accretive to our earnings in 2014. Going forward, with the revenue growth potential that we believe we can achieve with this business, as well as operating synergies to be realized over the next few years, we expect this acquisition to meet or exceed our target return thresholds.”

The acquisition is subject to regulatory approvals and other customary closing conditions and is expected to close in the second quarter of 2014.