by Paul Feeney, Axus Technology
November 22, 2011 – This year’s International Conference on Planarization/CMP Technology (ICPT) was held recently in Seoul, South Korea. Over the last few years, this international event has continued to solidify its position as the world’s largest CMP-only conference, this time covering a full three days.
Leading off the talks was a plenary by Geun-Min Choi of Hynix. The three key drivers for memory (voltage, density, and speed) were shown to be driving some of the same changes that are underway for logic, but for different reasons — for example, the drive to replacement metal gates is being driven by resistivity rather than transistor performance. Memory needs are also leading to vertical gates and spin-on dielectrics (SOG) for shallow trench isolation; Choi stressed that the overall direction for memory is away from charge-based storage to resistance or magnetic storage.
The first invited talk from Jae-Dong Lee of Samsung made similar points with different examples, stressing manufacturability and reduction of variation and defects. For STI, he looked to flowable oxide using polysilazane and for interconnects featured airgap structures for capacitance rather than resistance.
Consistent with previous years at ICPT, there was continued emphasis on some main CMP application areas such as STI and copper with ultralow-k. Various consumable suppliers touted their latest efforts in slurries and cleaning solutions for Copper. Xun Gu of Tohoku U. showed that the mechanical effect of overpolish time was a factor in the shift of keff value. The audience was also reminded of the importance of controlling DI water rinsing following the use of today’s highly chemical slurries. As expected, there were multiple papers looking at different aspects of cleaning solutions for copper. There were also papers from G&P and Samsung that studied the design of the nodules on cleaner brushes.
The emphasis of technical work in dielectric CMP, especially STI, was still present, but took a new form. Some focus remained on defect reduction through typical techniques such as filtering and improved cleaning with ceria-based processes. Many of the papers showed progress in making ceria-based polishing more efficient, which should not come as a total surprise given the enormous jump that the industry has seen in raw cerium prices. N.K. Penta of Clarkson U. studied the use of chemical additives to enable ceria solids levels to drop to 0.1% by weight. Other academics displayed results to understand the basic mechanism of ceria polishing, changing pad grooving with ceria, and even applying AC voltage to drive better distribution of ceria particles, all to improve efficiency. C.H. Lin of UMC showed that using silica-based slurries for the bulk step in STI also improved pattern factor robustness.
The conference program contained a large amount of material that demonstrated how CMP is being utilized in new applications, many of which involve new materials. The processing of through-silicon vias (TSV) was a popular theme, with information on the backside process from Cabot Microelectronics, on the front side for via middle from UMC, slurries from Anji Microelectronics, and both test chips and bonding processes from Fraunhofer Institute. There were also several papers devoted to issues in polishing of GeSbTe (GST) and Ge. Optimization of the poly-open-polish (POP) and aluminum CMP steps needed for replacement metal gates also commanded attention of many researchers. Sapphire polishing for LED’s also drew three papers. Other materials that were covered included ruthenium, cobalt, carbon nanotubes, molybdenum, Quartz, porous silicon, gallium nitride, and lithium niobate.
Another area that has gained momentum in CMP publishing has been the interaction of pads, pad conditioning, and slurries. Araca taught the audience how the radius of curvature of a pad asperity can alter dishing in copper CMP. Samsung’s Myungki Hong et al. reminded us that with ceria slurries, increased conditioning actually decreases removal rate. Researchers from Nitta Haas talked about the relationship of slurry particles to the asperities that helped explain the rate results reported by Samsung. Kyushu U.’s P. Khajornrungruang et al. added to this by demonstrating Fast Fourier Transformation analyses that certain frequencies of roughness drive the majority of removal rate. Saint Gobain’s Taewook Hwang et al. explained how their double-sided conditioner disk controls the stresses that drive other disks to become warped. Then David Slutz from Morgan Ceramic gave an update on low cut-rate conditioners they offer for today’s softer pads. John Zabasajja et al. from 3M also touted a new design of disk for soft pads.
Non-uniformity improvement was given a surprising amount of attention. For tungsten CMP, CEA-Leti (Viorel Balan et al.) studied the effect of retaining ring pressure on non-uniformity and UMC researchers showed that how slurry is dropped on the pad has a significant effect. Moon Hyung Cho from Dongbu did similar work studying retaining ring effects in ceria-based oxide polishing. UMC also wrote about the use of real-time process control for non-uniformity in copper CMP. G&P unveiled a new carrier design for non-uniformity.
All in all, there was a lot of information shared — clearly there is no shortage of opportunities to advance all different types of planarization processes.
Paul Feeney is the director of process technology at Axus Technology. He spent almost 15 years with IBM, starting his involvement in CMP in 1989 with responsibility for ILD and W CMP processes, then leading IBM’s selection efforts for both equipment and consumables for CMP. He was responsible for the successful implementation of copper and barrier CMP into manufacturing for the world’s first commercial copper chips. At Cabot Microelectronics (Feb. 1999-2011, CMP Fellow) he played a lead role in the development of slurries and processes for ILD, STI, copper, barrier, poly, and aluminum CMP. He is also a co-leader for planarization topics for the ITRS. E-mail: [email protected].
