Category Archives: Materials and Equipment

January 24, 2011 — Semiconductor Research Corporation (SRC) and researchers from Stanford University have developed a combination of elements that yields a unique nanostructure material for packaging. This advance should allow longer life for semiconductor devices while costing less than current state-of-the-art materials. In addition to chip manufacturers, several other industries could also gain greater product efficiencies from related thermal energy management technology.

Semiconductor manufacturers currently rely on tiny pins or thick solder to bond sections of the semiconductor in order for the device to perform. However, current solder materials tend to degrade and fail due to heat and mechanical stress. To continue the scaling of integrated circuits (ICs), SRC and Stanford have researched materials that provide a high thermal connectivity (comparable to copper) with the flexible compliance of foam. The answer has been created through a nanostructured thermal tape that conducts heat like a metal while allowing the neighboring materials to expand and contract with temperature changes (metals are too stiff to allow this). This ability to reduce chip temperatures while remaining compliant is a key breakthrough for electronic packaging.  

"A big roadblock to increasing the performance of modern chips is hot spots, or millimeter-sized regions of high power generation. This advance in nanostructured materials and methods will allow us to better cool these spots and serves as a key enabler for densification of computational circuitry," said Professor Ken Goodson, lead researcher for SRC at Stanford University. "This can help packaging to withstand the demands of Moore’s Law."

In addressing the challenges of miniaturization, the first line of defense for hot spots is the interface material. Incorporating nearly two decades of advanced research and simulations for problems at the packaging level — much of it funded by SRC — the Stanford team ultimately arrived at their unique combination of binder materials surrounding carbon nanotubes (CNTs). The researchers expect it to facilitate the highest thermal conduction and the most desirable level of elasticity of any known packaging solutions.

"This new thermal nanotape revolutionizes the chip’s heat sink contact," said Jon Candelaria, director of Interconnect and Packaging Sciences at SRC. "Instead of being forced to rely upon the properties of just a single material, this combination gives the integrated circuits industry an opportunity to circumvent severe performance limitations and continue to improve packaging without adding cost."

While the research was funded by members of SRC to enhance computer chips, demand for applications of this kind of thermal interface also is rising in other industries. For instance, several automotive-related companies hope to recover electrical power from hot exhaust gases in cars and trucks using thermoelectric energy converters but reliable interfaces are a problem. Professor Goodson leads a major grant from the National Science Foundation (NSF) Department of Energy Partnership on Thermoelectric Devices for Vehicle Applications, with the goal of transferring the SRC-funded interface work to vehicles.

Patents for the technology are pending. The next step in the research is to license the new methods and materials to advanced thermal-interface companies for application tailoring and commercialization. End users are expected to benefit from the technology by 2014.

For more information and details about the new packaging materials and methods, visit http://pubs.acs.org/doi/abs/10.1021/nl100443x and http://microheat.stanford.edu/publications/A119.pdf.

SRC is a university-research consortium for semiconductors and related technologies that defines industry needs, invests in, and manages the research that gives its members a competitive advantage in the dynamic global marketplace. For more information, visit www.src.org.

January 24, 2011 — Semiconductor Research Corporation (SRC) and researchers from Stanford University have developed a combination of elements that yields a unique nanostructure material for packaging. This advance should allow longer life for semiconductor devices while costing less than current state-of-the-art materials. In addition to chip manufacturers, several other industries could also gain greater product efficiencies from related thermal energy management technology.

Semiconductor manufacturers currently rely on tiny pins or thick solder to bond sections of the semiconductor in order for the device to perform. However, current solder materials tend to degrade and fail due to heat and mechanical stress. To continue the scaling of integrated circuits (ICs), SRC and Stanford have researched materials that provide a high thermal connectivity (comparable to copper) with the flexible compliance of foam. The answer has been created through a nanostructured thermal tape that conducts heat like a metal while allowing the neighboring materials to expand and contract with temperature changes (metals are too stiff to allow this). This ability to reduce chip temperatures while remaining compliant is a key breakthrough for electronic packaging.  

"A big roadblock to increasing the performance of modern chips is hot spots, or millimeter-sized regions of high power generation. This advance in nanostructured materials and methods will allow us to better cool these spots and serves as a key enabler for densification of computational circuitry," said Professor Ken Goodson, lead researcher for SRC at Stanford University. "This can help packaging to withstand the demands of Moore’s Law."

In addressing the challenges of miniaturization, the first line of defense for hot spots is the interface material. Incorporating nearly two decades of advanced research and simulations for problems at the packaging level — much of it funded by SRC — the Stanford team ultimately arrived at their unique combination of binder materials surrounding carbon nanotubes (CNTs). The researchers expect it to facilitate the highest thermal conduction and the most desirable level of elasticity of any known packaging solutions.

"This new thermal nanotape revolutionizes the chip’s heat sink contact," said Jon Candelaria, director of Interconnect and Packaging Sciences at SRC. "Instead of being forced to rely upon the properties of just a single material, this combination gives the integrated circuits industry an opportunity to circumvent severe performance limitations and continue to improve packaging without adding cost."

While the research was funded by members of SRC to enhance computer chips, demand for applications of this kind of thermal interface also is rising in other industries. For instance, several automotive-related companies hope to recover electrical power from hot exhaust gases in cars and trucks using thermoelectric energy converters but reliable interfaces are a problem. Professor Goodson leads a major grant from the National Science Foundation (NSF) Department of Energy Partnership on Thermoelectric Devices for Vehicle Applications, with the goal of transferring the SRC-funded interface work to vehicles.

Patents for the technology are pending. The next step in the research is to license the new methods and materials to advanced thermal-interface companies for application tailoring and commercialization. End users are expected to benefit from the technology by 2014.

For more information and details about the new packaging materials and methods, visit http://pubs.acs.org/doi/abs/10.1021/nl100443x and http://microheat.stanford.edu/publications/A119.pdf.

SRC is a university-research consortium for semiconductors and related technologies that defines industry needs, invests in, and manages the research that gives its members a competitive advantage in the dynamic global marketplace. For more information, visit www.src.org.

January 20, 2011 — Dow Corning has formalized an agreement to enter the imec multi-partner industrial R&D program on GaN semiconductor materials and device technologies. The program focuses next-generation GaN power device and LED development. The collaboration between Dow Corning and imec will concentrate on bringing the GaN epi-technology on silicon wafers to a manufacturing scale.

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Due to the combination of superior electron mobility, higher breakdown voltage and good thermal conductivity properties, GaN/AIGaN heterostructures offer a high switching efficiency for next-generation power and RF devices compared to the current devices based on silicon. A process for high-quality GaN epi-layers on Si substrates is key in obtaining superior power and RF devices. Accurate control of the epi-growth process to master substrate bow, epi-layer defectivity and uniformity while maintaining high epi-reactor throughput are needed to reduce the overall technology cost.

Imec has pioneered GaN epi-growth on sapphire, SiC and Si substrates from 2 to 6" substrate sizes and currently focuses on developing GaN epi-layers on 8" Si substrates. Leveraging the economics of scale and compatibility with high throughput and high-capacity 8" Si-wafer-based process technology will further reduce the cost of GaN devices and LEDs.

As a leading producer of SiC wafers and epitaxy, Dow Corning is leveraging its capability in electronic materials technology and quality supply to bring next-generation materials technology to global device manufacturers.

"By joining the imec GaN Affiliation Program, Dow Corning will rapidly expand its substrate product portfolio with high quality and affordable GaN epi-wafers for power, RF and LED markets," says Tom Zoes, global director, Dow Corning Compound Semiconductor Solutions.

Dow Corning is also the majority shareholder in the Hemlock Semiconductor Group joint ventures, which is a leading provider of polycrystalline silicon and other silicon-based products used in the manufacturing of semiconductor devices and solar cells and modules.

"We are delighted to welcome Dow Corning as a partner in our GaN Affiliation Program. Teaming up with imec’s epitaxy and device researchers within our multi-partner environment creates a strong momentum to bring this technology to market," says Rudi Cartuyvels, VP, Process Technology at imec.

Imec performs research in nanoelectronics. Further information on imec can be found at www.imec.be.

Dow Corning provides performance-enhancing solutions to diverse customers. The Hemlock Semiconductor Group (hscpoly.com) – Hemlock Semiconductor – is comprised of two joint ventures: Hemlock Semiconductor Corporation and Hemlock Semiconductor, L.L.C. The companies are joint ventures of Dow Corning Corporation, Shin-Etsu Handotai and Mitsubishi Materials Corporation. Hemlock Semiconductor is a provider of polycrystalline silicon and other silicon-based products used in the manufacturing of semiconductor devices and solar cells and modules.

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January 20, 2011 — Brush Engineered Materials Inc. (NYSE:BW) will change its name to Materion Corporation (NYSE:MTRN) and unify all of its businesses under the new name effective March 8, 2011. The Company’s common stock will continue to trade on the New York Stock Exchange. Concurrent with the March 8 name change, the Company also will unveil a new company website and company-wide brand identity.

Brush Engineered Materials began in the metals, mining and specialty metals businesses, but has evolved into other areas like thin-film solar and microelectronics packaging materials, said Richard J. Hipple, chairman, president and CEO. He added that "heritage" businesses are very successful and integral to the company’s future, part of a much larger portfolio. "Through changes, acquisitions and other internal initiatives, we have expanded into a brand new 80-year-old company at the forefront of technologies essential to our customers. We are a leading global producer of advanced materials and services providing enabling technology solutions for customers in the fastest-growing segments of long-term global growth markets, including consumer electronics, telecom infrastructure, defense and science, industrial and commercial aerospace, energy and medical."

"As we have grown, our businesses continued to operate under original names and brand identities. That has made it difficult to position the Company as a single, unified organization. We find that even some long-time customers are not aware of the full scope of our capabilities."

Hipple added, "We are often competing against large global players that enjoy strong brand recognition. With annual sales of more than $1.2 billion and growing at a compounded annual growth rate of 17% since 2002, we have the resources and critical mass to participate successfully at that level. We expect to benefit from the recognition that comes from one name and a single strong brand."

In its transformation, Hipple noted that the Company has also become leaner, faster-growing, more diversified, and less cyclical. "We have a higher-value business model today in terms of our growth potential, margins, cash flow, balance sheet and capital structure. We believe the new name will better reflect the new Company."

The unification of all of the Company’s businesses under the Materion name is intended to create efficiencies and facilitate synergies. The new name, along with a new business unit alignment under the Materion brand, is expected to provide customers with better access and recognition to a broader scope of products, technology and value-added services.

Brush Engineered Materials Inc., through its wholly-owned subsidiaries, supplies highly engineered advanced enabling materials to global markets. Products include precious and non-precious specialty metals, inorganic chemicals and powders, specialty coatings, specialty engineered beryllium alloys, beryllium and beryllium composites, and engineered clad and plated metal systems. http://www.beminc.com/ Subsidiaries: Brush Wellman Inc.; Williams Advanced Materials Inc.; Technical Materials, Inc.; Zentrix Technologies Inc.; Brush Ceramic Products Inc.; Beryllium Products

Williams Advanced Materials supplies specialty materials used in thin film deposition and semiconductor packaging applications. Learn more about Williams Advanced Materials (WAM) at http://www.williams-adv.com/

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January 19, 2011 — Wafer fab capex in 2011 is expected to stick around 2010 levels. But don’t despair of growth, says Dean Freeman of Gartner. For one thing, cutting-edge wafer fab equipment will be hot. On top of that, 2011 will be a brief respite, with a strong 2012/2013 waiting in the wings.

Listen to Freeman’s talk: Download or Play Now

Freeman, research VP at Gartner, summarizes key elements of his semiconductor industry forecast — which he presented to attendees of SEMI’s Industry Strategy Symposium (1/9-1/12/11, Half Moon Bay, CA) — in a podcast interview with Debra Vogler, senior technical editor. Figure 1 summarizes key technology trends that Gartner believes will drive the industry.

Top 10 strategic technology areas for 2010 Top 10 strategic technology areas for 2011
  • Cloud computing
  • Advanced analytics
  • Client computing
  • IT for green
  • Reshaping the data center
  • Social computing
  • Security — Activity monitoring
  • Flash memory
  • Virtualization for availability
  • Mobile applications
  • Cloud computing
  • Mobile applications and media tablets
  • Next-gen analytics
  • Social analytics
  • Social communications and collaboration
  • Video
  • Context-aware computing
  • Ubiquitous computing
  • Storage-class memory
  • Fabric-based infrastructure and computers
Figure 1. Looking forward at the technology trends.

Wafer fab equipment capex

Wafer fab equipment capex is expected to be flat in 2011 at around $54 billion — about the same as in 2010 — but leading edge equipment is expected to be strong. In particular, Freeman said that the 193i stepper will have "another barnburner year" in 2011 with a significant portion of capex. Following that lead would be double-patterning, polysilicon etch, and deposition equipment. Freeman made a special note of Globalfoundries announcement that it would increase its capex spending in 2011 by $2 billion (from Gartner’s original forecast) as the reason Gartner increased its capex forecast.

Because the semiconductor industry is tied to gross domestic product (GDP) — and it appears to be increasing across the board — Freeman anticipates a good year in 2011. He sees a stronger pull from consumer demand worldwide for electronic devices (cell phones, PCs, tablets) and that bodes well for capex. "If we see a strong acceleration of the economy," noted Freeman, "we expect a 5-10% growth rate in capex." If the economy remains flat, however, Gartner expects only a flat capex for 2011. However, in 2012 and 2013, Freeman is expecting to see a strong positive capex of 10% each year. The semiconductor industry will not have a major downturn in 2011, just a slight "digestion" period before re-accelerating into 2012 and 2013 (Fig. 2).  

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Figure 2. Semiconductor capital equipment, 4Q10: strength through 2013, then retrenchment. Source: Gartner.

Foundry capacity

Freeman addresses the question of whether or not foundries will have an over-capacity situation. "It appears the foundries have gone from a ‘once we get an order, we’ll build capacity’ back to a, ‘if we build it, they will come’ mentality," said Freeman. "With three leading-edge foundries — Samsung, TSMC, and Globalfoundries — all capable of 28nm, all approximately at the same time, there is a much higher level of competition." As a result, Freeman observes that they all have to demonstrate to customers that they have the capacity for any one of them. So this will probably lead to a slight overbuild at 28/32nm. "It’s possible you will see IDMs start to shift over sooner than expected, and that may absorb the over capacity fairly quickly." Freeman expects the over capacity will be short-lived (6 months to a year); Gartner expects 28/32nm to ramp very rapidly. Freeman cautions, however, that the foundries do not appear to be overspending from a device revenue perspective, so Gartner is monitoring the situation closely. "What a great time for a fabless company to be at the leading edge," said Freeman.

Freeman also commented on the impact of energy on the semiconductor industry. He sees a strong growth potential for analog. Green tech and automotive will also drive unique devices such as GaN on silicon and SiC devices.

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by Michael A. Fury, Techcet Group

January 17, 2011 – SEMI’s Strategic Materials Conference (SMC 2011) continued on Day 2 with introductory remarks specific to the electronic materials industry. This year’s theme was Material Innovation: Catalyst for Success. Two new features were introduced this year to facilitate some real time online dialog as well as ongoing discussions beyond the life of the meeting itself: one is the Electronic Materials Information group which has been created on LinkedIn and is open to everyone; the other is Techcet’s Electronic Materials Information Conference site, also open to everyone. The LinkedIn function provides excellent broad networking communication but limits the length of individual messages to 200 characters, plus an optional web link. The Techcet site facilitates full discussions with no length restriction. We hope readers in the electronic materials field will participate in both forums and keep discussions robust not only during conferences, but throughout the year.

The opening keynote for SMC 2011 was delivered by Nobu Koshiba, president of JSR Corp., speaking on semiconductor technology trends, challenges and opportunities. The consolidation of chip manufacturers (i.e. fewer customers) is a business challenge in its own right that is further compounded by the fact that the next several nodes will be driven by new device architectures, over which materials suppliers have no control and limited insight, he said. The focus for high-volume materials will shift to analog an power devices. New CMOS materials being developed have no guarantee of longevity beyond the node for which they are developed, decreasing the return on R&D investment.

A different perspective on semiconductor technology trends was delivered by Gary Patton, IBM’s VP of SRDC. He asserted that the three-way collaboration of fabs with materials & equipment suppliers is the only way that the Roadmap can be realized. Traditional scaling has run out of steam; only a combination of material and structure changes can facilitate progress. The ruling mantra will be atomic level in deposition, patterning, etching, cleaning and planarization. IBM has ~30 ongoing joint development programs in Albany with another ~30 already completed. Success stories include 2nd generation immersion litho for 28nm; topcoat for immersion litho to prevent resist & lens contamination by the fluid layer, with JSR; and source mask optimization to enable pattern resolution to 20nm, with ASML, Toppan, & Mentor Graphics. Extreme ultraviolet (EUV) lithography is critical to recover the optical k1 factor that degrades from 22nm to 15nm to the extent that double patterning is required, yet is itself not extendible. His roadmap of future device structures showed proof of concept devices to 3nm. A critical high implant dose resist strip was co-developed with ATMI. Copper contacts with a Ru barrier have been implemented on a 0.1μm2 6T-SRAM cell, breaking the paradigm that presumed the perpetual use of tungsten for the contact level.

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 CMOS scaling realities: Pitch degradation.
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EUV lithography: The promise of high k1 imaging.

Redirecting the group’s focus, Andrew Thompson, co-founder and CEO of Proteus Biomedical, noted that the medical services industry does not serve as many as 85% of the global population. Only about 3.5B people on Planet Earth wear shoes — but 4.5B own cell phones, even though a vast majority of them earn less than $10 per day. Underlying this is the notion that individuals now hold more computing power than corporations and governments. The cost structure for medical enterprises has been built around the ability of the richest 10% to pay, whereas electronics innovation is underwritten by the richest but successfully addresses the ability to pay for the remainder.

Revenue source Medtronic Novartis Intel
ROW 14% 18% 70%
Europe 24% 43% 15%
USA  62% 40% 15%

The system uses edible electronics incorporated into the patient’s pills that, when ingested, transmit information to an external band-aid worn on the skin, which in turn transmits pill and vital sign data to a cell phone which then is made accessible to caretakers. ON Semiconductor is the primary partner for both the ingestible and wearable electronic components. Myfortic and Metformin are two of the drugs slated for initial commercialization; approval is well underway by the FDA and its European counterpart. The pharmaceuticals industry is $750B in 2010, but Morgan Stanley projects $2.0T in 2020 for this sort of intelligent pharmaceuticals, based on an electronics industry cost structure rather than traditional big pharma. Thompson’s vision is to bring affordable health care to everyone using technology. The ingested component is a silicon grain powered by a Cu and Mg bimetallic couple that is activated by body fluids. The digitally encoded data presents itself as a dipole that is detected by the band-aid. There is no powered RF involved until the data is transmitted beyond the band-aid. Product authentication is an additional benefit of this technology. In Nigeria, 80% of the pills taken are counterfeit or just plain fake; in China, one pill in seven is fake. The social implications of this technology and of changing the pharmaceutical business paradigm are huge.

Returning to somewhat more traditional device manufacturing and material technologies, Jae Hyun Kim, principal engineer at Samsung brought us the perspective of this leading manufacturer. Major upcoming innovations supported include 3D integration, EUV lithography, and capacitor dielectric competition between HfO2, ZrO2 and other high-k materials. Packaging density demand for 2012 will be up 3× for DRAM and 8× for Flash. Several examples emphasized the importance of analytical and characterization advances concurrent with technology advances, including rapid QC protocols. Their four pillars for resource conservation are recycle, reuse, reduce and refuse (eliminate processes). [Note that their 4 R’s are more correct that the traditional American 3 R’s, of which one is actually a W and which requires an apostrophe for ‘Rithmatic. Is this creativity or just marginal education?]

Blizzards in NY deprived us of a presentation from Bryan Rice, director of lithography at SEMATECH, on advanced lithography challenges (current and future). We hope to hear from him on this subject in the near future, before the challenges change — again. I’m pretty sure that snow was a challenge not included in his presentation.

Venturing into the More than Moore realm, mc10 CEO David Icke introduced us to high-performance conformal electronics. Venture-backed mc10 was co-founded by Prof. John Rogers at UIUC, who was originally scheduled to speak. The common theme is to leverage the performance of conventional silicon ICs into conformal and bio-inspired environments. David made the point that such technology represents a strategic direction for some electronic packaging applications. The technology is based on the flexibility of single crystal silicon that manifests when the material is sufficiently thin. Straightforward wet etch undercut is the production tool. Applying this flexible silicon to polymer, fabric or skins is managed using ‘accordion physics’ that tolerates 70% substrate strain while only imposing 0.2% strain on the metal interconnects between silicon features, and 0.15% strain on the silicon itself. Maintaining biocompatibility enables a host of medical applications, including optoelectronic catheters, trauma monitors in military helmets, temporary tattoos for vital sign monitoring, and a direct brain-computer interface. FDA certification aside, there is no fundamental cost hurdle anticipated in scaling up the technology.

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Serpentine mesh interconnects. (Source: Nature Materials)

Moving into semiconductor adjacencies, Joe Berwind, principal at Alternative Energy Investing, led us off with a discussion on grid parity, levelized cost of energy (LCOE), and the PV supply chain. Typical grid parity projections do not take into account the specific cell costs and performance and durability variations among the different PV technologies being commercialized. LCOE calculations normalize the effects of government subsidies, enabling more functional comparisons between regions:

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Solar adoption/ growth trends by region, with grid-parity projections. (Source: Heliovolt)

On the other hand, government subsidies play a tremendous role in accurate forecasting for PV silicon demand, but are frequently taken into account inadequately:

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A technology overview of PV was provided by Rommel Noufi, principal scientist and PV group manager at NREL, focusing on high-efficiency CIGS solar cells. Thin-film PV share is 17% globally (62% in US), projected to be 25%-30% by 2015. First Solar currently holds the lowest CdTe manufacturing cost at $0.76/watt. CIGS degradation is due mainly to the water sensitivity of ZnO, which necessitates encapsulation or an alternative TCO. Achieving 80% of the best-case lab efficiency is a critical milestone for module scale up feasibility for volume production. CIGS manufacturing cost projections provided by NREL show a lot of promise compared to silicon, but the analysis was provided with an explicit disclaimer since the government does not intend to advise investors. Unlike CMOS devices, CIGS actually requires Na+ diffusion doping in the Mo base to increase efficiency. (Heresy!) Indium is the most costly element in the CIGS layer, with efforts underway to substitute more and more of the In with Ga. Replacement of the CdS top buffer with a Cd-free substitute is a key milestone on the scale-up roadmap.

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Solar PV module manufacturing costs, benchmarking analysis: CIGS vs. CdTe and x-Si incumbents.
Module costs must be considered in the context of module efficiency, i.e. impact on installation costs.

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Device structure varies between monolithically and mechanically integrated modules. (Source: NREL)

The adjacencies session then moved into LEDs, with David Bour, chief technologist for LED product technology at Applied Materials, speaking on epitaxial nitride semiconductors for solid-state lighting. Light extraction is improved by using a patterned sapphire substrate that encourages defect pinning. A white light is fabricated by combining a blue LED with yellow phosphors to approximate the whiteness equivalent of black body radiation at ~4200°K. Visual repeatability is heavily dependent on thickness and composition uniformity in each layer; this is difficult, so device binning is used to approximate visual uniformity in the end package. Preliminary data indicates that the junction quality of the AMAT 450nm devices is superior to that of commercial 475nm devices, based on the observed absence of nonradiative defects at low currents. These devices were fabricated to demonstrate the benefits of run-to-run reproducibility in automated multilayer MOCVD, and do not signal a move by AMAT into LED manufacturing.

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 LED epitaxial layer structure.

The final talk of the adjacencies session was on the MOCVD of III/V semiconductor by Johannes Kaeppeler, VP of technology at Aixtron. [Side note: Aixtron offers a PECVD carbon nanotube deposition tool called "Black Magic"; I like the way these guys think!] Aixtron’s revenue picked up sharply starting in 2007 due 90% to LEDs and the HDTV market, to the extent that they are already a $1B equipment company. I am personally fascinated by the complexity of multilayer structures that are already in volume production. The company’s long-term strategy calls for moving beyond LED and PV planar structures into CMOS III/V on Si, ready for production on 300mm & 450mm wafers in 3-4 years.

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Typical grown MOCVD structures.

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Integration of Ge p-channel and III-V n-channel using MOCVD. (Source: www.ims.demokritos.gr/DUALLOGIC/)

Panel: Supply chain and materials

The traditional panel discussion on supply chain analysis and the materials business environment was moderated by Carl Johnson of Infrastructure, and began with a brief presentation by each of the five panelists.

  • Tim Hendry, Intel VP and now head of its Fab Materials Organization, suggested some notions of improving materials affordability with supply chain innovation. Conflict-free minerals have moved very quickly from a level of social concern to government regulation, requiring rapid response by our industry.
  • Norm Armour, VP/GM of GlobalFoundries Fab 8 in NY, is concerned about the materials cost escalation that accompanies design and device complexity. From 40nm to 28nm, materials costs are expected to double, while equipment costs will only increase 1.57times;. Immersion resist costs are 3-4× higher than DUV resist. Stronger lobbying is likely needed to protect the industry and specifically US interests.
  • Roger Gossett, senior procurement manager at Freescale, dwelled on assurance of supply as a basic mantra, which resurrects the discussion of dual sourcing strategies and zero defects (although six sigma was never mentioned…).
  • Jeremy How, strategic sourcing manager at Air Products, mapped out the intersection — collision, really — of volatility and complexity, and laid claim to having captured all of the points made by the prior three IDM speakers in his one chart. I do believe he may have done just that.
  • Kurt Carlsen, strategic sourcing director for Air Liquide, monitors ISM data for US manufacturing looking for implications that will impact semiconductor supply chains from not-necessarily-expected sources. Those supply chains are now longer, more complicated, work on lower inventories, and require higher risks. He sees more of his suppliers planning to exit the semiconductor industry because many other industries provide greater stability in exchange for higher returns.

Johnson opened the panel discussion with a series of quick questions for individual panelists. Gossett is dealing with the huge bounce back in the automotive industry. Armour is spending capital at a rapid rate without necessarily being guaranteed of the material volumes needed to operate them. Hendry is running an abundance of tool qualifications while dealing with a too-high number of single source suppliers. How asserted that they can identify new suppliers for demand bubbles much more quickly than fab customers can qualify them. Carlsen expounded on the differences between procurement (day to day, price dominates) and sourcing (strategic, longevity dominates). Continually driving prices down ultimately results in suppliers exiting the business.

Raw material price increases drive delivered product prices (e.g. W powder needed for WF6), and this requires supplier-customer discussion, particularly in anticipation of expectations of price decreases if/when raw material prices decrease.

Electronic materials suppliers that simply repackage or ship direct from qualified sub-manufacturers are not often cut out as the middle man because they do provide a level of logistics management that fabs do not wish to replicate.

Hazardous materials shipped by boat can be refused loading by the captain, delaying the shipment until a captain comes along who is willing to convey the materials. Local manufacturing is the only solution to this problem for materials that cannot be shipped by air — of which the semiconductor industry uses several.

There is some marginal improvement in the US recently with manufacturing tax credits that make it possible to better maintain or upgrade US chemical manufacturing plants to keep the US competitive with emerging markets in China and elsewhere.

Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected].

January 17, 2011 — SEMI named Thomas DiStefano, John W. Smith Jr., and Michael Warner as recipients of the 2010 SEMI Award for North America for contributions to the development and commercialization of Micro Ball Grid Array (μBGA) technology.

This advancement led to many forms of semiconductor chip scale packaging (CSP) that enabled cost-effective miniaturization. It has had a significant impact on the proliferation of products with smaller form factors, such as handheld phones, cameras, games and other electronics that have since become common. The SEMI Award for North America is the association’s highest honor for technical contribution to the semiconductor industry. The industry awards were presented during a banquet at the 2011 SEMI Industry Strategy Symposium (ISS) in Half Moon Bay, CA.

"Our industry honors Tom DiStefano, John Smith and Michael Warner for their combined efforts to commercialize Micro Ball Grid Array technology while at Tessera Technologies," said Stanley T. Myers, president and CEO of SEMI. "This critical packaging technology was an important development in the proliferation of smaller personal electronic devices that have spurred the market for semiconductor devices."

Dr. DiStefano was the founding president of Tessera Technologies and a co-founder of ChipScale Review. DiStefano helped to build Tessera into a world leader in miniaturized packaging. Royalties from U.S. Patents coauthored by DiStefano produced well above $1billion revenue for Tessera. John W. Smith, Jr. joined Tessera in 1992 as its CEO where he served until his retirement in 2000. Michael Warner, a Tessera Fellow, joined the company in 1994 as the vice president responsible for developing products employing µBGA solutions for commercial applications.

"The introduction of chip scale packaging by Tessera enabled a decrease in package size and an increase in package frequency while reducing the total power required," said Bill Bottoms, chairman of the SEMI Award Advisory Committee. "This innovation is now the packaging solution of choice for most memory devices and a significant number of logic devices. It was initially adapted to meet performance requirements and the high-volume commercialization led to its widespread adoption as a lower-cost packaging alternative."

The SEMI Award was established in 1979 to recognize outstanding technical achievement and meritorious contribution in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

The award is the highest honor conferred by SEMI. It is open to individuals or teams from industry or academia whose specific accomplishments have broad commercial impact and widespread technical significance for the entire semiconductor industry. Nominations are accepted from individuals of North American-based member companies of SEMI. Past award recipients include Walter Benzing and Mike McNealy, Ken Levy, Jean Hoerni, Dan Maydan, Robert Akins and Igor Khandros, among others.

SEMI is the global industry association serving the manufacturing supply chains for the microelectronic, display and photovoltaic industries. For more information, visit www.semi.org.

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January 12, 2011 — Popular consumer products such as smartphones, tablet PCs, and LED televisions have created demand for a new breed of low-cost advanced packaging technologies. There are a few key attributes in the highest demand for devices targeting these applications: a reduced footprint and/or profile, high electrical performance, fine-pitch design, custom features, and a low cost.

As consumer applications evolve into smaller, feature-rich devices, the supply chain must respond to meet these low-footprint, high-density component packaging demands. Over the last several years, the quad flat package no leads (QFN) package has been the standard device due to the benefits it offers (small, light, better thermal, etc.). Devices are getting smaller and are proving to be a challenge to assemble with finer pitches and longer bond wires. The introduction of dual-row QFNs has helped to reduce the package size and improved manufacturability. But these multi-row QFNs present their own challenges including finding manufacturers that can produce good lead features and ensuring the capability of an SMT house to mount multi-row QFN with no lead standoff height. In some cases, they also affect singulation by requiring a dual-pass process.

Newer technologies have taken the dual-row QFN a step further. The etched leadless package (ELP) offers flexibility with up to 3 rows with isolated pads, power and ground rings. This gives the device manufacturer options to optimize product performance. The triple-row capability provides an even smaller footprint having more I/Os. Another advantage of this package over standard QFNs is that the sawing process only cuts the mold compound, improving the cutting speed by >2× and extending saw blade life of the saw blade.

Click to Enlarge Click to Enlarge Click to Enlarge Click to Enlarge Click to Enlarge
Figure 1. Variations of the etched leadless package (ELP).

Another newer multi-row QFN-style package is QPL’s HDL technology. Unisem has collaborated with QPL to introduce the technology to their package portfolio in 2010 as their leadframe grid array (LFGA) package. The LFGA is similar to the ELP package — greater flexibility in a leadframe-based package — and allows for even greater customization to simplify the wire layout. The higher density routing also enables use of even more rows of leads to further reduce package size. Active leads can be placed underneath the die, attached by non-conductive epoxy or die attach film (DAF).

  52 lead – 4.5x7mm form factor   52 lead – 4×4.5mm form factor
Leadframe internal design Click to Enlarge   Click to Enlarge
Front of line (FOL) assembly wire bonded  Click to Enlarge    Click to Enlarge
End of line (EOL) assembly after etching  Click to Enlarge    Click to Enlarge
Final package solder finish Click to Enlarge   Click to Enlarge

Figure 2. Leadframe grid array package (LFGA).

For an even smaller package size, there has been strong surge in the demand of wafer level chip scale packaging (WLCSP). With features like its small footprint, thin profile, light weight, and cost competitiveness, it is a true chip-sized package where I/Os can be fully populated within the chip using a redistribution layer (RDL). Typical chips size range from about 1 × 1mm to 6 × 6mm with bump pitches of 0.4mm or larger. The WLCSP is utilized heavily in handheld products such as smartphones, tablet PCs, and digital still cameras.

Electrical performance continues to be a priority for packaging as well and is a requirement for most levels of devices in consumer electronics. The conventional wire bonded device has some limitations on when it comes to clock speed and cross-talk due to wire proximity. Using flip-chip technology improves the device response by >10% and at the same time gives better thermal performance 10~20% with the use of thermal bumps when attached to the thermal pad. Flip chip with Cu pillar bump technology can further help to improve the electrical performance. The WLCSP package technologies with direct ball drop on the pads or on redistributed pads will also have lower inductance when compared with standard wire bond.

Today’s complex devices also require fine-pitch design feature capabilities. Multi-row and fully populated QFN-style package offer design capabilities that in the past were limited to more expensive ball grid array (BGA) substrate-based packages. The previously mentioned packaging technology from QPL that Unisem has introduced as the LFGA is able to support 0.4mm pad pitch. Flip chip and WLCSP packages are also able to offer finer pitch features. Flip chip bumping technologies such as the Cu pillar bump can achieve a bump pitch of 120µm vs. electroplated solder bump (150µm) and conventional ball drop (400µm).

Custom packaging or even die-level features may also be required to meet today’s consumer electronic requirements. Multi-chip packages (MCMs), also known as system in package (SiP), integrate multiple chips and passive components within the package and help to reduce footprint, improving electrical performance and cost competitiveness. SiP is widely used in RF application products such as frontend power amplifier (PA) modules. Using an integrated passive device (IPD) to replace passive components in a SiP package is also gaining popularity. IPDs help to simplify the substrate and leadframe design for module packages, reducing the footprint and packaging lead time.

Conclusion

With all these needed features and advances in leadframe and flip-chip-based packaging solutions, the pressure is still on the assembly provider to offer all this at a competitive price. Leadframe-based packaging is generally more cost efficient than those that use substrates. QFN, multi-row QFN, ELP, LFGA, and other similar technologies have the ability to achieve higher I/Os and are very cost efficient. WLSCP packages using the ball drop process on 200 and 300mm wafer sizes is cost efficient because there are no direct packaging materials required and it simplifies the back-end assembly processes.

Other assembly process solutions that can help lower the assembly cost are Cu wire bonding, smaller wire diameter, lower-cost bill of materials (BOMs), post wire bond taping, and using a jig saw instead of tape saw for QFN. Pre-plated leadframes (PPF) can also lower the cost of the assembly processes.

Leadframe and flip-chip packaging technologies continue to evolve and help provide the semiconductor industry with package solutions that are both cost effective and able to take on the complexities of today’s and tomorrow’s consumer electronics market segment. Characteristics such as a reduced footprint and/or profile, electrical performance, fine pitch design, custom features and a low cost are now able to be achieved with technologies such as the ELP multi-row QFN package and with bumping technologies such as the fine pitch copper pillar bump. Device manufacturers no longer need to migrate to BGA-style packaging when requirements become demanding or complex.

Rico San Antonio of Unisem (Batam, Indonesia) co-authored this article with Chris Stai, Unisem (Sunnyvale, CA). Contact them at [email protected].

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Technology forecasts for 22nm
Addressing defectivity will require new surface-engineering processes at 22nm
RoHS, device shrinks will continue to drive packaging technology
Tooling and process technology vital for thin packages
More collaboration is needed to improve process integration
22nm brings maskmakers, end users closer
22nm: The era of wafer bonding
Failure analysis challenges at 22nm drive the need for turn-key failure analysis solutions
A materials evolution and revolution for 22nm devices
Enabling lithography for the 22nm node
Keys to CMP and cleans: Defect reduction and process customization
Gate structure/3D stacking "winners" will determine industry direction

(This is an online exclusive essay in SST‘s Forecast for 2011: Back to Reality series.)

Bioh Kim, director of business development for 3D and AP, EV Group, Tempe, Arizona, USA

Click to EnlargeJanuary 11, 2011 – With the leading edge of the semiconductor industry edging toward the 22nm production node, the "More Moore" debate rages on about the best lithographic solution to economically scale down to smaller design rules. Yet beyond "More Moore," an equally key trend looms large for IC manufacturers: "More than Moore," where the migration to the 22nm node involves not only scaling down, but building up — adding more heterogeneous device components, such as radio frequency (RF), power management, optics, and even MEMS devices, into a single package. In these complex systems-in-package (SiP), high-density interconnection is especially critical, which in turn is driving a greater emphasis on wafer bonding.

Choosing the right bonding process depends upon several important criteria, including the thermal budget of materials properties and manufacturing processes, the alignment accuracy of the substrates, the throughput of the bonding process, and minimizing the risk of metal ion contamination.

Based on these criteria, the two most viable bonding process methods for high-density interconnection are copper-copper thermo-compression bonding and a variation of silicon direct bonding, called plasma-activated low-temperature oxide bonding. Each has its trade-offs. Copper-copper thermo-compression bonding provides optimal alignment accuracy and electrical performance but is slower (typically 1-2 hours per wafer) and requires temperatures at the upper-limit of what is allowable for CMOS processing (around 400°C). Plasma-activated low-temperature oxide bonding, on the other hand, is initially a room temperature process and involves lower pressure — making it an easier and faster process (2-3 minutes per wafer). Subsequent annealing (at 200-400°C) as a batch process enhances the bond strength. However, it requires very stringent surface quality requirements and needs subsequent interconnection processes after bonding.

In addition to adding more device components within a package at the 22nm node, chipmakers are also thinning the wafer (to ~50μm) to enable more stacked devices within the same package footprint. Since these thin wafers are extremely fragile, wafer bonding again plays a crucial role. By allowing device wafers to be temporarily bonded onto carrier substrates, they can undergo wafer thinning and through-silicon via (TSV) interconnection without risking damage.

In temporary bonding and debonding, selecting the right material and bonding equipment vendors is critical. Many polymers are susceptible to deformity and bubbling at temperatures above 200°C, which impairs the quality of the bond. Leading materials companies are focusing significant resources to develop new polymers that are more stable at higher temperatures. In choosing the right wafer bonding process, chipmakers need to consider many criteria beyond which bonding process works best for them — including process expertise, optimization of equipment design to ensure stringent temperature, pressure and environmental control, and advanced wafer handling to ensure the integrity of these fragile and costly product wafers.

In summary, the migration to the 22nm node is about more than just scaling down; it’s also about scaling up — with thinner devices and more of them stacked into a single package to enable increasing levels of functionality. These "More than Moore" trends require new manufacturing considerations — with wafer bonding playing a central role in each one.

Technology forecasts for 22nm
Addressing defectivity will require new surface-engineering processes at 22nm
RoHS, device shrinks will continue to drive packaging technology
Tooling and process technology vital for thin packages
More collaboration is needed to improve process integration
22nm brings maskmakers, end users closer
22nm: The era of wafer bonding
Failure analysis challenges at 22nm drive the need for turn-key failure analysis solutions
A materials evolution and revolution for 22nm devices
Enabling lithography for the 22nm node
Keys to CMP and cleans: Defect reduction and process customization
Gate structure/3D stacking "winners" will determine industry direction

(This is an online exclusive essay in SST‘s Forecast for 2011: Back to Reality series.)

Doug Dixon, marketing dommunications director, Henkel, Irvine, CA USA

Click to EnlargeJanuary 11, 2011 – How do we follow a year like 2010? Though market analysts certainly projected an up year as compared to 2009, none could have anticipated the growth that the packaging market experienced throughout the previous calendar year. And, while this market expansion has undoubtedly had its benefits, challenges have also resulted. With demand at record highs, efficiently managing the supply chain has become increasingly more complex. Large, global organizations with a depth of resource and world-class supply chain management systems are arguably navigating this terrain a bit more successfully than others and providing better predictability of supply to their customers.

On the technology side, environmental legislation in combination with device miniaturization will continue to drive packaging development efforts throughout 2011 and beyond. Now set for 2014, the deadline for compliance with RoHS legislation in the power/discrete device market is forcing manufacturers to find alternatives to high-lead die attach solders. Of course, compliance with environmental standards cannot come at the expense of performance and this balance is the ultimate challenge. Developing materials that can provide sufficient thermal and electrical capabilities in a lead-free medium has been at the forefront of our R&D efforts.

But environmental concerns are not the only thing keeping packaging specialists awake at night. Without question, the smaller, thinner, more powerful paradigm is here to stay and is challenging traditional design and assembly rules, ultimately putting greater demands on the materials needed to enable their function. Much thinner wafers (≤50μm) and the ability to stack die to unprecedented heights (32 die stacks) has driven die attach materials innovation to address these new requirements. New die attach film materials with thicknesses as thin as 5μm are enabling much thinner bond lines and delivering thermal budgets that allow for extreme multi-stacking processes. In fact, for many applications, die attach film will be the only die attach option as traditional die attach pastes will not be workable for applications that require extremely small, thin die. This will not only be the case for non-conductive applications, but for conductive, power devices as well.

With the convergence of environmental legislation alongside increasingly miniaturized, higher functioning devices, 2011 promises to be a very demanding and exciting year!