Category Archives: Metrology

(July 15, 2009) &#151 Following are some of the booth highlights from companies exhibiting at SEMICON West, July 14–16, 2009 in San Francisco, CA. Booth demonstrations include cleaning products for flip chips, bonded wafer inspection systems, airborne particle sensor/monitors, die-attach systems, and more for semiconductor manufacturing, packaging, and test.

CyberOptics Semiconductor, North Hall, booth #5761
The WaferSense airborne particle sensor (APS) wirelessly monitors airborne particles in process equipment to validate and analyze wafer contamination in real-time to reduce wafer scrap and improve die yield. The wafer-like, automated, and vacuum-compatible APS identifies particles and their exact location in a process as mechanical and gas events are cycled, including in and around tools, transfer areas, front-ends, track tools and chambers. Initial testing has shown sensitivity to detect 0.1&#181m particles. The system will be available in 2H09 in 300mm and 200mm form factors, with 450mm versions to be available by special order.

Micro Precision Automation (MPA), at the Applied Mechatronics booth, North Hall, booth #6082
The polar coordinate 450mm metrology stage consists of a linear, rotary and Z axis, boasting a compact footprint for inspecting 450mm wafers. The bridge configuration provides a stable platform for mounting a variety of metrology systems. Additional features include an integrated prealigner, independent load/unload stations, a low-contact vacuum chuck (1.7% of a 450mm wafer), and an option for a lift pin mechanism for measuring wafer bow.


Tiger Optics, South Hall, booth #1736
The Prismatic can measure up to 16 different species simultaneously. Users select the species of interest from Tiger’s detections list. Brewster’s angle prism retro-reflectors provide total internal reflectance broad enough to measure multiple species down to parts-per-billion with a single Ring-Down cell. The Prismatic development was initially funded by the National Science Foundation. For Continuous Wave Cavity Ring-Down Spectroscopy (CW-CRDS), the Prismatic offers accuracy, speed of response, very low maintenance, freedom from calibration, and wide dynamic range, with no ambient effects. The debut Prismatic system measures down to ppb levels of moisture, methane, carbon monoxide, and carbon dioxide gases. The system’s built-in reference cells and automated tune function prevent interference and drift, without external calibration, consumables or routine maintenance. A non-contact measuring technique, CW CRDS is suitable for bulk gases, clean dry air (CDA), corrosives, fluorocarbons, and other specialty gases, such as nitric oxide, nitrogen fluoride, and sulfur hexafluoride.


Technical Manufacturing Corporation (TMC), North Hall, booth #5765
STACIS FM is a hard-mount active vibration cancellation system, part of TMC’s family of STACIS advanced piezoelectric vibration isolation products designed to control building floor vibrations in semiconductor manufacturing facilities. The frame-mountable Stacis FM incorporates proprietary Stacis technology for efficient vibration isolation using piezoelectric actuators and a stiff suspension. It is designed to be integrated into advanced, high-throughput lithography and metrology tools. The Stacis technology is capable of fast settling of the isolated payload in response to motorized, stage-induced motion, resulting in increased tool throughput. Stacis FM features extended stroke piezoelectric actuators, fast settling time in response to stage motion, and a hard-mount suspension with no soft air springs. It is available in either 3&#176 or 6&#176 of freedom and starts to isolate well below 1 Hz.


Aries Electronics, South Hall, booth #435
The CSP/BallNest Hybrid Socket suits prototyping, test, or burn-in of chip scale package (CSP), ball grid array (BGA), microBGA, and land grid array (LGA) devices. The socket, which features a lid that nests each ball termination into the socket for a reliable connection, can be used on any device with a 0.30mm pitch or larger. The ZIF-style (zero insertion force) socket uses Aries solderless, gold-plated pressure mount spring probes, allowing for easy mounting and removal from the PCB. The design maintains constant force throughout the entire test and burn-in cycle as well as on the surface mount PCB when no chip is engaged. The socket bolts down onto the target PCB in the same footprint as the socketed device. This process also enables the socket to be mounted to an adapter board terminated with male thru-pins effectively creating a thru-hole solder tail socket for BGA devices. The socket cover can also incorporate heat sinks. A four-point crown ensures “scrub” on solder oxides. The gold-over-nickel plated compression spring probes leave very small witness marks on the bottom surface of the device solder balls. Its signal path is 1.96 mm. The socket’s contact forces are 15g per contact on a 0.30-0.35mm pitch, 16g per contact on a 0.40-0.45mm pitch, 25g per contact on a 0.50-0.75mm pitch, and 25g per contact on a 0.80mm pitch or larger. Operating temperature is -55&#176 to +150&#176C and estimated contact life is 500,000 cycles. The test socket is available in custom materials, platings, sizes and configurations.

Dage Precision Industries, a Nordson company, South Hall, booth #807
The enhanced 4000HS High-Speed Bondtester offers high-strain-rate bond testing for detecting brittle fracture failures in lead-free materials. Dage’s new 4000HS software and hardware toolset offers enhanced capability for bond testing analysis and process control. This toolset includes high-speed trigger capture software and rising table work holder for cold bump pull bondtesting. These toolset features further advance the application of high-speed bondtesting. The test instrument provides energy measurements during bond testing and ensures full compliance with JEDEC standards, analyzing microelectronic solder joint integrity and reliability.

Dage will also showcase its Quick View CT inspection system that allows users to obtain initial computerized tomography (CT) reconstructions within 5 minutes, compared to previous times of over 20 minutes. This quick view CT software makes CT a much more viable process tool for production and failure analysis applications. The Quick View CT software is available for Dage’s X-ray inspection systems that combine digital acquisition technology and ImageWizard software. The Dage NT X-ray tube provides sub-micron feature recognition with the added benefit of a sealed tube for minimal maintenance.

Strasbaugh, South Hall, booth #2007
The STB P300 CMP system is designed to incorporate next generation factory (NGF) principles. It targets production and process flexibility with advanced CMP technologies. Features include lower cost of ownership and integrated wafer cleaning. The system supports high mix, small lot applications. P300 is available in several configurations for semiconductor, data storage, SOI, silicon, and MEMS manufacturing. Several CMP technologies will be introduced with the P300, including the nVision II optical and motor current endpoint detection system, the new-generation Saturn wafer carrier, the Precision pad conditioner, and integrated cleaning.


JEOL, South Hall, booth #606
The ultrahigh-resolution analytical Thermal Field Emission Scanning Electron Microscope (SEM) JSM-7600F will be demonstrated via live remote viewing and control at the SEMICON West booth. Resolution is up to 1,000,000&#215 magnification. The SEM also features X-ray analytical mapping of individual layers, elemental composition, contaminants, particulates, and process defects in semiconductor devices. It has a large chamber with large specimen exchange airlock and LN2 anti-contaminator, the JSM-7600F accommodates specimens up to 200mm in diameter, and features a highly stable 5-axis motor drive eucentric stage that can be tilted from -5&#176 to +70&#176. The microscope’s electron column produces a high beam current and superior imaging of nonconductive samples that traditionally charge. The JSM-7600F minimizes beam damage on heat-sensitive samples such as low-k dielectrics. It offers improved stability for unattended data acquisition, particle analysis, EBSD, and X-ray mapping. The JEOL JSM-7600F is outfitted for comprehensive analysis techniques and can simultaneously view and acquire images and data from 4 types of imaging detectors. The SEM also can be used as a direct write e-beam lithography tool when outfitted with a high-speed beam blanker and a pattern generator.

Confluense LLC, South Hall, booth #2209
The Pad Surface Manager pad conditioning system claims to improve chemical mechanical planarization (CMP) consumable utilization efficiency by >300%, and reduce particle adders and defects by 30–80%. The pad is cleaned in situ immediately after it contacts the wafer, removing spent slurry, pad debris, and by-products and preventing them from being recycled back under the wafer and ensuring fresh slurry at the wafer surface at reduced feed rates. Bi-directional control of the conditioner downforce maintains high removal rate with minimum cut rate, reducing pad debris and extending both pad and conditioner life. Effluent streams are separated by slurry concentration to reduce waste treatment load and DI water recycling costs.


Asahi/America Inc., South Hall, booth #1431
Dymatrix Multiport Valve (MPV) Manifolds are now manufactured in the company’s Malden, MA facility to reduce lead times to 2-4 weeks. The PTFE valves are machined on dedicated CNC equipment and assembled in a clean room. The Dymatrix MPV Manifold offers a variety of capabilities in a compact valve. The valve design features a zero dead leg diaphragm with full flush capabilities. The special diaphragm eliminates dead space and particle generation, suiting semiconductor and ultra-pure water industries, as well as harsh chemical applications. The high cycle life of the valve ensures reliable performance in critical applications, and its compact design fits tight equipment.

DEK, South Hall, booth #811
The company will demonstrate a full line solution that incorporates a Galaxy Thin Wafer System and a next-generation CHAD WaferMate wafer handler. The line resolves traditional challenges associated with high-speed handling and processing of thinned wafers on a proven print platform. With the ability to process as many as 60 wafers per hour (wph), the DEK and CHAD technology pairing offers semiconductor specialists a high-volume, high-accuracy thin wafer platform that enables precise printing processes for wafers as thin as 75&#181m. CHAD’s WaferMate system incorporates advanced engineering principles, delivering thinned and warped wafer handling capability, movement of wafers or paper from a coinstack configuration and the ability to limit wafer contact during transfer to the print pallet so as to avoid any damage to delicate, thinned wafers. Once placed on the DEK thin wafer pallet, which can accommodate wafers as large as 300mm and is flat to less than 10&#181m, the Galaxy transport system precisely and quickly transfers the wafer-loaded pallet into position. Advanced vision capabilities align the wafer and the specified imaging process commences. Packaging techniques including ball placement, DirEKt Coat wafer backside coating, protective coating imaging, thermal interface materials deposition, wafer bumping, and encapsulation processes can all be accomplished with exceptional accuracy and precision at high UPH. For DirEKt Coat applications, which will be demonstrated at Semicon West, the new Galaxy Thin Wafer System delivers a process capability of Cpk>2 @ ±12.5&#181m with a Total Thickness Variation (TTV) of <7&#181m on 200mm, 150&#181m-thin wafers for coatings as thin as 25&#181m. During the live demonstrations, wafer transfer and loading of 120&#181m wafers will be carried out by CHAD's WaferMate handling system.


Sonoscan’s AW300 inspects bonded wafers.
Sonoscan, South Hall, booth #407
The C-SAM series AW300 for bonded wafer inspection carries out robotic handling and acoustic imaging of bonded wafer pairs up to 300mm in diameter. Twin transducers scan two wafer pairs simultaneously, while the two previously scanned wafers are dried and returned to their carriers. An industry standard equipment front end module (EFEM) is SECS/GEM ready, accommodates single or multiple load ports, and utilizes either vacuum or edge grip end effectors. The scanner system utilizes linear motors and is inertially balanced for vibration-free operation.

EV Group, North Hall, booth #5547
The EVG770 UV-based nanoimprint (NIL) step-and-repeat system addresses large-area master fabrication for optical applications and replication of high-resolution features. It supports hard and soft UV-NIL as well as micro-contact printing applications for wafer sizes ranging from 100mm to 300mm. Features include a dual-stage alignment approach, a high-precision wafer stage for sub-50nm placement accuracy, the ability to imprint in a vacuum, and support for semi- and fully-automated wafer and template transfer. Other applications include the manufacture of waveguides, ring resonators and R&D nanoelectronics applications (i.e., dual damascene and contact holes).

Finetech, South Hall, booth #712
The Fineplacer Lambda, with ±0.5&#181m placement accuracy, will be shown in a manual configuration capable of sophisticated die-attach tasks such as bonding of flip chips, MEMS, MOEMS, and sensors on substrate sizes up to 180 &#215 136mm. A FA7 heating plate offers a 50 &#215 50mm heating area, high ramp rate, excellent thermal conductivity, very low thermal expansion, and optional heated inert gas integration. Applications include eutectic soldering, Au/Sn soldering, thermo compression, thermo-/ultrasonic bonding, adhesive technologies, and MEMS/MOEMS placement.


ECT’s Z pin test probe.
Everett Charles Technologies, a subsidiary of Dover Corporation, South Hall, #331
The Z pin, or “Zip,” features a patented 2D design with planar contact surfaces fabricated by a proprietary test pin manufacturing process. The Zip Family of compliant contacts deploys planar contact surfaces on scalable test pitch products. The Z pin is available in radial, flat, and hybrid configurations. The Radial Series uses traditional machined 3D components; the Flat Series uses innovative 2D components; and the Hybrid combines both technologies, a flat contact for the interface board married with a radial contact for the DUT. Multiple plating options are available with test pitches of 0.4, 0.5, and 0.8mm. The 1.00 and 0.3mm designs are scheduled for a Q3 release. Other probes displayed in the booth will include the Bantam for demanding test applications; the Mini-Mite for higher current and consistent DC resistance requirements; and the CSP series that addresses double-ended Pogo technology applications with drop-in compatibility for most competitor test probes.

Kyzen, South Hall, booth #910
The Aquanox A4520 aqueous cleaner for flip chips and advanced packaging is effective on all lead-free, no-clean, and eutectic materials when run at low temperatures and low concentrations &#151 including lead-free flux, tacky flux, reflowed paste, no-clean flux, RMA flux, OA paste, oils, fingerprints, light oxides, and polymerized soils. Features include a long bath life, RoHS compliance, no CFCs or HAPs, and it is biodegradable.

Synopsys, South Hall, booth #2221
The Fammos software tool analyzes stress evolution for the entire interconnect fabrication process, using design database and process to perform 3D backend process simulations. It predicts interconnect stress distributions from multiple stress sources (intrinsic, thermal-mismatch, grain-growth, and externally applied) and accounts for proximity effects, and can detect stress hot spots that are susceptible to debonding, voiding, and cracking, and employs a set of physics-based models to evaluate reliability failures. Fammos generates stress distributions to mitigate reliability issues during through-silicon via (TSV) fabrication and 3D IC stacking, and computes stress-induced mobility changes in transistors in proximity to TSVs.

Technical Manufacturing, North Hall, booth #5765
The Stacis FP active vibration cancellation floor platform system suits use with scanning electron microscopes (SEMs). Features include sub-1Hz cancellation, extended stroke piezoelectric actuators, and damped, powder-coated steel plates sandwiching 4 isolators and a digital controller. An active hard-mount floor platform fits most commercial SEMs, and the tool is compatible with all internal SEM vibration isolation systems. The <400lb system supports more than 2500lbs with no soft air suspension.

Virtual Industries, South Hall, booth #817
Several vacuum handling systems will be on display. The TV1000 vacuum handling tool handles a variety of optics, ball lenses and SMT parts sized 250µm to several inches in diameter, with a long-life diaphragm vacuum pump that generates up to 10&#34 of mercury with an open air flow of 2.3 lpm. The Stealth-Vac Elite vacuum pen operates directly on compressed air or nitrogen, with air conservation features; vacuum level can be controlled by adjusting the input pressure. The Porta-Wand Elite with PEEK wafer tip handles up to 200mm wafers or solar cells. A Push Button Vacuum Wafer Wand accepts any of Virtual’s press fit tips for handling solar cells or semiconductor wafers.

Rudolph Technologies, South Hall, booth #1621
The MetaPulse-G thin-film metrology system targets copper damascene process from 45 to 22nm and copper via fill in 3D ICs. Features include a green wavelength ultrafast laser, optimized for copper applications, that delivers higher signal/noise ratios and measurement repeatability better than 0.3% at throughputs of 60-80 wafers/hour. A 10 &#215 10&#181m spot size can measure films within 30 &#215 30&#181m or smaller test sites, and in active die on product wafers at high-volume throughputs. A time-resolved acoustic signal can be used in active die in the absence of special underlying test pads.

For more new products at SEMICON West, visit www.semi.org.

(April 21, 2009) T&#196BY, Sweden &#151 Micronic Laser Systems AB intends to acquire MYDATA automation AB. In the proposed transaction, Micronic would acquire MYDATA from Skanditek Industrif&#246rvaltning and the minority shareholders against payment in the form of newly issued shares in Micronic. Combining Micronic and MYDATA will create large potential within the market for electronic packaging using Micronic’s and MYDATA’s complementary imaging and deposition technologies.

Following the transaction, Skanditek Industrif&#246rvaltning will be the largest shareholder in Micronic, owning approximately 38% of the capital and votes. The transaction is expected to result in operational synergies as well as reduced financial volatility for the combined company, according to Micronic, and would have annual sales of SEK 1.2 billion based on 2008 performance, approximately 640 employees, and operations in 11 countries. MYDATA, headquartered in Bromma, Sweden, has approximately 290 employees. Operations such as development and manufacturing are conducted in Sweden. The company also has sales and service operations in the U.K., Germany, France, the Netherlands, the U.S., Japan, Singapore, and China. In 2008, MYDATA reported sales of SEK 625 million and an operating loss of SEK 31 million under Swedish GAAP.

Combining Micronic and MYDATA will create large potential within the growing market for electronic packaging using Micronic’s and MYDATA’s complementary knowledge and experience in this market, according to Micronic. Micronic sees an opportunity to develop new products within the field of electronic packaging in PCBs. Micronic has technology with superior precision and data handling for image formation in the area of advanced electronic packaging. MYDATA has a strong PCB industry history and the MY500 product for direct write or jetting of solder paste. Micronic plans to develop these technologies into products for silicon circuits through finished PCB markets.

Micronic Laser Systems AB is a Swedish high-tech company engaged in the development, manufacture and marketing of a series of extremely accurate laser pattern generators for the production of photomasks. The technology involved is known as microlithography. Micronic’s product offering also includes metrology systems for display photomasks. MYDATA designs, manufactures, and markets SMT process equipment based on a modular hardware and software design for high-mix/high-yield production. The company’s products are focused on faster changeovers and set ups, and on achieving the lowest possible cost per mounted component.

The companies are similar enough to already today benefit from synergies by coordinating sourcing, R&D efforts, and administrative functions, Micronics asserts. There will also be cooperation benefits by a more optimal use of the two organizations’ production facilities. The two companies are today operating on somewhat different geographical markets, Micronics adds, stating that the acquisition would create opportunities for MYDATA to strengthen its presence in markets where Micronic is strong such as Japan, South Korea, Taiwan, and China.

Micronic operates on a market with low short-term demand visibility and high cyclicality that makes the company’s sales and profits volatile. MYDATA’s markets are also cyclical, but with a business cycle that is more stable than Micronic’s. MYDATA’s business is based on a structure with a large number of small customers, which differs from Micronic’s structure based on small number of large customers. Combining Micronic with MYDATA is thereby expected to reduce the overall volatility in sales and profitability. Given the relatively small size of both Micronic and MYDATA, a combination of the two companies would likely have a positive effect in the capital markets.

Based on Micronic’s closing share price on NASDAQ OMX Stockholm on April 20, 2009, of SEK 13.50, the market capitalization of Micronic totaled SEK 529 million, implying a value of MYDATA of SEK 352 million. Based on Micronic’s average closing share price on NASDAQ OMX Stockholm over the preceding 30 trading days of SEK 9.96 per share, the corresponding values totaled SEK 390 million and SEK 260 million for Micronic and MYDATA respectively. Skanditek will have the right to appoint two of five (or corresponding ratio) board members in connection with Micronic’s extraordinary general meeting to be held on July 2, 2009.

Due diligence will take place immediately, concluding on May 12. A prospectus will be made public on June 16. The newly issued shares, should the acquisition proceed as indicated, will be included in trading on NASDAQ OMX Stockholm on July 13. The transaction is conditional upon, inter alia, that an extraordinary general meeting (EGM) in Micronic approves the new share issue of approximately 26.1 million shares with payment in kind as well as an amendment of the articles of association in order to enable the new share issue, which requires support of shareholders representing not less than 2/3 of the votes cast as well as of the shares represented at the EGM. The Board of Directors of Micronic intends to summon an EGM once a binding share purchase agreement has been entered into between Micronic and Skanditek.

Carnegie is acting as financial adviser and Advokatfirman Vinge is acting as legal adviser to Micronic in connection with the Transaction.

A conference call will be held this afternoon at 15:30 CET where investors, analysts, and media will be given the opportunity to ask questions. Persons interested in participating on the conference call can email [email protected] or call +46 8 638 54 64 before 13.00 CET.

For more information, visit www.micronic.se.

March 31, 2009 – Budapest, Hungary-based Semilab is staking its claim in the metrology sector with a pair of new acquisitions to broaden its portfolio and cement a foothold in Tier 1 fabs.

The two new acquirees — Advanced Metrology Systems (AMS) and QC Solutions — are being folded into a new Massachusetts-based division called Semilab AMS, each bringing to the table different components of metrology technology to beef up Semilab’s expertise in materials characterization. AMS offers metrology technology for characterizing 3D etched structures including high aspect ratio contacts and trenches; metal film thickness on product wafers; and high-speed online mapping of low-k material properties. QC Solutions offers noncontact nondestructive systems to accurately and repeatedly measure electrical properties of epitaxial and implanted silicon wafers.

The deals came about, according to Chris Moore, president/CEO of now Semilab AMS, because a mutual industry acquaintance to both Semilab and AMS recognized synergies. “They approached us. quite a while ago — early last year, before the major downturn,” he told SST. AMS’ private equity owner, JHW Greentree Capital, wasn’t shopping its AMS investment, but in the world of PE there’s always an eye to making a satisfactory return. At first the response was “interesting, for some day,” Moore said; that eventually bloomed into a cooperation between sales channels, then expanded to Semilab realizing that it would make the most sense to just buy them.

The timing was just fine with AMS’ owners, who had just the one asset in the semiconductor industry, and weren’t prepared for the sudden unpredictability in the market since the DRAM market tanked. Once the economy headed south too, modeling after past cycles wasn’t viable, and an unpredictable market proved a bit too distasteful. (Moore wouldn’t provide specifics of the all-cash transaction, but did say that Semilab “took advantage of the times.”)

Semilab is strong in solar and materials characterization, but it suffers from a lack of industry clout — it’s “the largest unknown metrology company,” Moore quipped, and it doesn’t have much business online in Tier 1 fabs. And that’s where AMS comes in. “Semilab saw two things [in AMS]: a small company selling to Tier 1 fabs, and technologies complementing their base.”


Chris Moore, president/CEO of Semilab AMS

In terms of technology, the key to Semilab’s strategy is a collection of technologies that can be combined and applied to certain key applications. Much of it has been assembled via M&A over the past couple of years: noncontact electrical (QC Solutions), contact electrical (SSM, majority share bought in March 2008), optical, and x-ray (via Sopra, September 2008). One example Moore cited: a conceivable tool that could handle pre- and post-anneal, combining Semilab technologies from AMS and Boxer Cross (acquired from Applied Materials last fall), with noncontact electrical tools (QC Solutions) for epitaxy. Another example: high-k. Semilab’s lineup of technologies spans thickness, roughness, and k value (via spectroscopic ellipsometry and x-ray), and leakage (via SSM) — “if you know those four, you know everything you need to know about high-k,” he said.

While cluster-type tools aren’t a new concept, most companies wouldn’t do” setups like the aforementioned examples, instead focusing on a more narrow expertise, Moore said. And for 300mm Tier 1 fabs, that solves a big pain point in moving material between tools. “It’s a lot better [for the fab] to have one tool with one move, get the information you need, and then go on to the next problem,” he said.

How is Semilab positioning itself in the metrology sector vs. competitors?

“We have no intention of taking on KLA-Tencor head-to-head. They do a lot of inspection and software, but not a lot of metrology. Semilab [with its acquired units over the past year] is strong in metrology in a number of areas. We get availability of common platforms across groups, which lowers production costs; we now have a direct sales and service worldwide. Both improve our ability to work directly with higher-end fabs.

How tough is it to get business in Tier 1 fabs in the current environment?

“The downturn makes it easier…they have more time, more attention when they’re not running full-out. It’s not easier to sell [equipment], but it’s easier to get evals. [Our message is that] we have a track record with a company that has already supplied you with equipment you like, and now we’re backed by a bigger player — and now we have support people in your area.”

Are fabs more receptive to evals in the past few months, if not actual tool sales?

“At AMS, not really. It’s easier to talk to them and keep their attention span; the last four or five weeks we’ve been talking to our customer base, they come up more & more with, ‘Can we do this-and-this’ stuff. Overall, is it easier [to get business?] Probably. It’s not something AMS could take advantage of — but Semilab can.”

What’s your take on consolidation in the current industry/macro environment, and the need to build critical mass to survive?

“I’m not sure if it’s consolidation or failures. It comes down to, do you buy the assets of a player, or buy their technology? If it’s a medium-sized firm (>$10M-$15M), do you just let them go [away]? If you’re a bigger player you may not want to take on a struggling firm’s legacy products, you can’t leverage money out of it…they must have something really new and nice, that you can do something with it.

“Attrition is a better word. Watch for a lot of ‘walking wounded’ metrology companies. Fabs are moving ahead — they’re not buying lots of equipment, but they need [to support their] next-generation processes. That’s tough to do when you’re a small [supplier]. This speaks to critical mass, and in more than one industry. Those with critical mass in just semiconductors are really hurting now. Semilab has critical mass in solar too.

“Back in 2007 there were niche markets; you could grow to a reasonable size. As long as you worked with customers and provided what they needed, critical mass wasn’t an issue. But then customers stop planning — that’s what happened in 4Q08, they literally froze for more than a quarter. At that point, you start to look at functional resources, how to get to a broader market base. You’re good in that niche, but they’re frozen. Then the question becomes: what do the deep-pockets owners want to do? How shellshocked are they too?”

We have to ask — what’s your take on the state of 450mm tool development?

“Semilab has a 450mm tool because they’re working with wafer makers. Semilab AMS has done design work on a 450mm tool. But for us, 450mm is a scaling issue; we need bigger bridges, wafer handlers, etc. But we’re not trying to deposit on a bigger wafer; that’s not our problem.

“The market [for 450mm] may develop, certainly for manual tools, for people to build 450mm wafers and epitaxy. People are starting to work on this. Once you have those tools, wafer handlers take it. We expect to be doing serious work…testing for SEMATECH and others. Some of that work is on upscale 300mm tools, of course. Once the wafer handlers are sorted out, it’s not a hard integration problem. That doesn’t negate the need to work with chucks, holders, etc., but it’s not the same level of problem as building a process tool…and we can build in stages — a manual load — for R&D work for the next few years, before ever having to do an automated system.”

When do you foresee 450mm becoming a manufacturing reality?

“450mm will be controlled by two things: when fabs put serious money on the table, and when equipment firms want to do it.” — J.M.

March 25, 2009: Just as X-ray technology, MRI and sonography transformed the practice of medicine, a newly created approach for seeing the invisible promises great potential for finding new ways to improve the health of human and microelectronic patients alike. Semiconductor Research Corp. (SRC), a leading university-research consortium for semiconductors and related technologies, has joined with Northwestern University to announce successful demonstration of a unique ultrasound holography approach that enables scientists to view the tiniest of buried structures.

The resulting three-dimensional information will provide benefits ranging from greater yields for semiconductor manufacturers to more effective treatments for medical patients.

Using a novel, non-destructive approach that combines, for the first time ever, scanning-probe microscopy (SPM) with ultrasound and holography, researchers at Northwestern University have demonstrated the ability to view subsurface particles as small as 15-20nm (one billionth of a meter). Such capabilities have not previously been possible without slicing the sample, which changes both the composition and structure and sacrifices characteristics of the studied subject.

What makes the new approach revolutionary is the combined use of the SPM, ultrasound and holography. SPM offers nanoscale resolution. Ultrasound is non-destructive, transparent to all materials and sensitive to embedded structures, including nano-sized defects. Holography also can provide sophisticated three-dimensional representations of the buried information. Together, the three technologies offer unprecedented visibility to the increasingly important tiny parts of nature.

As there’s neither a similar approach nor such a high class of result available anywhere, a high-tech start-up company has been launched to further the commercial applications for these methods. Named NanoSonix Inc., the spin-off will develop a nanoscale-imaging toolset capable of rapid evaluation of defects and flaws below the surfaces as well as valuable recognition of buried patterns and structures.

“Microelectronics, in particular, is a flaw-intolerant technology where even nanoscale defects can compromise the performance and yield of the devices,” said Dan Herr, director of nanomanufacturing sciences for SRC-GRC, an entity of SRC. “The ability to see such defects is critical for yield enhancement as devices become smaller and such metrology techniques and tools become even more crucial. These results are very good news for multiple industries.”


New subsurface, embedded defect analysis will be more accurate than any other imaging process, spurring a spin-off company to commercialize the technology. (Image courtesy of SRC)

Utilizing the new technology, the microelectronics and nano-electro-mechanical systems (NEMS) industries can improve performance of their devices, time to yield and, ultimately, yield rates by deploying this technique in process development and as an in-line quality control tool. Thanks to the non-destructive imaging approach, the pharmaceutical industry should benefit from better understanding of how drugs distribute, accumulate and clear from different parts of the body.

“Biomedicine is moving towards use of nano-bio-structures to interrogate cells and deliver therapeutic cargo. This requires a non-invasive view inside the cells to monitor what’s happening under physiologically viable conditions,” said Dr. Vinayak Dravid, professor of materials science and engineering and the director of the NUANCE Center at Northwestern University. “With the new imaging technology, it’s possible to sharply increase our understanding of the bio-distribution of new drugs and the important interactions of nanoparticles and cells during intended or desirable therapeutic delivery or unintended environmental uptake.”

Next steps in development of the technology include system integration, material handling, faster scanning and high throughput of results. In-line tools and methods for addressing these needs will be created by NanoSonix. For instance, in the next 12 months, the spin-off will develop an add-on module for existing commercial SPM equipment in order to meet associated off-line metrology requirements. Availability of such an add-on module will make this technology accessible to a wider community, not only in semiconductor metrology but also in bio-application for both academia and industry to look deep below surfaces non-destructively with nanoscale resolution.

by Griff Resor, Resor Associates, SST editorial advisory board

Experts say we’re on an ‘optics forever’ path, but EUV is gaining momentum and closing the gap, though the finish line is still several years away (and may keep moving). This year’s SPIE’s Advanced Lithography Conference in San Jose, CA, provided a detailed update on what is becoming a tight horse race.

The 32nm node is going into production now, with 193nm immersion optics, double patterning, improved overlay, and a bunch of new processes and materials. In two years the 22nm node will move into production; most expect this node will be done with yet another extension of optical lithography. It is clear, though, that if EUV were ready now, many process engineers would like to use it. C.K. Bok of Hynix was quite frank: “I want to use EUV [for the 22nm node] but my boss makes me work on optical lithography too, because EUV might not be ready and we have to have a solution.”

The ‘optics forever’ story

ASML, Canon, and Nikon continue to improve their 1.35 NA optics, providing improved polarization control through the projection lens, and new layers of feedback to control lens heating. Brion introduced software to analyze each mask and generate “source-mask co-optimized illumination”, a technique that increases the process window at 32nm by over 40%. Excimer laser bandwidth and speckle are being understood at levels of perfection formerly neglected because they add only a few nanometers of error. These improvements now provide an adequate process window for the 32nm node.

Which form of double patterning technology will be most widely used at the 32nm node is not clear. Spacer technology may provide better-defined structures (because chemically amplified resist can be replaced with smoother edged material) and does not require as tight a tolerance for overlay — but spacer technology appears to be more expensive. Suppliers of resists are developing coatings and/or process steps to “freeze” (harden) the first resist pattern so that a second pattern can be imaged next to the first pattern before etching the underlying layers. Probably all methods for double exposure technology will be used at the 32nm node, as the industry optimizes the process for each chip layer.


Figure 1: ASML’s new Mag-lev stage. (Source: van de Mast/ASML)

ASML, Canon, and Nikon also announced new platforms that will provide the very tight overlay required by double patterning. ASML’s NXT platform [Figure 1] will stay with its two-stage design, but can now move each stage directly using mag-lev technology, a change that reduces the stage mass 67%. By increasing stage acceleration and shortening overhead time, ASML plans to reach 175 wafer/hour (wph). The stage metrology is also new [Figure 2], now referenced to gratings mounted on a metrology frame at the bottom of the main lens. By shortening the air path, overlay errors have been significantly improved, less than 2.0nm (mean + 3σ)


Figure 2: ASML’s new grating based stage metrology. (Source: van de Mast/ASML)

Nikon will stay with a single stage, with first priority to reduce overlay errors. The new Nikon platform uses a hybrid metrology approach. Gratings on the stage around the wafer can be referenced to a metrology frame at the bottom of the projection lens. Stage interferometers will be retained to speed system calibration. Five alignment and focus sensors at an alignment location will shorten alignment time and gather more data during alignment. The stage will scan the wafer under these sensors in a single pass so multiple alignment and focus data can be gathered quickly. Targeted throughput is 200wph.

Optical lithography systems cannot move to higher numerical aperture (NA) lenses. Schott’s latest attempt to make improved high-index lens material failed and the project has been stopped. Optical scanners will have to work with the NA=1.35 lenses that they have now. This makes the push of optics to 22nm even more dependent on process tricks and computational lithography. Design choices will be even more limited. Will there be enough optical process window for production at the 22nm node?

Line-width roughness (LWR) is another serious issue. ASML presented a detailed analysis of excimer laser-induced speckle. Only about 30% of LWR can be attributed to this source. The statistics of photo-acid generation in chemically amplified resists remains the number one challenge.

The EUV story

Full-field (26 × 33mm) EUV scanners are operating at SEMATECH and IMEC (both ASML) and at SELETE (Nikon). SEMATECH reported its alpha demo tool has been operating for nine months. A source upgrade has boosted the pace of experiments. So far IMEC has seen no decay in the transmission of the projection optics — resist outgassing and general vacuum contamination were anticipated problems. SEMATECH reported that by adjusting slit uniformity, CD uniformity was brought into spec. Output is about 4wph, but many sites are not being exposed on test wafers, so real output may still be about 1wph. Nikon’s EUV-1 at SELETE has just begun resist experiments.


Figure 3: Comparison of image quality, 193i vs. EUV. (Photos courtesy of Gil Vandentop of Intel)

EUV images look great — clearly better than comparable 193i images [Figure 3]. Process windows also are significantly better [Figure 4]. 90% of mask defects are not printing, a much better result than predicted. Flare has been measured at 12% to 17% on the three alpha tools, mostly measurement uncertainty; EDA software can correct for flare, which will be reduced to 5%-8% on EUV production tools. Some rule-based OPC has been tried; off-axis illumination and model based OPC probably will be needed for the 22nm node. In general, though, mask design and process control will be much simpler for EUV single exposures with a k1 = 0.50.

Mix-and-match overlay with 193i tools does not yet meet the goal for a single-exposure process at 22nm. But in general, problems are not expected — toolmakers clearly understand how to push the overlay learning curve.


Figure 4: EUV has a much larger process window. (Source: Meiling/ASML)

Nearly all infrastructure items appear ready for EUV. Metrology to build, assemble, and test EUV lenses is ready at all three suppliers. EDA tools needed to make EUV mask adjustments (CD and overlay) and OPC adjustments are available, though process models are not done — resist choices need to be made, and the first production tools are needed. Mask blanks are available; at-wavelength defect inspection of blanks is being developed at SELETE. E-beam patterning of masks is ready. An at-wavelength AIM tool is being developed at Lawrence Berkeley National Labs to determine which mask defects print. One key EUV infrastructure tool is missing: a KLA-Tencor type of tool for scanning patterned masks at high speed and identifying potential defects. Intel says this could be showstopper.

For throughput, another major concern, the picture should improve dramatically over the next 12 months. ASML plans to have its first Gen1 tool installed by mid-2010: a 0.25NA tool with 60wph throughput, upgradable to 100wph as source output increases from 100W to 200W at the intermediate focus. A 10mJ/cm2 resist is assumed. ASML’s plans depend on Cymer’s progress; the supplier reported that factory acceptance testing of its first production LPP source is scheduled for March 2009. Its test platform has reached 40W average power, using a 400 msec (one field) burst and a 40% duty cycle. This should be ramped to 100W average power by the middle of 2009. Cymer will continue to push up the power of its LPP sources to 400W at the intermediate focus. The increased power will provide 175wph using 15mJ/cm2 resist, scheduled for 2012 installations.

Yet another problem area is resist. Gil Vandentop described Intel’s work to screen over 250 EUV resist formulations. Most of this work was done for 32nm half-pitch; they are now shifting to 22nm. Intel has found that an added rinse after post-exposure bake can smooth line edges and clear spaces; an under layer is recommended. Sensitivity can be as good as 8mJ/cm2, though line-edge roughness [LER] needs to be reduced 2X; resist sensitivity in other talks ranged from 9mJ/cm2 to 48mJ/cm2. EUV cost models should anticipate only slower resists will be available in 2011.

The team at Berkeley Labs has determined some LER is caused by EUV mask mirror roughness, which introduces small phase errors. When out of focus, 60%-80% of LER could come from this problem. At best focus a portion of the LER probably comes from absorber edge roughness. The absorber contribution remains to be determined.

Lawrence Berkeley National Labs is upgrading its micro-exposure tool to 0.30 NA, with simultaneous improvements to beam uniformity and off-axis illumination capability. This tool may be the best location to test resists for the 22nm node.

Seth Kruger of the U. at Albany introduced the concept of an acid amplifier for chemically amplified resists. The idea is to have photon-generated acid react chemically with a new resist component to add acid molecules [Figure 5] and make the resist more sensitive. But speed is not the goal — instead, more quencher will be added to shorten the diffusion length. The combination should improve PAG statistics and produce smoother lines. More work is needed to see if shelf life and production goals can be met.


Figure 5: Chemically amplified resist (CAAR) concept. (Source: Kruger/Brainard, U. at Albany)

Some evidence suggests that out-of-band radiation may be degrading full -field images. EUV resists are being adopted from 193nm and 248nm resists. They are sensitive at these longer wavelengths. At present, there is no filter in EUV systems to block this light. Modified mirror coatings or a thin-film window may have to be added to fix this problem. Expect a 2X reduction of light through the system. As an offsetting factor, the lens coating process continues to improve, centering the reflectivity at 13.5nm. A gain of 2X is expected. These two trends should offset each other.

Even if EUV can be ready in time (Gen 1 units in 2010, Gen 2 units in 2011), will they be economical? ASML, Nikon, and SEMATECH have presented separate analyses, all showing the same general picture [Figure 6] that EUV will be cheaper than 193i using double exposure at the 22nm node. This is true even when an $89 million price is assumed for the EUV tool (vs. $52 million for the 193i tool), EUV output is only 100wph vs. 200wph for the optical tools, and mask blanks cost $60K for EUV vs. $3K-$5K for optical mask blanks.

SEMATECH’s analysis looked at breakeven points for throughput and uptime, calculating that initially 40-70wph and 70% uptime will be sufficient; by 2011 EUV tools are expected to do much better than this. The SEMATECH model looks at a range of assumptions for double exposure technology, mask cost, and prints per mask. At 20,000 prints per mask the EUV lead is clear; at 1000 prints per mask the EUV solution costs very little more than today’s 45nm half-pitch single exposure processes. Mask cost is the most important issue. Yields were assumed to be equal for either kind of tool; but data shows a significantly larger process window for EUV single exposure tools. So the yield outcome probably favors EUV.


Figure 6: SEMATECH cost-of-ownership model results. (Source: Wüest/Hughes, SEMATECH)

Will the finish line move?

Nobody will openly discuss the possibility of a delay to the 22nm node — Intel even said they would not delay — but several issues might hold things up. Resist, which has been a problem for 193nm immersion, looks to be a common problem for 13.5nm EUV as well, and may not be ready in 2011 for the 22nm node. Existing optical scanners have demonstrated good 30nm line-space resolution with a useful process window. The EUV alpha demo tools have demonstrated 27nm line-space resolution with a useful process window. At this time, neither technology has been able to push line-space images to 22nm. Line-width roughness is clearly a challenge for both technologies. Details have been discussed already. We may see an intermediate node around 27nm as people hedge and wait for EUV.

DRAM companies talked about launching the 22nm half-pitch node in 2011 with 193i tools, then switching to EUV tools for first via and metal-1 layers as soon as possible. In this scenario, space could be planned in the fab for two or more EUV tools. 193i tools can be used to start production, and then be shifted to less critical layers as EUV production tools arrive. Of course, the current economic crisis (Great Depression 2.0?) may force changes none of us have seen in prior downturns.

As I left the SPIE conference I was asked, “Why did SEMATECH move to Albany?” My answer was, half kidding, ‘It’s the money.’ But then I paused on some observations: the EUV mask program moved to Albany a few years ago; the EUV alpha demo tool is there now; and a full pilot line has been built in Albany to test EUV on real chips at the 22nm node. Last year AMD went to Albany to make the first metal layer on a 45nm chip using EUV (and the chip worked). Even SEMATECH’s press staff has moved to Albany. Clearly SEMATECH has moved to EUV; this could be symbolic. Will the IC industry follow them to EUV? We won’t know for sure until 2011. But this is clearly a close race with EUV closing on the incumbent optical lithography. Any delay of the 22nm node will help EUV. — G.R.

AUSTIN, Texas — International SEMATECH Manufacturing Initiative (ISMI), the global consortium of the world’s major semiconductor manufacturers, today announced the launch of its new Environment, Safety & Health (ESH) Technology Center in Austin, Texas. The Center will be dedicated to providing green technology solutions that lead to reduced energy consumption, lower costs, and greater productivity in semiconductor manufacturing.

"Given the global environmental challenges we face, we believe there is nothing more important than energy and resource conservation," said Scott Kramer, vice president of manufacturing technology at SEMATECH. "Our objective in launching the ESH Technology Center is to lead the effort to keep our industry’s manufacturing businesses productive, profitable, and sustainable, while significantly reducing the environmental footprint of manufacturing operations."

In addition to the current ISMI members, who represent over half of the world’s semiconductor production, participation in the ESH Technology Center is open to all chipmakers and equipment and materials manufacturers. Adopting ISMI’s successful collaborative model, the Center’s participating companies will share ideas and resources, and direct, continuously evaluate, and refresh the program portfolio.
The new Center will drive ESH programs, built over 15 years by SEMATECH and ISMI, to: 

  • promote energy and resource conservation through technical evaluations and demonstrations;
  • advance green semiconductor operations and processes;
  • provide forums for sharing ESH benchmark data, surveys, and best practices.

As an example of the Center’s work, past projects have demonstrated 10-20% utility reductions by adopting best practices in ultrapure water recycle/reclaim and cleanroom HVAC optimization. The new Center will continue this focus on practical and cost-effective engineering solutions, and target other important areas such as energy reduction in process equipment.

"At the Center we will work through all levels of the supply chain to address the industry’s need for sustainability, productivity, and cost-effectiveness," said Ron Remke, ISMI’s ESH program manager who will head the Center. "We’ll be a source of data-driven best practices to tackle the challenges of sustainable manufacturing and act as a proving ground for technology solutions."

"Sustainable manufacturing is vital for the long-term growth of the semiconductor industry," said Kramer. "There is a high level of interest in the Center, and we’re convinced that it will bring significant value to existing ISMI member companies and new participants alike. We all share a common commitment to what is good for business and good for the environment, and together, we can do great things."
More information on the ESH Center and its initiatives is available at the ISMI website at http://ismi.sematech.org/esh.

ISMI is a global alliance of the world’s major semiconductor manufacturers, dedicated to reducing cost per wafer and ultimately cost per die, through cooperative programs focused on manufacturing effectiveness. ISMI’s current program portfolio includes ESH, next-generation factories, 450mm, continuous improvement, and metrology. ISMI is a wholly-owned subsidiary of SEMATECH (www.sematech.org).

ISMI Erica McGill, 518-956-7446 [email protected]

by Meredith Courtemanche, contributing editor, PV World

Jan. 12, 2009 — With the economy and oil prices plummeting, the solar cell industry is fighting to retain the interest, investment, and production volumes it gained as a result of the recent energy crisis and environmental awareness. Rudolph Technologies Inc. introduced a software package targeting the still-troublesome area of photovoltaic cell efficiency, hoping to bring solar cells closer to grid parity through reduced costs and inefficiencies.

Rudolph pulls product value from a mature production field — semiconductors — for its Discover Solar software package. The company asserts that cell efficiencies still have significant room for improvement, while competitions and attention to costs have escalated. Discover Solar is designed to automate process control and perform root cause analysis closer to real time.

Discover Solar is a fab management software tool designed to help photovoltaic (PV) manufacturers increase cell efficiency and reduce costs. Rudolph claims that the software, which operates with in-line data, reduces scrap and downtime by identifying root-causes of yield issues. For a PV cell manufacturer producing 7,500,001 30-MWp line wafers per year, the Discover Solar tool can cut out $495,000 in scrap, $90,000 in inefficiencies, and $87,600 in engineering costs, according to Rudolph, citing cost analysis data from a PV fab.

While Discover Solar is based on Rudolph’s semiconductor manufacturing process control software, the company acknowledged that they had to consider “everything differently” when designing software for PV lines, primarily due to the high volume of silicon wafers and the varying degrees of raw material quality. Discover Solar incorporates a re-engineered database structure and analysis engine optimized for the requirements of high-volume photovoltaic production. “Not a lot of in-line metrics are available in PV facilities, as compared to the semiconductor world,” states Mike Plisinski, VP and GM of Rudolph’s data analysis and review business unit. Root causes of useless solar cells or those with poor energy conversion efficiency are less easily tracked, he added. Using in-line metrology, equipment, and cell test data, the software’s path analysis equations allow for faster and more automated correlation between a problem and a specific line, line tool, or batch of wafers.


Discover Solar automatically identifies specific tool or process issues. (Source: Rudolph Technologies)

Discover Solar allows engineers to pinpoint a problem on the process tools (e.g., chambers, tubes, zones, or print tables), inline metrology (resistivity, thickness, color), tool input parameters (temperature, pressure, gas flow), and cell test data, by showing out-of-spec results after a particular process during PV manufacturing. The software can also call out a bad batch of wafers by identifying variations between wafers run over the same recipe in the same tools. Finally, it can alert users to “hidden” correlations between scrap or inefficient cells and multiple errors at different steps, resolving or preventing “second-order effects,” Plisinski asserts.

To accommodate the throughput volume at PV facilities, these path analyses are performed in seconds, according to Rudolph. Discover Solar also has alarming functions, which can be set to report out-of-spec operation automatically. It replaces slow, engineer-intensive statistical process control methods, such as SAS JMP or Excel programs, says Plisinski.

Rudolph is targeting process optimization and health monitoring with the software release. Discover Solar has been tested at a manufacturer, and testing is underway with different applications within the product’s scope. — M.C.

Chin-Chou Kevin Huang, David Tien, KLA-Tencor Corp., San Jose, CA USA

More challenging overlay requirements are driving a trend to use high-order control knobs for production set-up of scanners. This article explores the overlay requirements that are driving this trend, the challenges involved with implementing in production, and the cost-of-ownership trade-offs between different high-order control strategies.

Historically, lithographers have achieved layer-to-layer alignment control by assuming that overlay varies linearly across the wafer and across the scanner field. Although more sophisticated “high-order” control knobs have been available for use during scanner setup and optimization, they were not typically used in production. It has only been in the recent past, driven by the aggressive shrink in overlay budgets and the added complexities brought forth by immersion lithography, that these high-order degrees of freedom have finally been adopted into the production control loop [1-3]. In this article, we will explore the overlay requirements that are driving this trend, the challenges involved with implementing in production, and the cost of ownership trade-offs between different high-order control strategies.

Meeting the budget

Overlay control is a battle between overlay budget and control capability. Traditional overlay control separates the overlay data into two major components: systematic linear correctables and non-correctable residuals. Previously, the prevailing use of linear correctables was driven on the one hand by the lack of accessibility to high-order capabilities, and on the other by the relatively large overlay budgets that did not require the tighter control capabilities of high-order corrections. In Figure 1, the systematic linear correctables are illustrated in the green background, and the many other remaining contributors, as shown, are defined as uncorrected overlay residual contributors.


Figure 1. Overlay error contribution sources can be separated into three distinct categories: 1) Traditional linear overlay errors (green); 2) High order overlay errors (yellow); and 3) Non-systematic random overlay errors (gray).

Single machine overlay in current generation immersion systems is around 5nm, assuming process related contributing factors are removed. A critical layer in a typical 40nm process node usually requires overlay to be controlled within 10nm. If this overlay requirement is compared against the scanner’s capability, then it appears that the remaining tolerance or margin to accommodate typical fluctuations in overlay is quite small. Moreover, when the added complexity of double patterning lithography for the 32nm process node is folded into this problem, the overlay budget requirement shrinks well below 5nm. Clearly, minimizing overlay residuals, especially for these critical layers, is basic to maintaining low rework and high yield at the lowest cost/die.

High-order modeling

The overlay vector plot of Figure 2 shows the mis-registration vector plot for a contact layer exposed by a single immersion scanner. Overlay data was measured using a KLA-Tencor Archer 100 with 34 mAIM targets spread across the field.


Figure 2. Overlay mis-registration wafer plot before corrections: This vector plot of overlay mis-registration errors shows overlay errors as high as 26nm based on a |mean| + 3σ calculation.

Polynomial equations are used to model the overlay vector plot in the spatial x/y domain. The equations below are examples of 3rd order polynomials used to model x and y overlay vectors in each spatial domain.


CLICK HERE to view larger image

Traditionally, due to the relatively large overlay control margin at 65nm and above process nodes, overlay control knobs have been limited to the linear terms as defined by k1 to k6 of the previous polynomial equation. By using this linear model to correct the raw overlay data shown in Figure 3, the overlay correction results (referred to as overlay residuals) cannot be reduced below 10nm, which would not meet the required overlay control limits.


Figure 3. After linear corrections the overlay mis-registration wafer plot shows overlay errors to be as high as 12nm (|mean| + 3σ), which is beyond the 10nm overlay requirements for this layer.

In contrast, the modeled data shows a significantly better fit to the raw data by the full using 3rd order polynomials above for both grid and field terms as shown in Figure 4. As a result, the corrections are much better and now meet the control requirement.


Figure 4. After high order corrections the overlay mis-registration wafer plot can be reduced to 8nm (|mean| + 3σ), which now meets the 10nm overlay requirements for this layer. This represents over 30% improvement in overlay control for this layer by using high order modeling versus traditional linear modeling methods.

In addition to the selection of modeling terms, there are other factors that also need to be considered when moving to high order control. In the following, further studies will be discussed for the implementation of high-order control. These factors include source of variance analysis, sample planning, and correction efficiency.

Overlay source of variance error decomposition

One problem that occurs in the production line is that high rework rates can be attributed to repeated attempts to adjust the overlay using linear corrections, which just cannot bring the overlay within the required control limits. One way to tackle this problem of poor correction results is to understand their source and root cause. Based on a typical current generation exposure system, the residual contributors can be broken down into five components.

The first component is the wafer (or grid) level higher order (2nd + 3rd order) component. Adjustment knobs for grid components are commonly available on latest-generation scanners. The 2nd component is the wafer level higher order component (4th ~ 6th order). Adjustment knobs for this component are generally less commonly available for production usage, but some scanner vendors provide field-by-field correction functionality, which is a way to combine the 2nd to 6th order corrections together without access to all the knobs needed for individual field term corrections.

The 3rd component is the field level high order (2nd + 3rd order) component and is a component that is available with certain scanner vendors. The 4th component is the field-level higher order (4th ~ 6th order) component and is normally considered as a field level fingerprint, which usually cannot be corrected. The 5th and final component is the unmodeled component. This component can be treated as a random component that combines the exposure tool and metrology random errors. The main contributors for the unmodeled components are scanners mechanical capability, metrology tool measurement uncertainty, and overlay mark robustness. The equation below describes the decomposition of linear residuals in statistical variance domain.


CLICK HERE to view larger image

By using the above equation and ANOVA [4], the linear residuals for the contact layer shown in Fig. 3 can be broken down into five different components of variance. Figure 5 shows these individual components in a stacking variance bar chart in order to help highlight the source and impact of contribution of each component towards achieving the final overlay control objectives.


Figure 5. Source of variance in X and Y direction: The overlay variance (i.e. residuals squared) is broken down to show the source of contribution for the error in each axis using the variance domain.

Sampling strategy

The 9×4 (9 fields/wafer × 4 sites/field) sampling strategy is commonly observed in the production line. If this 9×4 sample plan is used, then the overlay can be effectively corrected at the sample sites. However, the overlay results at the unsampled locations might not be nearly as effectively corrected.

As this example shows, the sampling plan (along with the model used for correction and feedback) is a critical part of the solution when determining the overall best control strategy using the high-order modeling. In a production environment, it becomes critical to find an optimal sample plan to represent the entire overlay population with the least amount of sampling. Basically, overlay control parameters k1 to k20, as shown by the 3rd order polynomial equations above, are correctables representing the overlay population and can be solved by a least squares equation as shown in the following matrix.

Where:


CLICK HERE to view larger image

and where x and y are the coordinates of the field center for the grid correctables or the target locations relative to the field center for field parameters; and OVLm is the measured overlay value at each location.

By comparing the singular values of the H matrix (the geometrical based matrix), between the full sample and selected sample plans, one can determine the optimal sample plan and minimize the sampling effect. This same methodology can be used to select the optimal field sample plan for users to determine linear or high order modeling needs.

It is important to mention that both grid and field corrections are needed to achieve the full potential of any high-order control strategy. As shown in Figure 6, the four-corner sample plan does not adequately represent the field behavior. However, by adding an additional seven measurement points in the field, the corrections for the new eleven-point plan enables significant residual improvement.


Figure 6. Overlay mis-registration field plot after corrections using either 4 corner sampling or 11 points in-field sampling: The vector plot on the left side shows that the 4 corner (circled) sampling plan does not correct the actual errors as shown by the relatively large error vectors still remaining. In contrast, the 11 point vector plot (right side) using the in-field sample plan shows much smaller error vectors across the entire field after corrections and provides more than 35% improvement in residual reduction in this particular case.

Figure 7 shows the relationship between sample points, data modeling, and correction efficiency based on the raw data set shown in Fig. 2. Without proper modeling, there is no guarantee that the best overlay control will be obtained, even if the entire population of 4760 points is measured. High-order modeling and corrections can improve the overlay control up to 25% in this case study. Interestingly, it is not necessary to measure the full sample of thousands of overlay points to take advantage of high-order modeling. Instead, most if not all of the improvement in overlay can be gained with a properly selected sample plan determined through the optimization process.


Figure 7. Correction Improvement vs. Sample Plan: The amount of improvement in the overlay error is a function of both the sample plan and the data modeling technique. This graph shows that an optimized 24×11 sample plan using high order grid and field corrections can achieve nearly all of the improvement of a full sampling plan with significantly reduced sampling overhead. Overall, this represents a 36% overlay improvement compared with the 9×4 sample plan or 20% improvement compared with baseline sample plan.

Conclusion

As lithography continues to advance beyond 40nm, overlay control will also need to continue to move forward with new and more sophisticated control strategies. High-order correction has been demonstrated as an effective approach in meeting current 40nm overlay control requirements. The source of variance analysis technique also provides a fast diagnostic methodology to troubleshoot and de-convolute complicated overlay control issues that could otherwise consume much more time and resources. Sample planning is another important factor that needs more consideration in the move to high-order control and can have significant repercussions to not only productivity, but also yield.

Finally, an effective high-order control strategy requires both grid and field control. Although high-order grid control has become widely accessible to users with the latest generation of scanners, high-order field control still requires more collaboration between the user and vendor. Specifically, on the scanner side, adjustment knobs for field control need to become more easily accessible. Moreover, on the metrology side, high-performance small targets that can be placed in-field to capture these in-field errors also need to be readily available in order to enable a production-worthy control solution. Looking ahead, we are optimistic that these developments will continue to drive even more improved and effective high-order control strategies that can be readily integrated into production with compelling value creation for end users.

References

1. A. Sukegawa, S. Wakamoto, S. Nakajima, M. Kawakubo, N. Magome, “Overlay Improvement by Using New Framework of Grid Compensation for Matching,” Proc. SPIE Vol. 6152, 61523A, (2006).

2. T. Kono, M. Takakuwa, K. Asanuma, N. Komine, T. Higashiki, “Mix-and-Match Overlay Method by Compensating Dynamic Scan Distortion Error,” Proc. SPIE 5378, 221, (2004).

3. D. Choi, A. Jahnke, K. Schumacher, M. Hoepfl, “Overlay Improvement by Non-linear Error Correction and Non-linear Error Control by APC,” Proc. SPIE 6152, 61523W, (2006).

4. X. Chen, M. E. Preil, M. Le Goff-Dussable, M. Maenhoudt, “An Automated Method for Overlay Sample Plan Optimization Based on Spatial Variation Modeling,” Proc. SPIE 4344, p257, (2001).

Biographies

Chin-Chou Kevin Huang received his PhD in mechanical engineering from the U. of Florida at Gainesville. He is a principal engineer at KLA-Tencor, 160 Rio Robles, San Jose, CA 95134 USA; ph.: 408-875-1085; email [email protected].

David Tien received his BS chemical engineering from U.C. Berkeley and is a marketing director at KLA-Tencor.

November 28, 2008: The George Washington University has announced the establishment of the GW Institute for Nanotechnology. This institute will draw on the expertise of the University’s faculty members in mechanical, aerospace, electrical, computer, civil, and environmental engineering; physics, chemistry; and biochemistry. The institute is supported through special endowment funding designated for academic programs with the potential for a high level of intellectual distinction.
As part of the institute’s initial efforts, 16 faculty members from GW’s School of Engineering and Applied Science and Columbian College of Arts and Sciences will jointly undertake research projects related to nanostructured materials and their properties, applications and devices incorporating nanostructures, computational modeling and analysis, and nanomanufacturing and metrology. Projects already underway include developing a system for nanopatterning and scanning tunneling microscopy, studying growth of carbon nanotubes, creating computational mechanical modeling of nanomaterials, researching nanomagnetics, and constructing filtration with nanostructure materials.
“Nanotechnology is a vital area of national importance with applications across a wide spectrum from medicine to electronics to improving water quality worldwide,” said David Dolling, dean of GW’s School of Engineering and Applied Science and a professor of mechanical and aerospace engineering. “National laboratories, federal agencies, and private sector corporations all recognize the as-yet untapped potential for discoveries in this emerging field, and we believe that our engineers and scientists will be among those who unlock some of its exciting secrets. The GW Institute for Nanotechnology facilitates their task by creating an infrastructure that fosters multi-disciplinary efforts and provides research support.”
Peg Barratt, dean of GW’s Columbian College of Arts and Sciences and professor of psychology, added, “Nanotechnology calls for an extremely diverse approach, and we have a breadth and depth of experts who can gather in a common interest to explore its possibilities. The institute will build our knowledge about matter on an atomic and molecular scale, and our professors will share that science-based analysis with students and with the world.”
Explaining the importance of work in nanotechnology to the University’s engineering and science education programs, Ryan Vallance, GW professor of mechanical engineering and lead professor in the establishment of the institute, said, “Nanoscale phenomena are frequently incompatible with our classical intuition and experiences. Traditional engineering theories, like continuum mechanics, which engineers have used for over a century to design new devices, break down in nanotechnology. We have to now teach students additional physical, chemical, biological, and statistical principles that govern nanotechnology. The institute will help us incorporate nanotechnology into our educational programs, both at the undergraduate and graduate levels.”

November 24, 2008: Carl Zeiss SMT says it has set a new record resolution benchmark for scanning electron and ion microscopy. By employing Zeiss’ Orion Helium-ion microscope, a surface resolution of 2.4Å (0.24nm) has repeatedly been achieved (25%-75% edge-rise criterion) on various samples, 3× better than the most sophisticated scanning electron microscopes are able to achieve today with the same surface sensitivity.

“This unmatched resolution for surface imaging with scanning electron and ion microscopes is extremely important for semiconductor manufacturers and many others who need to see small features that currently cannot be resolved,” said Nicholas P. Economou, SVP of Carl Zeiss SMT, in a statement.

The ongoing shrinkage of feature sizes of semiconductor devices — some IC layers have reached thickness of only a few atoms — makes extreme high-resolution microscopy mandatory, explained Rainer Knippelmeyer, SVP of operations, in a statement. “Semiconductor manufacturers are in dire need of reliable high-resolution, surface sensitive metrology and process control tools,” he said. “With the Orion Helium ion microscope we offer exactly the tool the industry and nanotechnology research needs and we continue to keep pace with the industry’s rapidly changing requirements.”


Image resolution of 0.24nm a linescan over the very sharp edge of an asbestos fiber on a thin holey carbon foil. The texture of the holey carbon foil demonstrates the extremely high surface sensitivity of the Orion, which equals or even exceeds the surface sensitivity of an SEM operated at 1kV and below. (Source: Carl Zeiss SMT)

The secret behind the extreme high resolution of the helium-ion microscope lies in the proprietary source technology and in the interaction between the scanning ion beam and the surface of the specimen. The source of the microscope is very small and the helium ions emanate from a region as small as a single atom. Unlike electrons, the helium ions have a very small wavelength and hence do not suffer appreciably from adverse diffraction effects — a law of physics which fundamentally limits the imaging resolution of electrons. Also, the helium ion beam triggers signals directly from the surface of the sample and stays very collimated upon entering the sample. This results in very sharp and surface sensitive images at the quoted resolution which can be easily interpreted.