Category Archives: Metrology

September 6, 2007 — Oerlikon Solar has introduced its micromorph tandem technology, which promises conversion efficiencies of 10% and higher in the near future. And, the company has strengthened its commitment to solar development by creating the position of CEO.

The micromorph tandem technology combines two different silicon materials: An amorphous top cell converts the visible part of the sun’s spectrum while a microcrystalline bottom cell absorbs the near infrared portion of the spectrum. The combination boosts the efficiency level by approximately 50% compared to traditional amorphous single cells, the company contends. In addition, “All materials we utilize in our thin-film technology are non-toxic, low cost and readily available. The embodied energy used to produce our micromorph tandem modules is merely half versus crystalline cells,” says Oerlikon CEO Dr. Uwe Krueger.

Inventux Technologies AG, a Germany-based photovoltaic (PV) company, has signed a contract with Oerlikon Solar for a 30 MWp production line to manufacture micromorph tandem modules. Inventux’ production plant will be located in Berlin. The project also includes plans to rapidly expand the facility to 100 MWp capacity.

In addition, Oerlikon has named technology industry veteran Jeannine Sargent to the newly created position of CEO for Oerlikon Solar. The move puts all of Oerlikon’s solar-related business under one umbrella and strengthens its commitment to solar development. Sargent has 20 years experience working with public and private high-tech companies, and most recently served as executive vice president and general manager of Veeco Instruments’ Metrology and Instrumentation business.

Flip Chip Metrology
Veeco


September 4, 2007

The Wyko SP9900 surface-profiling optical metrology tool monitors height, yield, roughness, and other parameters of multilayer organic panels for pin grid array (FC-PGA) and ball grid array (FC-BGA) flip chip packaging. It offers faster measurement, increased sample access, and up to 600 &#215 600 mm panel measurement within the SP equipment footprint.

Performing quality assurance (QA), characterization, and small-lot production, the V5000ep builds on the V5000e platform with increased automation, testing and characterizing all memory types from wafer sort through final test. When testing multi-chip packages (MCPs), the system uses proprietary Matrix technology to automatically shift resources from one die to another without manual reinsertion of the device under test (DUT).

August 28, 2007 — Veeco Instruments Inc. has introduced a line of new production-scale PV-Series Thermal Deposition Sources, enabling copper indium gallium selenide (CIGS) thin film solar manufacturers to more quickly transition from pilot to full-scale solar-cell production. Veeco’s new line of thermal deposition sources for CIGS includes PV-Series SUMO (for copper, indium and gallium) and PV-Series Valved (for selenium and sulfur) for R & D and production environments.

The company’s new offerings “represent the industry’s first commercially available production-scale thermal deposition solution for thin film solar manufacturing,” said Jeffrey Hohn, Vice President and General Manager, Veeco MBE Operations. “We believe that our PV-Series sources will accelerate our customers’ production ramp, reduce capital costs and provide more reliable operation, compared to currently available sources or solar cell manufacturers’ in-house custom designs.”

In addition to the new thermal deposition sources, Veeco’s suite of solar technology solutions includes Metal Organic Chemical Vapor Deposition (MOCVD) systems for multi-junction solar cells and a complete suite of thin film and surface roughness metrology systems, including atomic force microscopes, stylus profilers and optical interferometer technology.

August 27, 2007 – Nanometrics says it has completed the sale of facilities in Narita, Japan, related to the flat-panel display business that it sold in 2005 and “had sat unutilized” ever since. Also sold was a residential condo near the company’s headquarters in Milpitas, CA. Together the sales will add about $2 million in cash and both reduce debt and add income of approximately $1.2 million in 3Q07.

Tim Stultz, the newly appointed president/CEO of Nanometrics, pointed out the asset sales represent another example of the company monetizing fixed assets and getting rid of noncritical businesses, citing the recent sale of its machining and plating shop.

In the past year the company has also sold off its Yosemite CD-SEM and DiVA product lines, consolidated its overlay metrology production in Korea, and seen former CEO John Heaton and CFO Dave McCutcheon leave the company.

by Debra Vogler, Senior Technical Editor, Solid State Technology

Buildup of chemical residues inside an ion implanter limits the tool’s overall utilization efficiency. James Dunn, Atmel Corp.’s equipment engineering section manager, described for WaferNEWS the results of the company’s evaluation of a new in situ chemical cleaning technology from ATMI that reduces such deposits and achieves greater predictability for source change-outs.

Deposit build-up is one cause of ion beam instability, which in turn adversely affects process integrity. Two major problems arise from ion beam instability. One problem is momentary drop-out in the beam current on the wafer being processed because of high-voltage arcing, which leads to undesired species being implanted into the process wafer for a certain period of time, according to Dunn. Such high-voltage glitches result in the nonuniformity of implants and particle contamination. Another kind of beam instability causes drifting of the beam current, which leads to dose errors. These process integrity problems lead to unpredictable change-out of the ion source.

While source lifetimes vary according to implanter type (i.e., medium-current vs. high-current) as well as application, according to Dunn, a typical medium current implanter application at Atmel might see a variation in source life between 200-500 hrs, when the actual filament life should be 500hrs.

During Atmel’s evaluation of ATMI’s AutoClean process — an in situ process that introduces a cleaning agent at regular intervals into the ion implanter — Dunn told WaferNEWS that 100% of the sources subject to the purge process have gone to the end of filament life (500hrs) — and even higher in some cases (see figure). During the evaluation, process qualifications and particle checks were done and the results indicated no harm was done to the wafers using the new cleaning technology.

According to Dunn, the fab’s population of medium current implanters has averaged 292 hours of source life, which translates to 27 source changes per tool per year. The two sources running AutoClean have averaged double that lifetime (588 hrs) with the third source still running stable with 501.28 hours, he said, and the company expects its annual source changes to drop to 13-14 per tool per year, “thereby reducing our costs for cleaning and consumable parts by 50%.” Dunn noted that the source changes average 5hrs to complete, involving the actual source change and also tool re-qualification, so fewer source changes with the new tools “translates to 65 hours of additional production time per tool per year, and a reduction of one-half the process qualifications, which frees up additional processing and metrology equipment in the fab.”

An additional benefit of using the new technology cited by ATMI is the ability to do species rotation, for example, being able to run a phosphorus process immediately after a boron process or vice versa. Having the ability to be flexible is becoming more important as fabs need to have shorter reaction times to respond to customer demand. — D.V.

IMAGE: Effect of in situ cleaning on ion source life. (Source: Atmel Corp.)

August 16, 2007 – Following months of trimmings and reorganizations, Nanometrics Inc. is further shrinking its corporate footprint with the closure of its machine shop and plating facility in Milpitas, CA. The move will result in a ~$4 million charge to write off assets; the company says it is trying to lease the facility and sell related assets.

“A key element of our restructuring plan is to unwind our vertical integration strategy, converting fixed costs to variable costs,” said Bruce Rhine, current CEO of Nanometrics, in a statement, noting that the machining and plating business adds no value, and disposing of it and the facility will improve the company’s cost structure and lower its breakeven profitability point.

Rhine is slated to move up to the chairman’s seat later this month to make room for new incoming president/CEO Timothy Stultz (formerly top exec at Imago Scientific Instruments). At the time of that announcement a few weeks ago, execs hinted that the company’s recent activities apparently haven’t gone as smoothly as hoped. Nanometrics founder Vincent Coates noted Rhine’s guidance “through some of the most challenging tasks we have faced as a company,” most notably “turning around a troubled business integration,” and Rhine himself remarked on “a number of challenges in integrating and consolidating its operations worldwide.”

It’s been a tumultuous year for Nanometrics, with a number of executive shuffles, selling off certain product assets, and moving other product lines overseas. Since last summer’s acquisition of metrology firms Soluris Inc. and Accent Optical Technologies (AOI), the firm has watched former CEO John Heaton leave the company with little explanation, followed a month later by CFO Dave McCutcheon “to pursue other interests”. More recently Nanometrics has announced it will consolidate all its overlay metrology production in Korea (and close the Soluris site in Concord, MA), where it already makes its Orion and Caliper systems. And weeks ago Nanometrics sold off the Yosemite CD-SEM technology originally developed by Soluris and AOI’s DiVA series of IV instruments primarily for use in the RF microwave industry, both for undisclosed amounts.

By Allen Park, KLA-Tencor Corp., Milpitas, CA, United States

EXECUTIVE OVERVIEW A powerful new method can identify systematic defects within a large defect sample, prior to SEM review. By integrating design data with defect data, this method enables accurate binning of randomly distributed structural systematic defects. Instead of relying on inefficient random review sampling to identify defects of interest (DOI), this technique applies a pattern search engine accessing the design files to correlate the DOI to pattern backgrounds, independent of their spatial distribution. Based on this approach we have identified numerous systematic defects including a residue defect. This novel binning technique allows users to quantify systematic defect types quickly and efficiently from wafer maps that consist of random and systematic defects, allowing for prompt corrective action.

Defect inspections performed during process development often result in 105 to 106 defect counts on a single wafer. Such defect data include both systematic and random defects, only some of which may be yield-limiting. The traditional method of reviewing a random sample of only 50–100 defects on the SEM makes it difficult to identify important systematic defects from a defect wafer map.

Systematic defects, generally pattern failures due to process or design marginality or parametric failures due to electrical issues, are growing in importance as a factor in overall yield loss [1]. Pattern-related systematic defects include line-end thinning, necking, CD variations, side profile variation, overlay error, broken lines, and edge residues (Fig. 1).


Figure 1. Sample pattern-related systematic defects. (Images courtesy of UMC)

Such systematic issues can be challenging to identify using in-line defect inspection systems, due to a high volume of other defect types, and noise-related nuisance sources. Since all systematic defects must be identified during process development, inspection recipes are often deliberately set with high sensitivity, even at the cost of potentially including large numbers of nuisance defects. The defect count can be upwards of hundreds of thousands per wafer, especially in the process development environment.

After inspection, defects must be reviewed to identify their type. A typical repeater analysis based on die-to-die comparison may not be sufficient to detect defects such as line-end thinning or broken lines, because the failure sites are not consistent among various die. Such randomly distributed structural systematic failures are compounded when combined with high defect count. Because of the time and effort required, defect review sampling is often limited to 50 to 100 defects per wafer. With 100,000 defects, a review sample of 100 represents only 0.1 % of the total population, enormously diminishing the probability of identifying critical systematic defects during defect review.

To reduce the difficulty of identifying randomly distributed structural systematic failures, a new design-based inspection technique from KLA-Tencor was evaluated. This advanced technique has been used for almost two years, generating valuable results for both 65 and 45nm development. The integration of design data with defect data enabled us to bin defects using the design background as a proxy for SEM review.

Systematic defect: STI residue
Within the shallow trench isolation (STI) process, a residue defect was discovered using random SEM review after inline defect inspection, however quantity and spatial distribution were unknown due to sampling limitation (Fig. 2). The inspection result was first analyzed using a traditional sampling approach. Even with the relatively low total defect counts on the wafer, the review sample of 50 defects/wafer, selected either at random or using defect size information, represented less than 10% of the total population. It was thus very difficult to quantify the occurrence of the residue defect and to identify its spatial signature, and the largest bin in the defect Pareto was the ‘unclassified’ bin. Only a small number of defects were identified as the residue defects in the traditional defect Pareto.


Figure 2. SEM images of the residue defect. (Image courtesy of UMC.)

To understand how the new technique might better quantify the residue defect population, the same data set was analyzed using both defect and design information. Each defect location was associated with, and then grouped by, the background patterns defined in the design. After grouping, a smart sample of defects was chosen for review. With this approach a significantly different Pareto was generated, and not only 50 defects, but all defects in the inspection result were classified. Such a technique provided a unique advantage in selecting the right set of defects for review, optimizing the return on the defect review effort, and quantifying an unknown failure mode that may otherwise have been overlooked.

Figure 3 compares the resulting Paretos using the traditional and new approaches. In the traditional approach, only 5% of the total defects were identified as residue defects, while the majority of defects remained unclassified. By applying the new technique, all defects were classified, and residue defects were identified at >13× the number identified using the traditional approach. With a significantly higher number of defects now identified as the defect type of interest, their spatial signature can be clearly understood (see bottom image in Fig. 3 below).



Figure 3. (top left) Pareto using traditional defect review; (top right) Pareto using new design-based technique; and (bottom) spatial signature of the residue defect (highlighted).

We found that the residue defects were structurally systematic, but spatially random within some of the die. While the defects seemed to occur in a certain pattern within the die, the failures did not occur at the same locations, according to a die-to-die comparison. By applying design data, we were able to identify that certain parts of the design are prone to this type of failure. Figure 4 illustrates the high probability locations of failure sites for the residue defect type.


Figure 4. Illustration of defect using design data. (Image courtesy of UMC)

Conclusion
Using design information associated with the defect locations provides significant advantage in identifying systematic defects. The new technique relies on an inspection tool with sufficient sensitivity and location accuracy. Using the new design-based inspection technique, unknown systematic defects can be identified and quantified quickly, leading to rapid root cause discovery and correction. While the traditional approach typically samples small portion of overall population, using the new approach allows user to sample 100% of defects by using design as proxy to SEM review.

This kind of structurally systematic, but spatially random defect typically occurs within a fraction of the die; because it does not occur at the same locations, a die-to-die comparison is not suitable in identifying the problem. Using the design data as an integral part of the inspection, we significantly increased our ability to identify those parts of the design most prone to this type of failure. ♦

Acknowledgments
The authors would like to thank J.H. Yeh, Hermes Liu of UMC’s CRD YE team, and Dr. Tzou for providing courtesy sample images.

Reference
1. K. Monahan, B. Trafas, “Design and Process-limited Yield at the 65nm Node and Beyond,” SPIE, 2005.

Allen Park received his BS degree in physics from U. of Irvine, California, in 1988 and is now a marketing manager at KLA-Tencor Corp., where he has worked for more than 12 years. Prior to K-T, he worked in process development and yield enhancement at National Semiconductor and Silicon Systems. KLA-Tencor Corp., 1 Technology Drive, Milpitas CA 95035, United States; ph 408/875-5195, e-mail [email protected].

The P-733.3CD stage with an E-761 PCI bus piezo controller.

August 10, 2007 — PI (Physik Instrumente) L.P. has launched a new 3-axis nanopositioning / scanning stage, the P-733.3CD. The high-resolution stage is designed for nanomanipulation, high-resolution microscopy, imaging applications, and materials research. The unit’s parallel-kinematics design, which involves just one platform for moving in X,Y, and Z axes, reduces the moved mass, and complements the unit’s stability to enable “higher operating speeds than other piezo scanning stages,” according to PI.

The stage features:
+ A travel range of 100 x 100 µm in X/Y and 10 µm in Z
+ Direct metrology with capacitive sensors for up to 0.1 nanometers resolution
+ Parallel kinematics for better multi-axis accuracy and dynamics
+ 50 x 50 mm clear aperture for transmitted-light applications

Typical applications include metrology / interferometry, biotechnology, semiconductor testing, mask and wafer positioning, image enhancement, and stabilization

The stage promises speed, accuracy, and sub-nanometer precision. Its large, clear aperture is an advantage in transmitted-light applications. The high-speed Z-axis (sub-millisecond response time) can actively compensate out-of-plane, Z-axis deviation during XY scans.

Capacitive nano-measuring sensors read the platform position directly and without physical contact. This promises freedom from friction and hysteresis, and very high levels of linearity, up to 99.99% with resolution to 0.1 nanometers. The Parallel Metrology configuration measures all axes against the same fixed reference, providing better precision than serial (individual) metrology.

August 8, 2007 – Nearly a year after putting some of its lithography metrology patents up for auction, Nova Measuring Instruments says it has signed a >$1 million deal with an unnamed “top-10 semiconductor manufacturer” for a license covering use of its technologies for integrated metrology and integrated process control before and during the photolithography manufacturing step.

The deal, which the company says follows response from several semiconductor manufacturing companies interested in the patents, “is clear evidence of the strength of the IP and its importance to semiconductor manufacturing,” said Gabi Seligsohn, president/CEO of Nova, in a statement, adding that the company will “continue discussions with additional companies interested in licensing or purchasing these patents.”

In an e-mail exchange, Seligsohn clarified to WaferNEWS that Nova is still “in active discussions” regarding both licensing and outright sale of the patents, but that this first license was crafted to be “in perpetuity” to guard against possible strategic maneuverings, “such that the possible new proprietor will have no ability to enforce the patents against a licensee.”

In Sept. 2006 the company started soliciting bids from approximately 100 companies to license six of its patents relating to use of a lithography tool with integrated metrology, including bids for outright ownership of the technology. Four of the patents relate to a lithography track with integrated optical measurement capability, used with overlay registration, critical dimensions, and macrodefect inspection. Two others, from the company’s advanced process control group, are for methods for photolithographic processing involving making a spectrophotometric measurement and using it to influence the processing time, focus or exposure of a processing tool.

August 7, 2007 — Nanometrics Inc., supplier of advanced metrology equipment to the semiconductor industry, says that Timothy J. Stultz, Ph.D. will join the company as its president and chief executive officer (CEO), succeeding Bruce C. Rhine, who will become chairman of the Board of Directors. Founder Vincent J. Coates will become vice chairman of the Board. Dr. Stultz will also be appointed to the company’s Board, effective as of his start date, which is expected to be late August 2007.

Dr. Stultz, 59, comes to Nanometrics from Imago Scientific Instruments, where he has served as president, CEO and a director since June 2003. From 1994 to 1999, Dr. Stultz served as a vice president and general manager with Veeco Instruments, during which time he led the growth of Veeco’s metrology business. Dr. Stultz also was the founder and CEO of Peak Systems, Inc., a pioneer in the rapid thermal processing segment of the semiconductor capital equipment industry.