Category Archives: Metrology

July 9, 2007 – Ofer Du-Nour, founder of Israeli metrology firm Tevet Process Control Technologies Ltd., has been named as CEO of the company, following the sudden resignation of Yuval Wasserman “to pursue other interests.” Peter Gillespie, VP of marketing and sales, also has been promoted to president of the firm.

The company explains that the changes are linked to its release of additional product lines. “Ofer Du-Nour and Peter Gillespie have been key drivers in Tevet’s Trajectory T3 film thickness integrated metrology product line,” said Ron Hiram, managing partner at Eurofund, a leading investor in Tevet, in a statement, noting that with the new leadership comes expectations that the T3 line will “continue to make gains and further anchor Tevet’s presence in the market.” “We also believe that now is the right time to broaden Tevet’s product line and the BOD is fully supportive of Tevet’s move into new product line development,” he added.

Before founding Tevet, Du-Nour, a 20-year industry vet, was SVP and director of the microelectronics division of Israeli firm Industrial Development Corp. Prior to that, he was projects department manager at Israeli foundry Tower Semiconductor.

Prior to joining Tevet in 2005, Gillespie (a 15-year industry vet) held VP and director-level positions at KLA-Tencor Corp., Boxer Cross Inc. (acquired by Applied Materials Inc.), and Axcelis Technologies Inc., and held marketing/engineering management positions at Inchcape Testing Service (now Intertek ETL SEMKO) and Nippon Sanso, parent firm to Matheson Semi-Gas Systems.

June 29, 2007 – KLA-Tencor Corp. apparently has quietly acquired FabSolve LLC, a US firm with “design-based metrology” software, based on its Vietnam parent group’s digital mapping/GIS technology, that can be used for in-line metrology in semiconductor manufacturing. Terms of the deal have not been disclosed.

FabSolve’s technology is based on work from DolSoft Inc., a Vietnam-based developer of geographical information systems (GIS)/digital mapping technology, which had already has found other applications for its GIS algorithms, e.g., security & video surveillance, noted Steve Cintron, VP of marketing for FabSolve, in a phone conversation with WaferNEWS.

In 2005, two new hires with backgrounds at fabs in the 1990s (e.g. Texas Instruments) and Knights Technology joined the company, he said, and realized what the GIS technology could do for semiconductor manufacturing: capturing SEM data in real-time and overlaying it with the design to locate and classify deviations/defects, databasing the data, and figuring out what process parameters to change to improve yield.

Cintron indicated that FabSolve had progressed its technology to the point of customer demos, and was on the brink of signoff with two top-10 global semiconductor firms (one top-5) for both a purchase order and a joint development agreement. But at a recent industry event, KLA-Tencor approached them interested in the technology for in-line metrology, laying the groundwork for this acquisition, he said.

June 21, 2007 – A new study by Wright Williams & Kelly Inc. and Strategic Marketing Associates sheds light on what people in the industry think will be most likely to hit production process lines in the next 2-5 years, and which ones may take longer than expected to be adopted into manufacturing lines, if ever.

Manufacturing technologies included in the survey are most lithography and gate technologies currently in development — new methods of cleaning, deposition, and test/metrology; and several cost reduction or productivity enhancing manufacturing technologies, including 450mm, energy saving methods, remote diagnostics, and manufacturing simulation, according to Daren Dance, WWK’s VP of technology, who shared some insight into the survey results in an e-mail Q&A with WaferNEWS.

Getting the nod by ≥50% of respondents to be seen in production manufacturing by 2008-2010 are high-k dielectrics and metal gates; adaptive test; and equipment with energy saving “sleep” states, according to the survey. Meanwhile, ALD is viewed as ready now for production by 50% of respondents, and half of respondents think both FUSI and integrated in-situ metrology will be ready within the next year or so.

Another ≥50% of respondents think a group of technologies, including damascene gate formation, 193nm high-index immersion lithography, and wafer-level reliability testing, should be ready for production sometime between 2010-2012.

Dance pointed out that it’s no surprise that respondents are cautious about lithography forecasts, since “new litho technologies have a way of falling by the wayside, leaving optical as the industry workhorse.” He added that although similar caution exists regarding gate technologies, multiple advanced gate approaches are likely to be used, as each has different benefits for certain architectures and applications.

One of the more interesting results from the survey was respondents’ opinions on a change to 450mm wafers, one of the more polarizing debates currently happening in our industry. Right now, sentiments seem to be of three types:

– “Yes it’ll happen” — pushed heavily by the biggest chipmakers like Intel, or TSMC seeking economies-of-scale (and with them probably heavily funding much of the development costs);
– “Yes, but way later than the ITRS‘ 2010 deadline” — noting how long it took 300mm to gain traction, and how long it’ll likely take everyone involved to come to a consensus the next time;
– “No, it’ll probably never happen” — citing tool suppliers’ aversion to bear any brunt of the massive development costs foreseen in a new wafer-size change implementation.

In this WWK survey, respondents’ sentiments fall squarely in the latter camps. The most frequent response to 450mm wafers was that they won’t see the light of day in production manufacturing until 2013 or later — but 39% of respondents think 450mm won’t ever happen at all. Respondents also doubt the viability of EUV lithography and imprint lithography as finding inroads into production until 2013 or beyond.

Dance noted that the survey tried to avoid bias by asking for a “date when expected,” with the option to choose “Never” added at the last minute. That option was ultimately checked at least once by ~40% of the questions, though he pointed out that some of them referred to technologies that are actually seen in current production. J.M.

June 19, 2007 – Klaus Schruefer, chief scientist for Infineon’s multigate FET technology project, tells WaferNEWS why mugFETs are being pushed out beyond 32nm, and what’s highest on the to-do list to get the technology ready for chip manufacturing, even by the 22nm node.

Infineon extends multigate-FET work

In an interview with WaferNEWS, Klaus Schruefer, chief scientist for Infineon’s multigate FET technology project, confirmed that the latest info from the company seems to push mugFETs out beyond the 32nm node, whereas in discussions back in December around IEDM there was talk that only 45nm would be too early. “What has changed in the meantime is progress on high-k and metal gates,” he said. “Of course, each and every company wants to stay planar as long as they can, if it’s possible.”

Asked what are the challenges Infineon faces to get the promising mugFET technology ready for production, he indicated there are a range of issues from a manufacturing, equipment, and design standpoint — though yields and reliability of the manufacturing process are not a concern.

One of the hurdles to multigate FETs has been integration with design. FinFETs are totally different structures, requiring new computer models built with data from actual results on silicon, which implies months or years of running processes. Schruefer acknowledged that compact modeling remains “an open question” and probably won’t be ready until mid- or late-2008. However, he added that he saw “really good progress” on compact modeling at this year’s VLSI Symposium, in papers presented by the U. of California-Berkeley on its “BSIM” model (Berkeley short-channel insulated-gate FET), and NXP’s work on its “PSP” model is “following very fast,” he noted.

A bigger concern is getting metrology technology to catch up with these new chip architectures. To have multigate finFETS ready for 32nm or even 22nm chip manufacturing, that means the metrology needs to be ready 18-24 months from now, Schruefer explained. And right now, for example, there’s no “mature” technology to measure plasma doping concentration on the sidewalls of a 3D device. Consortia including IMEC and SEMATECH are working on these metrology issues (e.g., atomic-force microscopy for vertical measurement of doping densities, and other things like line-edge roughness SEMs for fins), but Schruefer admitted that progress is “too slow.” “Metrology has to be ready when you start to really develop the technology,” he said. “We hope that things will be ready when we need it.” — J.M.

MEMS Metrology System


June 18, 2007

The DSM200 automated metrology system performs cassette-to-cassette front-to-back alignment for front- to back-side alignment applications, such as MEMS, power semiconductor, and optoelectronics assembly.

June 8, 2007 – Yet another move in a busy spring has left Nanometrics Inc. feeling better about its positioning in the market with a core group of metrology technologies, after the recent sale of two tangential product lines, the company says.

The first transaction involves the Yosemite CD-SEM technology originally developed by Soluris Inc. and acquired by Nanometrics in March 2006, which has now been sold to Korean chip equipment firm SNU Precision Co. Ltd. for an undisclosed amount. Under Soluris’ stewardship, income generated from the company’s flagship IVS 155 overlay tool had been plowed back into R&D for the Yosemite CD-SEM in two joint development projects with customers, but the technology faced a likely long uphill battle vs. entrenched and far larger competitors, and Nanometrics deemed it was unworthy of further investment.

Ironically, Korea is also where Nanometrics recently said it will consolidate all its overlay metrology production, a move that will result in the closure of Soluris’ Concord, MA facility. The company already makes its Orion and Caliper systems in Korea.

The other product line divestiture is the DiVA series of moderate power, low-cost IV instruments primarily for use in the RF microwave industry, which was part of Nanometrics’ acquisition of Accent Optical Technologies Inc. a year ago. The line, which represented <$1 million in annual sales, was sold on May 31 to Lowell, MA-based Auriga Measurement Systems LLC for an undisclosed amount, according to the company.

“The DiVA is a well-established product that has no synergy with our metrology business, and the Yosemite includes some excellent technology but serves a market outside of our product focus,” explained Bruce Rhine, CEO of Nanometrics, in a statement. He added that these moves better position Nanometrics to pursue its growth strategy for overlay, optical CD, thin-film and integrated metrology markets.

These product line divestitures cap off a spring of corporate changes as well for Nanometrics. In March, CEO John Heaton mysteriously left the company (no details were provided about his departure), with then-chief strategy officer Rhine, former chairman/CEO of Accent Optical, taking the reins on what was described as an interim basis. One month later, CFO Dave McCutcheon followed him out the door “to pursue other opportunities,” replaced by chief accounting officer Quentin Wright.

June 5, 2007 – The market segment for semiconductor metrology and inspection tools will recover “modestly” this year after “a dismal 2006” in which the segment grew just half the rate of the rest of the frontend equipment market, according to a report from The Information Network.

Last year the metrology/inspection tool segment posted growth of 16.4% — well off the 33.6% clip for the overall frontend equipment market, and glaringly apart from the average 2.4% spread. Yields reached levels to the point that chipmakers could relax wafer sampling, and find ways to minimize capital expenditures, noted Robert Castellano, president of the market research firm.

Immersion lithography is now a principle driver for the metrology/inspection market, he noted, as process engineers consider the need for more sampling going ahead. Other factors helping the segment include continued usage of 300mm wafer processing, and introduction of new exotic processes and materials.

The firm projects the metrology/inspection to actually outperform the frontend equipment market in 2007, growing +3% vs. a -4% decline in frontend. Next year the firm pegs metrology/inspection growth at 16.5%, slightly ahead of the frontend segment (14.2%). Continued erosion in the semiconductor market will impact capex, Castellano told WaferNEWS, adding that Intel and STmicroelectronics combining NOR flash businesses to essentially bail out of the NOR flash market is a negative for equipment purchases in that sector.

By Tom Cheyney, Small Times Senior Contributing Editor

May 31, 2007 — A particularly compelling discussion among panelists from industry and academia at the NSTI Nanotech 2007 conference (May 21 – 24 in Santa Clara, Calif.) examined technical barriers to — and recent advancements in — nanomanufacturing. The frank exchange centered on successful integration of nanoelements with micro/nano structures and devices, and challenges to scaling up nanotech products to commercial volumes.

Several panelists emphasized the importance of drawing on the know-how of other industries, especially the semiconductor-manufacturing sector, to accelerate nanoproducts’ progress into production and the marketplace. Pointing to the chipmaking industry as “a good model to use,” MEMS industry consultant Roger Grace declared, “We need to learn from past experiences, we have to build on what we know.”
The creation and implementation of industry standards, support of R&D efforts, roadmapping, and establishment of a dedicated equipment, metrology, and packaging supplier infrastructure were among the lessons that nanomanufacturers could learn from the semiconductor community, according to Grace.

“The semiconductor model is the only one that will work for nanotechnology, with the exception of self-assembly,” said Brent Segal, COO/cofounder of Nantero. “Nanotechnology is mostly physical chemistry,” adding later that “the enemy of semiconductors is dirt. Even with the diversity of nanotechnologies, contamination control and reliability remain issues.” He mentioned that Nantero has successfully integrated its carbon nanotube-enabled NRAM devices into CMOS process flows in the Gresham, OR, chip fab operated by its partner (originally LSI Logic, now ON Semiconductor), without adding any new tools to the production line.

“How do you organize nanowires on a substrate?” asked Loucas Tsakalakos, staff scientist with GE Global Research. He reiterated the importance of understanding the controlled synthesis of “ordered nanostructures” and other fundamentals, citing materials incompatibility, alignment and positioning (vertically and horizontally), arbitrary patterns, and other technical challenges to “heterogeneous, multiscale materials and device” integration and manufacturability.

Several panelists identified metrology equipment as a “key bottleneck for advancing nanotechnology,” offering their views of specific tools and methods that have room for improvement.

Tsakalakos said that contact resistance needs to more accurately and repeatably measure nanowires, in order to determine their actual properties. Nantero’s Segal noted the challenge of measuring grain boundaries and other small structures of importance in “molecular-scale engineering.” Ahmed Busnaina, panel moderator and director of the NSF Center for High-Rate Nanomanufacturing (CHN) at Northeastern University, would welcome techniques and tools for in situ, fast measurement of defects and other anomalies over large areas, but “doesn’t see a good solution on the horizon.”

Busnaina and fellow professor Harry Stephanou of the University of Texas (Arlington) pointed out the great variety of applications and materials — and their relative immaturity — in the nano realm as well as the fragmentation of the micro/nano markets.

Stephanou urged “universities to do more than just research,” chiding higher-education institutions for the “lack of evolution in PhD programs” in the area of entrepreneurial skills. He also cited the “difficulties of having standard tools” and with the tools themselves, which makes it “less clear to know how to set up a [nano] fab,” as well as the complexities of “establishing a packaging infrastructure” because of the inherent diversity of nanotechnologies and materials.

Busnaina agreed that there is common ground between semiconductors and emerging nanoelectronics devices, but said the nanomaterials side has some key differences with the chip world, noting that specific applications have a great impact on how to develop and determine processes.

He said CHN tries to “bridge the gap between scientific research and the creation of commercial products” with the implementation of “processes and tools that will enable high-rate, high-volume, bottom-up precision manufacturing.” Part of the center’s nanoprocess standardization efforts focuses on the creation and development of what Busnaina calls “nanotemplates,” which will facilitate “guided self-assembly of nanoelements,” such as single-walled carbon nanotubes and polymers.

by Bob Haavind, Editorial Director, Solid State Technology

A ConFab session on “Capital Equipment: Alternative Financing Models” was kicked off by Craig Ignaszewski, director of capital equipment procurement, IBM, with discussion of the rationale for leasing vs. buying equipment.

Increasing complexity in chipmaking creates greater risk of technological change and obsolescence, which can be mitigated by leasing, he explained. In some cases, equipment is not strategic, but may be useful for a short-term bubble in the market, or a new area with an uncertain future. Leasing makes sense here as well.

Once favorable operating lease treatment is negotiated, there are other benefits to the corporation, according to Ignaszewski: It accelerates the timing of free cash flow, allows alternate sources of funding, and may optimize the tax position.

Leasing also preserves operating and financial flexibility, he added. An agreement should include an early buyout option, as well as a purchase option at the end of the lease. This might include “item-by-item” selection for accessories, add-ons, or parts of a total system. There should also be a substitution capability, he suggested.

IBM also has other alternatives to leasing or buying equipment, he said. Sometimes the company works in joint development programs or does beta evaluations of new tools. Collaboration sometimes involves sharing of development expenses. The company also uses sale-leaseback arrangements, primarily for IBM-owned manufacturing equipment.

Other leasing options were discussed by Zvi Lando, VP at Applied Materials’ Israel operation.

“Metrology and inspection equipment may be the most suitable for leasing,” Lando suggested.

Metrology equipment is usually designed to operate through at least two nodes. But upgrades often can improve the equipment performance, and may be capable of carrying it through a third node. Leasing arrangements can be structured, he explained, to incorporate future upgrades. — B.H.

May 23, 2007 — Hyphenated Systems , provider of hybrid microscopy solutions for three-dimensional (3D) imaging and metrology in micro- and nanotechnology, has announced the development of a combined advanced confocal/atomic force microscope (ACM/AFM) on one platform. The system is being developed jointly with atomic force microscope (AFM) provider KARMA Technology, Inc., and is geared for three-dimensional (3D) metrology applications in semiconductor manufacturing and laboratory environments.

Geared for the semiconductor industry, the system will be built to accommodate wafers up to 12-inches in diameter. It will also feature a patented probe module that is easily replaceable — eliminating the need for time-intensive probe tip changes of the AFM.
“This hybrid confocal-AFM tool is expected to be the first real, fab-friendly AFM. We are building every possible feature into it to accommodate the needs of the manufacturing environment. The probe module eliminates tool downtime due to tip changes of the AFM; a special vibration isolation platform will enable the AFM to operate with high accuracy in a manufacturing environment; and the system will combine high-speed confocal imaging of larger features with detailed atomic-resolution imaging of targeted features — without having to move the sample from one tool to another,” said Terence Lundy, company vice president and managing director.

Hyphenated Systems specializes in advanced confocal microscopes that enable 3D measurements of material structures and fluid flow with sub-micrometer resolution. The company says its patented confocal microscope technology is unique in its ability to provide extremely fast, accurate, structural characterization of materials, including steep slopes, rough surfaces, and subsurface features in transparent media, many of which are difficult or impossible to measure with alternative techniques. The combined ACM/AFM tool promises the speed and 3D imaging advantages of ACM, combined with atomic-level resolution measurement capabilities of an AFM — all on one single platform, preventing the need to move the sample.