Category Archives: Metrology

Nanometrics Incorporated, a provider of advanced process control metrology and inspection systems, today announced that SK Hynix has reported significant process control improvement by deploying the Atlas II platform for optical critical dimension (OCD) metrology across its memory device production.

"Nanometrics, with its Atlas II platform, has enabled key yield and performance learning on our DRAM devices," said a representative of SK Hynix. "Nanometrics continues to be a valuable technology supplier to SK Hynix and the Atlas II platform plays an important role in the production ramp of our next-generation products."

"We have a close collaboration with SK Hynix, and have provided the company metrology solutions across multiple technology generations of memory devices since first introducing our industry-leading NanoDiffract OCD analysis software," commented S. Mark Borowicz, senior vice president of silicon solutions at Nanometrics. "Our Atlas II system, with its advanced technology for in-line process control, has enabled this important customer to quickly identify and address manufacturing steps that impact device performance, and tune key processes to maintain process stability."

The Atlas II is a high-performance process control system capable of advanced thin film and OCD metrology, leveraging the industry-leading performance of Nanometrics’ NanoDiffract software for complex structure metrology.

Semiconductor revenue worldwide will see improved growth this year of 6.9 percent and reaching $320 billion according to the mid-year 2013 update of the Semiconductor Applications Forecaster (SAF) from International Data Corporation (IDC). The SAF also forecasts that semiconductor revenues will grow 2.9 percent year over year in 2014 to $329 billion and log a compound annual growth rate (CAGR) of 4.2 percent from 2012-2017, reaching $366 billion in 2017.

Continued global macroeconomic uncertainty from a slowdown in China, Eurozone debt crisis and recession, Japan recession, and the U.S. sequester’s impact on corporate IT spending are factors that could affect global semiconductor demand this year. Mobile phones and tablets will drive a significant portion of the growth in the semiconductor market this year. The industry continued to see weakness in PC demand, but strong memory growth and higher average selling prices (ASPs) in DRAM and NAND will have a positive impact on the semiconductor market. For the first half of 2013, IDC believes semiconductor inventories decreased and have come into balance with demand, with growth to resume in the second half of the year.

"Semiconductors for smartphones will see healthy revenue growth as demand for increased speeds and additional features continue to drive high-end smartphone demand in developed countries and low-cost smartphones in developing countries. Lower cost smartphones in developing countries will make up an increasing portion of the mix and moderate future mobile wireless communication semiconductor growth. PC semiconductor demand will remain weak for 2013 as the market continues to be affected by the worldwide macroeconomic environment and the encroachment of tablets," said Nina Turner, Research Manager for semiconductors at IDC.

According to Abhi Dugar, research manager for semiconductors, embedded system solutions, and associated software in the cloud, mobile, and security infrastructure markets, "Communications infrastructure across enterprise, data centers, and service provider networks will experience a significant upgrade over the next five years to support the enormous growth in the amount of data and information that must be managed more efficiently, intelligently, and securely. This growth is being driven by continued adoption of rich media capable mobile devices, movement of increasingly virtualized server workloads within and between datacenters, and the emergence of new networking paradigms such as software defined networking (SDN) to support the new requirements."

Regionally, Japan will be the weakest region for 2013, but IDC forecasts an improvement over the contraction in 2012. Growth rates in all regions will improve for 2013 over 2012, as demand for smartphones and tablets remain strong and automotive electronics and semiconductors for the industrial market segment improve in 2013.

Rudolph Technologies, Inc., a provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, today released three new application-specific configurations of its industry-leading NSX 320 Automated Macro Defect Inspection System. The suite includes specially-designed configurations for wafer level packaging, 2.5D (interposer) and 3DICs using through-silicon via (TSV) as interconnects. The first NSX 320 Metrology System for wafer level packaging shipped in June to a major outsourced assembly and test (OSAT) facility in Asia.

“These new application-specific configurations of our established NSX 320 System are designed to address the emerging need for fast, precise three-dimensional (3D) measurements in the rapidly growing advanced packaging market sector,” said Rajiv Roy, vice president of business development and director of back-end marketing at Rudolph Technologies. “We have completed the integration of 3D measurement sensors, recently acquired from Tamar Technology, into the NSX System. Tamar’s sensor technology is well recognized and widely used, and integrating it into the NSX 320 System adds critical capability required for enabling advanced packaging applications such as copper pillar bumping and TSV.”

The NSX 320 wafer level packaging configuration is designed to measure film thickness (polymers, photoresist, glass), thin remaining silicon thickness (RST), surface topography, copper pillar height and solder bump height. The advanced wafer level packaging configuration adds measurements of the wafer profile (warp and bow), total stack thickness and thick/thin RST (bonded wafer before and after grind). The 3DIC configuration is capable of all the above measurements plus via depth, trench depth, bonded wafer TTV and adhesive layers.

Roy stated, “3DIC device volume is forecasted to grow to $38.4B by 2017, according to Yole Développement. Rudolph is positioned to address the growth requirements for wafer level packaging, as well as 2.5D and other advanced packaging technologies, with industry-proven metrology tools that offer superior speed and measurement solutions.”

Dialog Semiconductor plc, a provider of highly integrated power management, audio, AC/DC and short-range wireless technologies today announced that Richard Beyer, appointed to the board in February this year, as an independent non-executive director, will succeed Gregorio Reyes as chairman of the board. Greg will continue to serve as a board member.

Beyer, 64, was the chairman and CEO of Freescale Semiconductor from March 2008 to June 2012, subsequently retiring from the board in April this year. Prior to this, he held successive positions as CEO and director of Intersil Corporation, Elantec Semiconductor and FVC.com. He has also held senior leadership positions at VLSI Technology and National Semiconductor Corporation and served as an officer in the US Marine Corps. In 2012, he was chairman of the Semiconductor Industry Association Board of Directors and served for three years as a member of the US Department of Commerce’s Manufacturing Council. He currently serves on the Board of Micron Technology Inc.

Dialog’s board said that Reyes has been an excellent Chairman, presiding in that position over the last six consecutive years of revenue growth and significant increase in shareholder return. He steps down as chairman on the high note of the positively received acquisition of iWatt Inc. earlier this month.

After a flat year in 2012, global purchasing of semiconductors by the world’s top electronic brands is set to return to growth in 2013, as Apple Inc. and Samsung Electronics contend to claim the title of biggest spender.

The total available market, or TAM, for semiconductor spending by major original equipment manufacturers (OEM) in 2013 will rise to $265.2 billion this year, up 4.2 percent from $254.4 billion in 2012, according to a Semiconductor Spend Analysis Market Tracker Report from information and analytics provider IHS (NYSE: IHS). Spending by year-end will be at its highest level in six years, with expenditures in 2014 forecast to make another modest jump to $279.4 billion.

This top OEM semiconductor spending TAM represents about 83 percent of the total semiconductor market of $318.8 billion, as valued by the IHS Application Market Forecast Tool (AMFT).

If internal chip consumption within companies is excluded, the served available market for semiconductor spending, or SAM, will equate to an amount slightly lower than the TAM, at $241.3 billion in 2013.

As IHS announced in 2012, Apple is set to maintain leadership in the OEM semiconductor spending SAM in 2013. However, when also accounting for consumption of internally produced chips, Samsung will take the lead in terms of TAM this year.

“Depending on the metric used, either Samsung or Apple will be the top chip spender for 2013,” said Myson Robles-Bruce, senior analyst for semiconductor spend & design activity at IHS. “Either way, the honor does not merely signify bragging rights but also carries attendant overtones of prestige and influence, with the incumbent leader often tacitly acknowledged by all others as the industry’s top semiconductor spender.”

Other OEMs that make an appearance in both TAM and SAM lists—rankings vary depending on the roster—include Hewlett-Packard, Lenovo, Sony, Dell, Cisco Systems, Panasonic, Toshiba and Asustek Computer.

Wireless is king, but computer platforms still matter

Not surprisingly, the greatest share of spending this year will be in wireless communications, where Samsung and Apple lord over other players. Wireless alone is forecast to gobble up 26 percent—approximately $62 billion—of total top OEM semiconductor SAM. Wireless is also expected to be the highest growth market in 2013 after an annual projected expansion of 12.8 percent.

Within the wireless segment, handsets continue to be the single largest market, with OEM chip spending in 2013 expected to reach $46.7 billion. Media tablets are next at $8.2 billion, exceeding wireless infrastructure for the first time after the latter falls this year to $7.1 billion.

After wireless, computer platforms representing PCs and similar computing devices collectively represent the next-largest segment, forecast to take up 23 percent of OEM chip spending. China, which became the world’s biggest market for PC shipments last year, continues to account for a hefty part of PC-related chip spending even as the overall global computer market has slowed.

However, it should be noted that if the computer platforms segment is combined with the computer peripherals market, it becomes the largest single semiconductor market, beating wireless.

Following wireless and the computer platforms segment are the other smaller markets that take up the rest of OEM chip spending. In decreasing size, these segments are consumer, computer peripherals, automotive, industrial and wired communications, with share portions for each ranging from 6 to 15 percent.

Among semiconductor components, OEM chip spending this year will be largest in logic integrated circuits (IC) at nearly $75 billion, followed by memory ICs at $44 billion. The rest of the categories being tracked include analog ICs, discrete chips, microcomponent ICs, optical semiconductors, and sensors and actuators.

North America-based manufacturers of semiconductor equipment posted $1.33 billion in orders worldwide in June 2013 (three-month average basis) and a book-to-bill ratio of 1.10, according to the June EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in June 2013 was $1.33 billion. The bookings figure is 0.7 percent higher than the final May 2013 level of $1.32 billion, and is 6.6 percent lower than the June 2012 order level of $1.42 billion.

The three-month average of worldwide billings in June 2013 was $1.21 billion. The billings figure is 1.4 percent lower than the final May 2013 level of $1.22 billion, and is 21.4 percent lower than the June 2012 billings level of $1.54 billion.

“The SEMI book-to-bill ratio has been above parity for six consecutive months and bookings in the quarter ending in June are 20 percent above the quarter ending in March,” said Denny McGuirk, president and CEO of SEMI.  "As recently announced, we anticipate that total worldwide equipment spending will decline by low single-digits this year and rebound with a double-digit growth rate in 2014.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

 

Billings 
(3-mo. avg)

Bookings
 (3-mo. avg)

Book-to-Bill

January 2013

968.0

1,076.0

1.11

February 2013

974.7

1,073.5

1.10

March 2013

991.0

1,103.3

1.11

April 2013

1,086.3

1,173.9

1.08

May 2013 (final)

1,223.4

1,321.3

1.08

June 2013 (prelim)

1,206.8

1,329.9

1.10

Source: SEMI, July 2013


The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains.. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. For more information, visit www.semi.org.

Researchers sponsored by Semiconductor Research Corporation (SRC), the world’s leading university-research consortium for semiconductors and related technologies, today announced that they have developed a more efficient purge technique that reduces the consumption of ultra-high purity (UHP) purge gases by more than 20 percent during the production of semiconductors. The new process has been co-developed with Intel Corporation and can be applied to a wide range of manufacturing operations beyond the chip industry.

In response to industry demand, the research performed by the SRC Engineering Research Center (ERC) for Environmentally Benign Semiconductor Manufacturing has focused on minimizing the amount of UHP bulk gases used to purge and clean tools and gas distribution systems. The new technique—called Pressure Cyclic Purge (PCP)—can easily replace the industry’s standard steady-purge method while delivering welcomed energy and gas savings.

Currently, the widely used conventional steady-purge method for cleaning and drying highly sensitive equipment and gas distribution systems requires flowing large amounts of expensive gases through production equipment and distribution systems; this procedure results in higher cost and waste of consumables. As contamination continues to be a major concern in scaling devices to smaller feature size for enhanced density and performance, the inefficient use of expensive purge gases to eliminate contaminants is a key challenge to the productivity of future IC technologies.

“The widespread use of ultra-pure gas for purging purposes, which essentially all goes to waste, has been a significant environmental and efficiency issue for more than a decade,” said Farhang Shadman, lead researcher and the ERC Director at the University of Arizona for the SRC-funded research. “Reduction of both UHP gas usage as well as the resources used for purification processes are environmental gains in the fab, as well as in the production and supply of these gases.”

Through direct measurement and system simulations, the SRC-supported research has demonstrated that the unique flow and cyclic change in the new PCP technique utilizes substantially smaller amounts of purge gases and achieves the required cleanliness in a shorter period of time. For example, the new approach can accelerate the time for the industry’s standard gas distribution system ‘dry down’ process by greater than 30 percent for large, complex systems with the PCP technique.

“Continual increase in environmental quality and cost-effectiveness are on-going goals for our R&D and we have already demonstrated the benefits of this new approach at several sites,” said Carl Geisert, Senior Principal Engineer at Intel. “As we continue to push reduction of contaminant levels towards the parts per trillion level, collaboration between industry and the ERC is key to continued progress toward our goals.”

In addition to Intel, other SRC members have access to a simulator program that can be customized with the PCP technique for their needs. Tests with the new purge technique suggest that the simulator will be ready for commercialization by early 2014. The PCP technique is expected to be relatively easy to implement with minimal change in hardware or configurations for existing fabs and facilities.

In addition to semiconductor equipment and manufacturing companies, other industries that use ultra-clean gases for planar or patterned surfaces and small structures should also benefit from this technology. For example, makers of optics, optoelectronics and flat panel display are expected to show great interest in the tightly regulated semiconductor manufacturing processes such as the PCP technique. As this new purge technology moves quickly toward commercialization, development is underway for its integration into various process tools.

“This progress is reflective of the kinds of innovative approaches that simultaneously provide environmental gain, process improvement and cost reduction for semiconductor and other industries,” said Bob Havemann, Director of Nanomanufacturing Sciences at SRC. “That’s been the legacy and the mission of the SRC Engineering Research Center in the projects that we conduct jointly with industrial members for the purpose of enhancing the environmental sustainability of semiconductor manufacturing.”

Part 1 of this blog covered International Technology Roadmap for Semiconductors (ITRS) updates to System Drivers, Design, Modeling and Process Simulation, Process-Integration Device and Structures (PIDS), and Front-End Processing, as presented in a session on the last day of SEMICON/West 2013.

SEMATECH’s Mark Neisser provided a sobering overview of the challenges associated with extending Lithography technology to pattern device structures below a half-pitch of 20nm. The ITRS Lithography International Technology Working Group (ITWG) works with pitch and half-pitch ranges as lithographically determined and so do not have an exact correspondence to “nodes.” ArF light sources at 193nm wavelength have been extended as far as possible using immersion, and all so-called “next-generation lithography” (NGL) technologies have problems, such that it’s unsure if any will be ready at the decision points needed insertion into future chip-making lines. Today, we can look at anticipated  half-pitch ranges needed for proposed device structures and determine which proven technologies could be used:

  • 30-20nm half-pitch is the limit of ArF Double-Patterning,
  • 19-15nm half-pitch is estimated as the limit of EUV Single-Patterning,
  • 14-11nm half-pitch is estimated as the limit of ArF Quadruple-Patterning, and
  • 10-8nm half-pitch corresponds to the estimated limit of EUV Double-Patterning at the current NA.

“The industry needs an alternative to Quadruple-Patterning,” opined Neisser, “and the price-per-bit won’t necessarily go down.”

Front End Processes (FEP) needed for future chip-making were reviewed by Joel Barnett of Tokyo Electron. The FEP team is in flux, and Barnett solicited new team members. “Really what’s driving FEP these days is new materials for both logic and memory,” explained Barnett. New materials raise unpredictable integration challenges, for deposition, etch, cleaning, and metrology. We need to know the correlation between electrical properties and materials structures, and how can interfaces be engineered. Continued scaling of High-Performance finFET logic devices is challenging in all aspects:  EOT, junctions, mobility enhancement, new channel materials, parasitic series resistance, and contact silicidation. Fin pitch has now been set by consensus with the PIDS and Lithography ITWGs to be 0.75 of M1 pitch.

Emerging Research Devices (ERD) that could replace standard CMOS FETs were discussed by An Chen of GLOBALFOUNDRIES with an emphasis upon novel memory technologies. One surprise was the removal of “nano-mechanical memory” from tracking in the main ERD table due to lack of progress. Resistive-RAM (RRAM) is now anticipated to move into commercial manufacturing in 2018, and the ERD ITWG plans to start tracking 4 different RRAM technologies in a new table: conductive-bridge RAM (CBRAM), metal-oxide bipolar filament, metal-oxide unipoloar filament, and metal-oxide bipolar interface effect. Unlike conventional Flash many emerging memory devices need a “select device,” and while transistors provide the best performance 2-terminal devices are more easily scaled. On the logic side, ERD anticipates new devices with “learning capabilities” to be developed in the long-term such as neuromorphic chips.

Emerging Research Materials (ERM) that could be needed to integrate new functionalities into integrated circuits were shown by C. Michael Garner, now with Stanford and Garner Nanotechnology Solutions. Alternate-channel materials such as Ge and III-V compounds seem destined to be used in future CMOS, and the best results to date combine Ge pMOS with III-V nMOS. However, integration cost and complexity would be reduced if only one new material could be coaxed into use as the alternate-channel, and so there is continuing work on Ge nMOS and III-V pMOS transistors. Contacts are important for all new materials, so the engineering of atomic-interfaces will be critical for future devices.

“A few people have demonstrated that providing a very thin barrier counter-intuitively lowers contact resistance,” shared Garner.

Click here for more news from SEMICON West 2013.

In the afternoon of the last day of SEMICON/West 2013, a session was devoted to updates from the International Technology Roadmap for Semiconductors (ITRS) Front End of Line Technologies. Representatives from the different International Technology Working Groups (ITWG) provided highlights from the work now happening on the 2013 update.

Andrew Kahng of U.C. San Diego provided two presentations on challenges associated with future ICs:  System Drivers and the Design. Systems today are clearly driven by System-on-Chip (SoC) and mobile. The size of a typical mobile phone SoC is expected to double from ~50 mm2 to ~100 mm2 due to increased  integration of new functionalities such as Graphics Processing Units (GPU), memory controllers, and input/output (I/O) interfaces. Overall power for such a chip in the distant future would consume >200W of power compared to today’s ~8W unless new technologies are employed. Some future drivers such as medical and defense are now in question; will these segments develop unique devices and processes or will they simply ride on the progress of mainstream commercial IC development.

“The latter scenario is looking more likely now,” said Kahng.

Constant area-factors allowed prior node scaling to be 2x, however since 2009 the real scaling has been 2E(2/3)x or ~1.6x due to an “IC Design Gap.” This gap is due to overheads from non-core blocks and additional overheads from PIDS effects on the area needed for cores. Design cost for a SoC consumer portable chip in 2011 were $40M, helped by commercial EDA software advances over the last decades. Today only at most 2.4 percent of the logic in an SoC is turned on at any time, which is how the power can be kept to ~8W.

Modeling and Process Simulation challenges were covered by Lothar Pfitzner of Fraunhofer IISB, with understanding that the overarching goal of this ITWG is to use virtual cycle-of-learning to lower R&D costs. To do so there are different models needed in different conceptual domains, “based on quantitative physical understanding of processes, devices, circuits, and systems,” explained Pfitzner. “Both short-term and long-term challenges remain in modeling of chemical, thermo-chemical and electrical properties of new materials.”

PIDS updates on logic, DRAM, and Non-Volatile Memory (NVM) were provided by Mustafa Badaroglu of Qualcomm. PIDS mission is to forecast device technologies likely to be used 15 years in the future of main-stream manufacturing. With Denard-scaling now part of history, the specifications for future transistors using either FD-SOI or multi-gate (such as finFET) technologies require TCAD simulations of source-to-drain tunneling, band structure effects due to strong confinement, as well as crystallographic orientation and strain. The current target is an overall eight percent power reduction per year in logic, but parasitics dramatically limit device performance, and gate-length scaling is endangered by increased tunneling.

A 2013 survey recently done by the Japan PIDS regional group provides a consensus on when new devices are expected to reach volume manufacturing. For DRAM cells there has been a slight relaxation of the planned half-pitch, and  the cell size transition from 6F2 to 4F2 planned for 2016 (delayed by two years from the last ITRS update), and vertical transistors are likewise planned for 2016. RRAM is now planned as mainstream technology in 2018, and is projected to catch-up with the bit density of 3D Flash in 2021; however, development of a selector diode in a 3D architecture remains a challenge. The Purdue University TCAD tools (NanoHub) will continue to be developed to better project device characteristics, and new websites within NanoHub will be created to allow free public access to the tools.

Part 2 of this blog will cover ITRS updates on Lithography, Front-End Processing, and Emerging Research Materials/Devices.

Click here for more from SEMICON West.

 

cyberTECHNOLOGIES GmbH announced the addition of White-Light Interferometry (WLI) to its suite of production-proven CT SERIES non-contact surface metrology systems at SEMICON West 2013. WLI significantly broadens the range of use cases and applications of the existing CT SERIES, CT 100, CT 300 and CT x50T product lines and allows the user to not only scan large areas or samples, but also to zoom in on very small areas of interest for sub-nm analysis.

The new WLI modules can be installed either by itself or concurrently with the existing point sensors and provides the user with the ability to measure a broad range of applications, from surface topographies and printed structures on the order of several hundred micrometers down to sub-nanometer resolution surface roughness measurements, in a single system.

“Our customers want to take advantage of our superior user interface and automation capabilities not just in scanning applications but also for use cases where sub-nanometer resolution is required, “ said Frank Kemnitzer, head of product management at cyberTECHNOLOGIES GmbH. “With the WLI module installed, they can now select between different measurement technologies and adapt the measurement system to their requirement at hand. All within the same easy to use interface, the same advanced analysis capabilities, without learning how to use another system.” The systems were designed with modularity and versatility in mind and the addition of the new WLI sensors further broadens their range of applications.

Be it for quick, individual measurements on a single or multiple samples or the automatic inspection of complete production runs, cyberTECHNOLOGIES’ SCAN SUITE makes it simple and easy for the user to get accurate results.

Multiple systems with WLI  have been installed at leading manufacturers in Europe, Asia and North America.