Category Archives: Metrology

By Dr. Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc., San Jose, Calif.

Random process variations and layout-dependent effects are a fact of life for designers working at the more advanced process nodes and become critical at 45nm. Besides random and systematic variation effects, reliability effects, such as bias-temperature-instability (BTI), also become prevalent, introducing another dimension of variations that impact parametric yield.

These variations are unavoidable and, in fact, increasing as we move to more advanced nodes, where circuit designers encounter yield problems and need to spend extra effort on variation analysis for yield and performance trade-off. 

On one side, foundries have to double or even triple their efforts to make complicated model libraries to characterize different types of variations, despite having to cover variation sources across the full statistical space –– an impracticality.

Conversely, efficiently running variation analysis with the best use of foundry models becomes critical for circuit designers, and is one of the more challenging aspects of system-on-chip (SoC) design that project teams face daily.

This means design-for-yield (DFY) considerations are more important than ever. And yet, we as an industry may not fully understand device modeling and its impact on DFY results. This is due in large measure to no clear definition of DFY. Some people are confused by DFY and design-for-manufacturing (DFM), and consider DFY a foundry’s responsibility or do not know what the role of DFY is. The value of DFY highly relies on how “good” the foundry models are and how efficient the tool can leverage model information to run needed analysis, such as statistical circuit simulations.

Foundry models can never be perfect, but represent process information that a DFY analysis requires. Designers need to have an appropriate expectation on models, especially for advanced technologies, and also understand model limitations. With this understanding, extracting information from models and making good use of this information together with DFY tools is becoming more critical.

Of course, DFY is not a new phenomenon and tools being categorized for DFY have been available commercially for some time now. They haven’t been widely adopted because they have not provided enough value to project teams due to the lack of information or confidence in the analysis results. Statistical simulation, such as Monte Carlo analysis, has been costly and time consuming, even for a 3s problem. Designers either skip Monte Carlo or often run a small number of samples that can limit the confidence level, making DFY analysis results unreliable and less valuable. Other types of analysis, including process-voltage-temperature (PVT) analysis, also run into similar problems if designers want to cover all corner cases that can easily increase up to hundreds of corners. A faster simulation engine, intelligent statistical analysis algorithms, and better use of foundry model information are the key components that EDA companies need to provide to make DFY tools more practical and reliable.

The final key would be on the application side. Circuit designers need to understand when and where they can apply DFY on top of their traditional design flow, and how to leverage DFY to achieve an optimal yield versus performance-power-area (PPA) trade-off.

Please join Solid State Technology’s own Pete Singer who will moderate a panel discussion on this topic, “Learn the Secrets of Design for Yield,” during the 50th Design Automation Conference (DAC). It will be held Wednesday, June 5, from 1:30 p.m. until 2:15 p.m. in Booth #509 on the Exhibit Floor at the Austin Convention Center in Austin, Texas.

A panel of foundry experts will weigh in with their opinions: Dr. Min-Chie Jeng from Taiwan Semiconductor Manufacturing Co. (TSMC); Dr. Luigi Capodieci from GLOBALFOUNDRIES; and Dr. Bruce McGaughy from ProPlus Design Solutions, Inc. They will share best practices and techniques to manage these sub-nanometer effects to improve manufacturability and yield. You can expect some insights into how foundries handle variations and how models are created. They will discuss how EDA companies handle variations in their tools, making variation analysis faster yet still reliable. And finally, attendees can expect to get some guidance and advice on how to better use foundry models and how to better use DFY tools in real designs.

As an organizer, along with Tom Wong of GLOBALFOUNDRIES, I expect to learn plenty and will share some of the conclusions in future blogs, including whether design for yield is the same as design for manufacturing.

About Zhihong Liu

Dr. Zhihong Liu is executive chairman of ProPlus Design Solutions, Inc. He was most recently corporate vice president for CSV R&D at Cadence Design Systems Inc. Dr. Liu co-founded BTA Technology Inc. in 1993 and invented BSIMPro, the leading SPICE modeling product. He also served as the president and chief executive officer of BTA Technology Inc. and later Celestry Design Technology Inc., acquired by Cadence in 2003. Dr. Liu holds a Ph.D. degree in Electrical Engineering from the University of Hong Kong and co-developed the industry’s first standard model (BSIM3) for IC designs as one of the main contributors at the University of California at Berkeley.

by Debra Vogler, SEMI

In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers and industry experts to comment on the challenges they wanted to highlight. Many of the inputs focused on the need for precision in the processes used to form transistors, as well as how EDA can contribute to mitigating variability.

Likely enhancements on the logic roadmap below 20nm are a move to FinFET, improved FinFET implementation, high mobility channel, and gate all around (GAA) structures, noted Adam Brand, senior director, Transistor Technology Group at Applied Materials. He told SEMI that, “The increased complexity of the FinFET, high mobility channel, and GAA devices in combination with continued scaling requires more precision in structure formation and improved materials to address structure formation and parasitic effects.”

The key steps for maintaining the structural integrity of the fin are precision etch, void-free STI fill, recess, and precisely tailored corner rounding through dummy gate oxidation. Dummy gate oxidation addresses the challenge of ensuring that electric fields can be avoided in the corner explained Brand, who will present at SEMICON West 2013 (http://www.semiconwest.org). “The dummy gate serves two purposes,” said Brand. “It’s a structural element and it’s there when you do the transistor formation so it can serve roles such as being the etch stop for the gate etch. It’s also able to play a role in shaping the fin.” The fin can be shaped by changing the oxidation rate depending on the amount of oxidation needed for the side vs. for the corner.

Precision again comes into play when forming the gate — precision CMP is required to control the dummy gate and replacement metal gate height. The dummy gate material must also be easily removed. “Advanced CVD materials offer more choices in materials for differentiating selective removal,” said Brand. “Implant-based precision material modification (PMM) has been effective in changing selectivity to obtain better structure control.” He noted that in the past, CMP had not played a role in directly affecting the geometry of the transistor, but now, it is playing a much more direct role in determining the size of the transistor features. For example, in the replacement metal gate step, CMP is used to polish the metals used for the replacement gate structure and it’s also used for the self-aligned contact polish. “So now, you’re polishing the gate at least three times in order to form it, and you need very precise gate height control because it affects the overall stack height and contact height.”

Further complicating transistor scaling is that the 3-D structure adds complexity in strain-related mobility enhancement. “Source/drain stressor shaping is needed to optimize strain and control unwanted increase in the Miller capacitance,” said Brand.  “Lower k dielectrics are also needed to manage the Miller capacitance.” He further explained that when strain is implemented in a FinFET, each source/drain area is a separate fin — as opposed to when strain is being implemented on planar devices. “When you grow the source/drain [in a FinFET], it grows both horizontally and vertically, so when you scale the pitch of the fins, there’s the challenge that eventually those source/drain stressors come very close to each other and they might merge.” The solution, therefore, has to allow the stressors to grow without having them merge between the transistors and still obtain the amount of strain that is wanted. The solution must also address the Miller capacitance. 

The SOI value proposition changes below 20nm

Gary Patton, VP at IBM’s Semiconductor Research and Development Center, told SEMI that in order for the full benefit of the FinFET to be realized below 20nm, a dielectric isolation scheme is necessary to counter the uniformity and variability challenges. “The arrival of the FinFET era has brought about a fundamental paradigm shift in the SOI value proposition such that the advantages of SOI-based innovation now extend well beyond just device performance as in the planar case,” said Patton.  Indeed, Soitec, and others, such as STMicroelectronics, are betting that SOI-based technology will be used as a bridge enabling the industry to get the performance benefits of a fully-depleted transistor while staying with a planar transistor all the way from 28nm down to 14nm, or perhaps even sub-14nm.

To those who question the added cost of going with an SOI-based platform, Patton said that the cost of dealing with the isolation challenge offsets the cost of using SOI substrates. “Offset costs are due to both additional process steps required for bulk, and increases to die area,” said Patton. “An STI isolation module must be added for bulk FinFETs, as well as a series of masking steps and implants for isolation-leakage control and latch-up avoidance. Estimated additional processing costs of bulk isolation offsets the cost advantage of bulk substrates over SOI.” He also pointed out that die area increases are driven by the need for well contacts, and I/O guard-rings (latch-up avoidance). “We also anticipate the overall die yield to be challenging for the bulk FinFET process due to variability and the need for matching performance of critical circuit paths in a chip.”

Another consideration for proponents of SOI-based technology is the issue of process variability. “A buried oxide layer (BOX) in SOI fins is responsible for three areas of improvement in variability over bulk-isolated FinFETs,” Patton told SEMI. “First, the top silicon layer is terminated by the buried oxide, is proven to be extremely uniform in thickness, and defines the height of the fin both physically and electrically, since any fin over etch does not contribute to the fin height.” He further explained that the source and drain are completely separated by the gated channel, unlike in a bulk FinFET, where there is a continuous path for leakage, requiring a highly doped punch-through stop.

“The non-abrupt nature of doping introduces a non-uniform doping profile, and hence, turn-on current, between the top and bottom of the fin, further eroding the FinFET advantage.” Patton noted that a more practical consideration is the slope or taper of the fin itself. “From an electrical point of view, the ideal fin would be perfectly vertical and of uniform thickness from top to bottom. In a bulk fin process, a degree of taper must allow for the subsequent oxide fill and etch-back, and also to accommodate a reduced spacer over-etch budget (vs. an SOI fin). The fin taper introduces further non-uniformity to the FinFET, which reduces switching speed.”

EDA tackles variability

Reducing/mitigating process variability is ever more critical to yield as the industry scales transistors below 20nm, and much can be done in the design arena to help. For example, EDA considerations can mitigate “noise” in the optical system [lithography] that is a source of variability.

Mike Rieger, group director, R&D, Silicon Engineering Group at Synopsys, uses communication theory to analyze certain aspects of a lithographic system. He told SEMI that when there are optical systems [lithography] without tuning, i.e., a “plain vanilla” system — all the spatial frequencies in the visible limit are present. Conversely, when the design is friendly to specific spatial frequencies and you then try to print that design with an optical system that is friendly to all spatial frequencies, there are other frequencies that leak through. This “leakage” causes a lowering of the contrast in the optical image. “With the lower contrast, the image is more susceptible to other sources of variation like defocused variation, or dose variation, and that translates into your printed features having more variation in their dimensions,” said Rieger, another speaker at the upcoming SEMICON West (http://www.semiconwest.org).

Rieger added that, if you can prevent the unwanted frequencies from even being passed through the optical system, the net result is that the contrast is improved. Additionally, by tuning these frequencies, the diffraction orders in the stepper (the rays of light used to form the image) are manipulated. “You can eliminate the zero order ray. This zero order ray reduces contrast and it also limits the maximum frequency that you can image.” The tuning process – also known as source mask optimization (SMO) – really isn’t the end game, noted Rieger. “It’s source design optimization that is the end game. You tune the configuration of your design to be consistent with the optimization of the source.”

Regarding the parallel paths the industry is taking – extending optical lithography while developing EUVL — Rieger is realistic in his assessment of what EDA can bring to the table. “We’re going to be using 193i for the foreseeable future — it will be years before 193i is replaced,” said Rieger. But, “Optical lithography on a single exposure is maxed out in terms of the density it can print, so if you want to get more transistors per chip or more details per chip, you must do a couple of things.” Those are: tuning the optics, which comes at a cost, and using multiple exposures. “To get an effective result, the whole process of the tuned optics and the multiple exposures must be comprehended in the physical layout software, and some of the things that need to be done go beyond what you can accomplish with the traditional rule-based constraint that you put on the layout.”

For more information on SEMICON West 2013, visit http://www.semiconwest.org. To view all the TechXPOT info, visit http://www.semiconwest.org/SessionsEvents/TechXPOTs.

Register through June 7 at only $50 here: http://www.semiconwest.org/registration. Note that registration fees increase on June 8.

 

At next week’s 50th Design Automation Conference (DAC) in Austin, Texas, GLOBALFOUNDRIES will unveil a comprehensive set of certified design flows to support its most advanced manufacturing processes. The flows, jointly developed with the leading EDA providers, offer support for implementing designs in the company’s 20nm low power process and its 14nm-XM FinFET process. Working closely with Cadence Design Systems, Mentor Graphics and Synopsys, GLOBALFOUNDRIES has developed the flows to address the most pressing design challenges, including support for analog/mixed signal (AMS) design, and advanced digital designs, both with demonstration of the impact of double patterning on the flow.

The GLOBALFOUNDRIES design flows work with its process design kits (PDKs) to provide real examples that demonstrate the entire flow. The user can download the design database, the PDK, detailed documentation and multi-vendor scripts to learn how to set up and use the GLOBALFOUNDRIES design flow. The flows use open source examples and provide the customer with working, executable and customizable flows.

“As the developer of the industry’s first modular 14nm FinFET technology and one of the leaders at 20nm, we understand that enabling designs at these advanced process nodes requires innovative methodologies to address unprecedented challenges,” said Andy Brotman, vice president of design infrastructure at GLOBALFOUNDRIES. “By working with a new level of collaboration with EDA partners, we can provide enhanced insight into our manufacturing processes in order to fully leverage the capabilities of 20nm and 14nm manufacturing. This provides our mutual customers with the most efficient, productive and risk-reduced approach to achieving working silicon.”

Production ready AMS flow from specification to verification

To address the unique requirements of analog/mixed signal (AMS) design at advanced processes, GLOBALFOUNDRIES has enhanced its design flows to provide production quality scripts and packaged methodologies. The new reference flow establishes a working flow from specification to physical verification that has been taped out to be verified on working silicon.

The AMS reference flow provides comprehensive double pattern design guidelines. It gives overview of decomposition flow for both block level and chip level. The flow also addresses decomposition for different design styles. Recommendations for color balancing, hierarchical decomposition, ECO changes are discussed. The flows also present decomposition impact on DRC run time and resulted database size.

Notably, the reference flow includes support for efficiency and productivity improvements in the Cadence Virtuoso environment specifically for designing in a double patterned process. The flow includes support for Virtuoso Advanced Node 12.1 and provides efficient access to the tool’s productivity benefits for physical design with real-time, color-aware layout. Circuit designers can assign “same net” constraints in the schematic, and the layout designers can meet these requirements as they create the physical view. Additionally, layout designers can take advantage of Virtuoso tool support for local interconnect, and advanced layout dependent effect management.

The flow also features interoperability with Mentor’s Calibre nmDRC, nmLVS, and extraction products which address multipatterning requirements for both double and triple patterning. In addition special settings for analog design; auto-stitching and when to use it; and fill and color balancing are described in detail.

The AMS flow provides detailed information on parasitic extraction and layout dependent effects, both of which introduce new challenges at 20nm and 14nm. For parasitic extraction, the flows are described in detail and customizable scripts and examples demonstrate OA and DSPF back annotation. In addition the flows illustrate methodologies to predict layout-dependent effects during schematic design and methods to include full models in post layout extraction. PEX flows for Synopsys StarRC extraction, Cadence QRC and Mentor CalibrexRC are supported.

These flows serve as references to validate the correctness of the accompanying PDK as well as the vendor tools setup.

Sign-off ready RTL2GDSII flows that address double patterning

GLOBALFOUNDRIES is also making available new flows that support a complete RTL-to-GDSII design methodology for targeting its 20nm and 14nm manufacturing processes. The company worked with EDA vendors to certify the flows in their respective environments and provide a platform for optimized, technology-aware methodologies that take full advantage of the performance, power and area benefits of the processes.

The result is a set of fully executable flows containing all the scripts and template files required to develop an efficient methodology. The flows serve as a reference to validate the correctness of the accompanying PDK as well as the vendor tool setup. In addition the flows offer access to other critical and useful information, such as methodology tutorial papers; guidelines and methodologies for decomposition of double patterned layouts; PEX/STA methodology recommendations and scripts; and design guidelines and margin recommendations.

A critical aspect of manufacturing at this level is the use of double patterning, an increasingly necessary technique in the lithographic process at advanced nodes. Double patterning extends the ability to use current optical lithography systems and the GLOBALFOUNDRIES flows provide comprehensive double pattern design guidelines. They address design for double patterning and the added flow steps for different design styles and scenarios.

This includes support for odd cycle checking, a new type of DRC rule that must be met to allow for legal decomposition of the metals into two colors. This check is detailed in the flow and guidelines are provided to make sure it is met.

Synopsys and GLOBALFOUNDRIES worked together to minimize the impact of changes associated with the 3-D nature of FinFET devices as compared to planar transistors.  The two companies focused on making FinFET adoption transparent to the design team.  The collaboration on Synopsys’ RTL to GDSII flow includes 3-D parasitic extraction with the Synopsys StarRC tool, SPICE modeling with the Synopsys HSPICE product, routing rules development with the Synopsys IC Compiler tool and static timing analysis with the Synopsys PrimeTime tool.

Cadence contributed a complete RTL-GDSII flow, including physical synthesis, and planning and routing developed with the Encounter Digital Implementation (EDI) System foundation flow. The seamless implementation flow, using Cadence Encounter RTL Compiler and EDI System, supports double patterning and advanced 20- and 14-nm routing rules.

Mentor’s Olympus-SoC place and route system is supported in the flow, providing support for new DRC, double patterning, and DFM rules. The Olympus-SoC router has its own native coloring engine along with verification and conflict resolution engines that detect and automatically fix double patterning violations. Expanded features include DP-aware pattern matching, coloring aware pin access, pre-coloring of critical nets, and DP aware placement. The Calibre InRoute product allows Olympus-SoC customers to natively invoke Calibre signoff engines during design for efficient and faster manufacturing closure.

Double patterning also impacts LVS and other DRC issues, and the flows provide methodology details to address these areas, including hierarchical decomposition to reduce data base explosion. Parasitic extraction methodologies and scripts are provided as well, offering ways to address double patterning-induced variations via DPT corners or with maskshift PEX features.

Later this month, IC Insights’ May Update to The 2013 McClean Report will show a ranking of the top 25 semiconductor suppliers in 1Q13.  A preview of the top 20 companies is listed in Figure 1.  The top 20 worldwide semiconductor (IC and OSD—optoelectronic, discrete, and sensor) sales leaders for 1Q13 include nine suppliers headquartered in the U.S., four in Japan, three in Europe, and two each in South Korea and Taiwan, a relatively broad representation of geographic regions.  The top-20 ranking also includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and four fabless companies.

IC foundries are included in the top-20 semiconductor supplier ranking, because IC Insights has always viewed the ranking as a top supplier list, not as a marketshare ranking, and realizes that in some cases semiconductor sales are double counted.  With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  Foundries and fabless companies are each clearly identified in Figure 1.  Overall, the list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

figure 1

It should be noted that not all foundry sales should be excluded when attempting to create marketshare data.  For example, although Samsung has a large amount of foundry sales, most of its sales are to Apple.  Since Apple does not re-sell these devices, counting these foundry sales as Samsung semiconductor sales does not introduce double counting.

In total, the top 20 semiconductor companies’ sales increased by 2 percent in 1Q13 as compared to 1Q12, one point better than the total 1Q13/1Q12 worldwide semiconductor market increase of 1 percent.  It took semiconductor sales of almost $900 million in 1Q13 to make the top-20 ranking.

Intel remained firmly in control of the number one spot in the 1Q13 ranking.  However, Intel lost some of its lead over second-ranked Samsung by registering 45 percent greater semiconductor sales than Samsung in 1Q13 as compared to a 68 percent margin in 1Q12.  The only movement with regard to the top five spots in the 1Q13 ranking was that fabless supplier Qualcomm, riding the continued success of the smartphone market, reported a 28 percent surge in sales (highest among the top 20 companies) and moved up one position to replace Toshiba as the fourth-largest semiconductor supplier.

Micron’s acquisition of Elpida is expected to be completed sometime in 2Q13.  It is interesting to note that if Micron and Elpida’s 1Q13 sales were combined, the “new” company would have had $3,060 million in total sales and would have been ranked as the fifth-largest semiconductor supplier.

As shown in Figure 2, there was a wide range of growth rates among the worldwide top 20 semiconductor suppliers in 1Q13.  The continued success of the fabless/foundry business model is evident when examining the top 20 semiconductor suppliers ranked by growth rate.  As shown, the top nine performers included three fabless companies (Qualcomm, Broadcom, and Nvidia) and three pure-play foundries (TSMC, UMC, and GlobalFoundries).

figure 2

Figure 2 illustrates that four of the five top-20 ranked companies that registered a double-digit sales decline in 1Q13 were headquartered in Japan (Toshiba, Renesas, Fujitsu, and Sony).  However, it should be noted that the conversion of Japanese company semiconductor sales from yen to U.S. dollars, at 79.26 yen per dollar in 1Q12 versus 92.19 yen per dollar in 1Q13, had a big impact on the sales figures for the Japanese semiconductor suppliers.  Thus, while Sony and Fujitsu would have logged a double-digit semiconductor sales decline even if their sales results were not converted to U.S. dollars, Toshiba would have posted a 5 percent increase in semiconductor sales if the figures were expressed in yen.  Unfortunately for AMD, it cannot attribute its extremely poor performance to currency conversion issues.

By Dr. Phil Garrou, Contributing Editor

I have said many times that it will be impossible for a complicated technology like 3DIC to ever become commercial without standardization. SEMI has been working on this now for 3+ years. Let’s take a look at their recent update from their SEMICON Singapore presentation. So far, they have published the following standards:

SEMI 3D1-0912, Terminology for Through Silicon via Geometrical Metrology

– Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services.

– The purpose of this Document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV).

SEMI 3D2-1113, Specification for Glass Carrier Wafers for 3DS-IC

– This Specification describes dimensional, thermal, and wafer preparation characteristics for glass starting material that will be used as carrier wafers in a temporary bonded state;

– Methods of measurements suitable for determining the characteristics in the specifications indicated.

SEMI 3D3-0613, Guide for Multi-Wafer Transport and Storage Containers for 300 mm, Thin Silicon Wafers on Tape Frames

–Address the methods for shipping thin wafers on tape frames.

SEMI 3D4-0613, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks

– Control of bonded wafer stack (BWS) thickness, total thickness variation (TTV), bow, warp/sori, and

– This std provides a description of tools that can be used to determine these key parameters before, during, and after the process steps involved in wafer bonding.

SEMI 3D5-0314, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through- Silicon Vias (TSVs) in 3DS-IC Structures

– This std assists in the selection and use of tools for performing measurements of geometrical parameters of an individual TSV (through-silicon via), or of an array of TSVs.

SEMI 3D6-0913, New Standard: Guide for CMP and Micro-bump Processes for Frontside Through Silicon Via (TSV) Integration

– This std provides a generic middle-end process flow to define acceptable TSV and CMP quality criteria as well as to develop methodology and measuring procedures for micro-bump.

SEMI 3D7-0913, New Standard: Guide for Alignment Mark for 3DS-IC Process

– Photo alignment mark configuration is the key to ensure consistent and precise alignment of layers, chips and wafers.

– This standard provides an alignment mark strategy for chip to chip, chip to wafer, and wafer to wafer stacking.

SEMI also has organized task forces in North America, Taiwan and Japan focused on various aspects of 3DIC manufacturing and testing. The North America task force is focused on:

Bonded Wafer Stacks – Create and/or modify specifica- tions that reflect bonded wafer stacks parameters and the wafer bonding process.

Inspection & Metrology – Develop standards for metrology and inspection methods to be used for measuring TSV properties, bonded wafer stacks, and dies used in the 3DIC manufacturing process.

Thin Wafer Handling – Develop standards for reliable handling and shipping of thin wafers, dies (e.g., Micro- pillar Grid array -MPGA) used in 3DIC high-volume manufacturing (HVM).

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, announced that worldwide sales of semiconductors reached $23.48 billion for the month of March 2013, an increase of 1.1 percent from the previous month when sales were $23.23 billion. Global sales for March 2013 were 0.9 percent higher than the March 2012 total of $23.28 billion, and total sales through the first quarter of 2013 were 0.9 percent higher than sales from the first quarter of 2012. All monthly sales numbers represent a three-month moving average.  

“Through the first quarter of 2013, the global semiconductor industry has seen modest but consistent growth compared to last year,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “Sales have increased across most end product categories, with memory showing the strongest growth. With recent indications that companies could be set to replenish inventories, we are hopeful that growth will continue in the months ahead. Regionally, the Americas slipped slightly in March after a strong start to the year, but Asia Pacific and Europe have seen impressive growth recently.” 

Year-over-year sales increased in Asia Pacific (6.9 percent) and Europe (0.7 percent), but decreased slightly in the Americas (-1.5 percent) and sharply in Japan (-18 percent), reflecting in part the devaluation of the Japanese yen. Sales in Europe increased by 5.7 percent compared to the previous month, the region’s largest sequential monthly increase since March 2010.  Sales also increased from the previous month in Asia Pacific (1.7 percent), but fell in Japan (-1.6 percent) and the Americas (-1.9 percent).

While investments and capital spending in Asia-Pacific garner much of the attention regarding semiconductor manufacturing, spending on equipment and materials in North America has totaled more than $100 billion over the past decade as leading device manufacturers expand capacity and invest in new facilities.  Another $25 billion in equipment and materials spending is forecasted to be spent over this year and next in North America, representing roughly 15 percent of the total spending globally in these two important industry segments. 

Semiconductor industry - investments

Intel, GlobalFoundries, and Samsung have been and continue to be the drivers of investments in North America. IBM and Micron invest in upgrades for leading-edge technology, while Cree and Philips Lumileds invest in LED and related production contribute to spending as well.  The NanoFab Xtension (NFX) facility by the College of Nanoscale Science & Engineering at SUNY Albany represents another major spending project in North America.

Fab investments represent a majority of the equipment spending in North America, though this region remains an important region for spending on test equipment.  Over $1.6 billion has been spent on test equipment in North America in the previous three years, and it is estimated that about another $500 million will be spent this year and in 2014.  SOC/Logic testers were the largest test equipment segment in North America with $356 million in spending in 2011 and $292 million in 2012.  In addition to the test equipment, VLSI Rearch estimates that 2013 test consumables (probe cards, sockets, device interface boards) market for North America is about $530 million.  More information will be available at the upcoming SEMICON West 2013 on July 9-11 in San Francisco. 

Over 50 hours of technical programs and 560+ exhibitors will be available at SEMICON West 2013 to provide the best answers to your questions about 450mm, EUV, 3D-IC, emerging technologies, roadmaps, and more. For information on SEMICON West 2013 (July 9-11), please visit www.semiconwest.org.  Free registration for SEMICON West 2013 ends May 10. Registration includes free access to all TechXPOT sessions, keynotes and executive panels.

The SEMI Industry Research and Statistics group provides market and trend information for market research, competitive analysis, and sales forecasting.

Semiconductor Research Corporation (SRC) and the National Institute of Standards and Technology (NIST) today announced the second phase of the Nanoelectronics Research Initiative (NRI). For this phase, SRC and NIST will provide a combined $5 million in annual funding for three multi-university research centers tasked with demonstrating non-conventional, low-energy technologies that outperform current technologies on critical applications in 10 years and beyond.

The second phase of NRI also features joint projects with the National Science Foundation (NSF) and the multi-university research network involves 34 universities in 17 states. The three research centers are:

  • the Institute for Nanoelectronics Discovery and Exploration (INDEX) at SUNY’s College of Nanoscale Science and Engineering (CNSE);
  • the Center for Nanoferroic Devices (CNFD) at the University of Nebraska-Lincoln; and
  • the South West Academy of Nanoelectronics (SWAN) 2.0 at the University of Texas at Austin.

“In 2012, the first phase of NRI culminated with a comprehensive assessment of the various NRI device concepts through performance benchmarking,” said Tom Theis, the new SRC program executive director. “NRI 2.0 will focus on key research opportunities identified in the benchmarking study and will explore the ultimate scalability of emerging digital device concepts and their functionality beyond digital logic. For example, researchers will explore magnetoelectric devices that promise improved energy efficiency and the ability to combine memory and logic.”

NIST will provide $2.6 million to the effort each year for up to five years, matched by $2.4 million each year from NRI. NRI is made up of participants from the semiconductor industry including GLOBALFOUNDRIES, IBM, Intel, Micron Technology and Texas Instruments.

“NIST collaborations with the NRI are one of the fastest ways to move pre-competitive technology forward,” said Under Secretary of Commerce for Standards and Technology and Director of NIST Patrick Gallagher. “We’re excited to see what innovative nanoelectronic devices and concepts the next phase of this partnership with SRC will produce.”

Additional universities involved in the NRI network include:

  • INDEX at SUNY’s College of Nanoscale Science and Engineering (CNSE): Purdue, Virginia, Cornell, Georgia Institute of Technology and Columbia.
  • CNFD at University of Nebraska-Lincoln: Wisconsin-Madison, Oakland, SUNY Buffalo, UC Irvine, Delaware.
  • SWAN 2.0 at University of Texas at Austin: UT Dallas, North Carolina State, Texas A&M, UC San Diego, Stanford and Harvard.

In collaboration with the National Science Foundation, NRI also supports Nanoscale Interdisciplinary Research Teams (NIRTs) as part of the National Nanotechnology Initiative’s Signature Initiative "Nanoelectronics for Beyond 2020.” Funding for these projects flows to many other leading U.S. universities.

NRI 2.0 is the successor to an earlier multi-year collaboration between NRI and NIST that focused on the long-term goal of “developing the next logic switch,” or the basic logic elements that serve as the building blocks of electronic devices. The NRI initiative was originally launched by the Semiconductor Industry Association (SIA) in 2005. The NRI and the collaboration with NIST are managed by the Nanoelectronics Research Corporation (NERC), a special purpose subsidiary of SRC, the world’s leading university-research consortium for semiconductors and related technologies.

The Nanoelectronics Research Initiative is one of three research program entities of SRC aimed at extending the frontiers of semiconductor electronics.

SEMI today announced that Philip Yeo, chairman of SPRING Singapore, and Lee Kok Choy, country manager of Micron Technology Inc. Singapore, have been voted by the SEMI Singapore Regional Advisory Board as recipients of two prestigious awards recognizing their contributions to the development and success of the Southeast Asian semiconductor industry. The awards will be presented during festivities held at SEMICON Singapore 2013 on 7 May, 2013.

The Lifetime Achievement Award is presented to Yeo for his pioneering and significant contributions to Singapore’s economic development, especially in the promotion and growth of the semiconductor industry. During his tenure as Chairman of the EDB, Yeo was instrumental in leading Singapore’s strategic growth and investment into the semiconductor industry, which today boasts an annual output of over $49 billion, hires over 42,000 employees and has 14 wafer fabrication plants. Yeo was also the former chairman of A*STAR and former special advisor for Economic Development in the Singapore Prime Minister’s Office.

The Industry Contribution Award will be presented to Lee for his work in advancing the competitiveness of the wafer fabrication industry in Singapore. Lee’s career in the Singapore semiconductor industry spans more than four decades, including positions at Texas Instruments, TECH and Micron. During his tenure at TECH and Micron, Lee was instrumental in growing their Singapore presence and maintaining Singapore’s competitiveness in the midst of competition from Korean and Taiwanese manufacturers. Lee also led the world’s first factory conversion from 200mm to 300mm technology while simultaneously maintaining production, and was instrumental into making Singapore into a base of Flash memory production that started in partnership with Intel.

"The contributions and accomplishments of both Yeo and Lee are well known within the Singapore and Southeast Asian semiconductor industry and these awards are a worthy recognition of their achievements on behalf of our industry," said Denny McGuirk, president and CEO of SEMI.

Terry Tsao, president of SEMI Southeast Asia added: "Yeo and Lee’s dedication to advancing the establishment and growth of the industry here has helped build Singapore into a globally recognized center of microelectronics innovation and manufacturing."

The award recipients were voted by the SEMI Singapore Regional Advisory Board (RAB), an advisory group of industry executives focused on advancing SEMI’s mission in Southeast Asia through the development and support of programs and initiatives designed to accelerate the growth and increase the visibility of the semiconductor industry in the region. The advisory board is led by newly elected executive directors including chairman KC Ang, senior vice president and general manager of GLOBALFOUNDRIES Singapore; vice-chairman Russell Tham, regional president, Applied Materials South East Asia and corporate vice president, Global Continuous Improvement, Applied Materials Inc.; and vice-chairman Jen Kwong Hwa, site director, Micron Semiconductor Asia.

"On behalf of SEMI and the industry, the SEMI Singapore RAB is proud to honor Yeo and Lee with these awards that acknowledge the key roles they have played in growing the Singapore semiconductor industry over the last two decades,” said KC Ang. “From a public and private sector perspective, their contributions have resulted in a robust semiconductor ecosystem in the region, where we continue to see this industry driving the global economic growth and now even enabling the explosive growth of the mobility markets that we are witnessing today."

The awards will be presented during two separate events held as part of SEMICON Singapore 2013. The Industry Achievement Award will be presented to Lee during the event opening ceremony on May 7 from 9:30am-10:00 a.m. at the Marina Bay Sands Expo and Convention Center, and the Lifetime Achievement Award will be presented to Yeo during the SEMI Singapore VIP Dinner, also on 7 May, at the Fullerton Hotel.

Rudolph Technologies, Inc., a provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, announced today that it has purchased selected assets, including a strong patent portfolio, relating to metrology capability from Tamar Technology, Newbury Park, Calif. The addition of Tamar’s advanced metrology technologies to Rudolph’s existing inspection and metrology systems will allow the company to address the emerging need for fast, precise three-dimensional (3D) measurement capabilities in the rapidly-growing advanced packaging market sector.

“The purchase of these assets adds new capabilities to our technology portfolio, which addresses an emerging need for 3D measurements to control copper pillar bumping in advanced packaging processes,” said Michael Jost, vice president and general manager of Rudolph’s Inspection Business Unit. “Tamar’s technology is already well-known and widely used. Integrating it into our NSX and F30 inspection and metrology platforms adds critical capability and value to an established and reliable tool set. Several customers brought this exclusive technology to our attention; and it was readily apparent that the acquisition of these assets would significantly enhance the breadth of our advanced packaging solutions. In addition, this purchase gives Rudolph a significant patent portfolio that we plan to fully leverage. The integration work is essentially complete and we expect to receive initial system orders in the coming months.”

Copper pillar bumping for flip-chips has been forecast to grow at a 35 percent CAGR from 2010 to 2018. While copper pillar bumping processes are the most significant immediate application, Tamar’s products are capable of critical measurements required in several packaging applications. For example, one application uses infrared light to measure TSV depth from the backside of the wafer, thus avoiding the limitations on via aspect ratio encountered by most frontside measurement approaches.

“We expect the addition of these unique and proprietary capabilities to positively influence both unit volume and margins while helping Rudolph to maintain our #1 market share position in this rapidly growing sector,” said Jost.

Terms of the transaction were not disclosed. However, the company noted that the asset purchase agreement includes an earn-out contingency that, if met, would bring the total transaction value to approximately $10 million. The company also noted that it expects the transaction to be accretive to earnings within the first 12 months.

Tamar Technology, based in Newbury Park, California, is a precision metrology company specializing in systems for the semiconductor, hard disk drive and medical device industries.  Rudolph provides a full-fab solution through its families of proprietary products that provide critical yield-enhancing information, enabling microelectronic device manufacturers to drive down the costs and time to market of their products.