Category Archives: Metrology

At the International Semiconductor Strategy Symposium (ISS Europe), the European semiconductor industry affirmed its ability to innovate. More than 170 top industry representatives agreed on a number of joint steps and strategic measures to strengthen their competitiveness and sustainability. The controversial question whether the best way to attack future challenges will be "More Moore" or "More than Moore," ended in an expected compromise, namely that the industry should pursuit both strategies concurrently, the participants of a panel expressed. Whilst the More than Moore sector is traditionally strong in Europe, going on with More Moore is important for two to three device makers in Europe and in particular for the European equipment suppliers which export 80% of their products.

In a global scale, the semiconductor industry is approaching the move to 450mm wafer processing technology – a step that promises to greatly boost the productivity of semiconductor manufacturers. However, since the investment to build a 450mm fab easily exceeds the 10 billion dollar mark, this move is regarded as risky and, for this reason, reserved to only the very largest enterprises. In the past, this perspective divided the European industry into two camps – the "More Moore" group that advocates taking on the 450mm challenge, and the "More than Moore" group which shunned this risky investment and preferred to rely on application-oriented differentiation instead.

At the event SEMI Europe, an industry association embracing enterprises that represent the entire value chain and organizer of the ISS Europe, set up a high-ranking panel discussion on options and choices of a single European semiconductor strategy. The panel proved that entrepreneurial spirit is well alive among Europe’s chipmakers, technology suppliers and researchers.

Time is ripe to close the ranks and take on the challenges, as the speakers in the panel pointed out. Judged on the basis of its expertise and abilities, the European semiconductor and equipment industry has remarkable strengths, the experts said unanimously.

"We have to think in European terms," said Luc Van den hove, CEO of the Belgian research center Imec. "Talking in a common voice allows the European Commission to act and support this industry".

Jean-Marc Chery, Chief Manufacturing & Technology Officer of chipmaker STMicroelectronics, reminded that a holistic approach is necessary. "We have to push the full value chain cooperatively," he said.

The panel participants recognized that the European semiconductor industry possesses the necessary expertise. So far, the willingness to jointly face these challenges has been affected adversely by the macroeconomic environment and the Euro crisis, which discouraged far-reaching strategic decisions. The members of the European Commission that recently signalized understanding the needs of the semiconductor industry’s vital role for the high-tech location Europe, certainly contributed to the optimism in the industry.

"We have all the knowledge, the materials and the equipment," said Rob Hartman, Director Strategic Program for leading equipment manufacturer ASML, during the panel. "Let’s do it in the EU."

European Commissioner Neelie Kroes’ idea of creating an "Airbus for chips," a European initiative for the semiconductor industry comparable to the initiative that once led to the launch of the Airbus in the aviation industry, was strongly hailed by the panel.

"An Airbus for chips could be a very powerful tool," Van der hove said. "It does not need to be a single company, it also can be a framework of companies," added Laurent Malier, CEO of French research centre CEA-LETI.

The main concern of the industry is the slow decision process of the European institutions due to a complex political approval process inside of the European Union, the participants agreed. This industry is moving fast and so the decisions have to be taken fast, too. The strong Euro and the lack of qualified labor are further regarded as potential stumbling blocks for the technological progress and the business competitiveness.

At the panel the European Commission signalized its support for the industry as well.

“If policy instruments would be combined on EU and national levels, a critical mass of support for R&D for both More than Moore and More Moore could be achieved,” said Khalil Rouhana, Director Components & Systems at the European Commission.

KLA-Tencor Corporation (NASDAQ: KLAC) announced its SpectraShape 9000 optical critical dimension (CD) metrology system and BDR300 backside defect inspection and review module at the SPIE Advanced Lithography conference this week. The SpectraShape 9000 is a new metrology system capable of monitoring the shapes of three-dimensional transistors, memory cells and other key structures that enable high-performance memory and microprocessor chips. The BDR300 inspects and reviews the back side of the wafer for defects that can cause patterning problems on the wafer’s front side. The two new systems are designed to enable volume production of integrated circuits at sub-20nm design rules.

“In this era of highly extended 193nm immersion lithography, our customers are innovating on several fronts to deal with process tolerances in lithography and etch that have become remarkably tight,” said Brian Trafas, Ph.D., chief marketing officer at KLA-Tencor. “The two products we have launched today tackle two key process control issues in this area: scanner focus-related defects and failure or underperformance of finFETs, vertically stacked NANDs, and other three-dimensional structures, caused by small deviations in shape. The BDR300 and SpectraShape 9000 are designed to help our customers navigate the monumental challenges they are facing today in lithography and etch.”

The new SpectraShape 9000 introduces a laser-driven plasma light source and several other significant advances that enable dimensional metrology capability for a broad range of materials and structures. The SpectraShape 9000 features higher sensitivity and throughput than its predecessor in order to accommodate the industry’s need for tighter process control at sub-20nm nodes—a need to measure more sites per wafer on an increasing number of layers. It also supports innovative metrology targets designed for multiple-patterning lithography.

The new BDR300 back-side inspection and review module for the CIRCL cluster tool features a dramatic improvement in defect sensitivity over that of its predecessor, allowing fabs to find and classify sub-micron back-side defects, which can agglomerate and affect yield at advanced nodes. The CIRCL cluster is now available as a stand-alone back-side inspection and review system, a configuration designed to support an increasing industry requirement to inspect the back sides of wafers before wafers enter the scanner. Clean wafer back sides reduce the probability of contaminating the scanner chuck and affecting subsequent product.

Multiple SpectraShape 9000 shape metrology systems have been installed at leading logic and memory chip manufacturers, where they are replacing existing CD/shape metrology tools for new technology development and ramp or fulfilling requirements for additional metrology capacity. The first CIRCL tools containing the BDR300 module have also been installed and are being used for proactive scanner monitoring as well as traditional after-develop defect inspection. To maintain the high performance and productivity demanded by leading-edge production, the SpectraShape and CIRCL tools are backed by KLA-Tencor’s global, comprehensive service network.

SEMATECH announced today that Dr. Bryan J. Rice, on assignment from Intel Corporation as SEMATECH’s director of Strategic Initiatives, was inducted as a 2013 Fellow by SPIE, the international society for optics and photonics, during its annual SPIE Advanced Lithography conferences in San Francisco, CA.

Each year, SPIE Fellows are elected based on their significant scientific and technical contributions in optics, photonics, and imaging. Rice received recognition for his achievements in technical and strategic leadership in the development of lithography. He was one of 69 Fellows elected to the Society this year.

“SPIE’s election of Bryan to Fellow demonstrates the significance of his achievements and is a testament to his leadership in the lithography community,” said Dan Armbrust, SEMATECH president and CEO.

Before being named SEMATECH’s director of Strategic Initiatives in 2011, Rice served as director of SEMATECH’s Lithography program for three years. Under his leadership, SEMATECH partnered with the College of Nanoscale Science and Engineering (CNSE) to launch the Resist and Materials Development Center, an EUV imaging resource, and the EUV Mask Infrastructure (EMI) Partnership which focuses on critical EUV tool development activities.

Rice also led SEMATECH’s high-index immersion research in the search for high-refractive index lens and immersion fluid materials, and helped form the group’s double-exposure program, which focused on the exploration of novel materials for the litho-litho etch patterning approach.

Prior to his assignment at SEMATECH, Rice worked with lithography tool manufacturers and EUV source suppliers in Intel’s Components Research Division, to remove roadblocks to the development of EUV lithography technology.

Rice holds a doctorate in nuclear physics from Duke University as well as a bachelor’s degree in physics and a master’s degree in computer science from the Georgia Institute of Technology. He holds 16 U.S. patents and is the author of numerous publications on lithography and metrology. 

As an active member of SPIE, Rice has authored and co-authored more than 30 papers, presented numerous papers and posters on current lithography issues, and contributed to selected chapters of books published by SPIE Press.

SPIE is dedicated to advancing scientific research and engineering applications of optical, photonic, imaging and optoelectronic technologies through its meetings, education programs and publications.

Luminescent Technologies Inc., a provider of computational metrology and inspection solutions for the global semiconductor manufacturing industry, and Dai Nippon Printing Company, Ltd. announced today the successful completion of the first phase of a three-year joint development program for computational metrology and inspection using Luminescent’s Automated Image Processing Hub (LAIPH) platform.  The goals of the collaboration are to dramatically reduce photomask defect review and analysis cycle time while simultaneously improving overall mask quality. The first phase resulted in the successful implementation of LAIPH Aerial Image Analyzer (AIA) software in DNP’s Kami-Fukuoka photomask production plant.

“Today’s advanced design technologies for semiconductors require sophisticated software to enable quick and accurate disposition of reticle defects for state-of-the-art lithography tools,” said Mr. Hideyoshi Takamizawa, deputy general manager of Photomask Technical Department, 1st Production Division, Fine Electronics Business Operationsof DNP.  “We are impressed with results obtained from Luminescent’s AIA software and look forward to extending the use of the LAIPH platform for further applications.”

"We are proud DNP has chosen Luminescent to assist with their world class performance in mask cycle time and quality," added Dr. Linyong (Leo) Pang, Sr. Vice President of Luminescent.  “Our contribution to DNP’s manufacturing success is further proof of the power of computational methods in defect metrology and inspection.”

Aerial Image Analyzer (AIA) is one of the applications on Luminescent’s LAIPH platform to address the growing challenges of inspection in advanced mask shops and wafer fabs. It provides precise quantitative analysis of defect images captured by Carl Zeiss SMT’s Aerial Image Measurement System (AIMSTM) and Applied Materials AeraTM series mask inspection systems. AIA automatically dispositions the defect based on its simulated wafer contour, CD, and location. It improves the equipment’s utilization while offering 100X faster, more comprehensive and consistent analysis than operator’s manual measurements.

Lithography scientists, engineers, and developers — long accustomed to working years ahead in order to meet industry needs — face keen challenges, with meeting user expectations, enabling new capabilities, and controlling costs at the top of the list. SPIE Advanced Lithography, the annual forum for discussions on meeting the challenges in developing state-of-the-art lithographic tools, resists, metrology, materials characterization, and design and process integration, will bring the community together in San Jose, California, to address those issues. The event will run February 24-28 at the San Jose Convention Center and San Jose Marriott Hotel.

Symposium chair Harry Levinson of GLOBALFOUNDRIES said organizers anticipate interest in several topics in particular, including:

  • Designing with multi-patterning and directed self-assembly (DSA): beyond SEMs toward real chips
  • Line edge roughness: clearly a concern of many and the focus of a session in the conference on Advanced Etch Technology for Nanopatterning.
  • Resist limits: secondary electrons, tradeoffs among resolution, line-edge roughness and exposure speed.

However, Levinson noted, “To be honest, the real buzz usually comes from something unexpected, which is probably one of the best reasons for attending Advanced Lithography!”

With the presence of leaders from companies such as Intel, Samsung, ASML, Taiwan Semiconductor Manufacturing Corp., and other companies that have announced large investment strategies in new technology, “unexpected” topics might include R&D toward photonics integrated circuits versus silicon photonics, retooling for 450mm wafers, or power-source issues in EUV (extreme ultraviolet) tools.

In addition to featured speakers and more than 560 technical talks, the event will include panel discussions on disruptive and emerging technologies, full- and half-day short courses on lithography topics, interactive poster paper receptions, and a 60-company exhibition showcasing many of the industry’s top semiconductor suppliers, integrators, and manufacturers. The exhibition will run Tuesday and Wednesday, February 27 and 28.

Plenary presentations from leaders in the lithography industry include:

  • Bill Siegle, Independent Consultant and ASML Advisory Board Member: “Contact printing to EUV: lessons learned from the art of lithography”
  • Howard Ko, Senior VP and General Manager, Synopsys Silicon Engineering Group: “The evolution of EDA alongside rapid silicon technology innovation”
  • Charles Szmanda, The Patent Practice of Szmanda & Shelnut, LLC: “The new U.S. patent law: what you need to know and how it will affect your strategy.”
  • Technical talks are organized into seven conferences:
  • Alternative Lithographic Technologies
  • Extreme Ultraviolet Lithography
  • Metrology, Inspection, and Process Control for Microlithography
  • Advances in Resist Materials and Processing Technology
  • Optical Microlithography
  • Design for Manufacturability through Design-Process Integration
  • Advanced Etch Technology for Nanopatterning

Accepted papers will be published in the SPIE Digital Library as soon as approved after the meeting, and in print volumes and digital collections.

Experts present advances in lithography at SPIE 2013SEMATECH experts will present research and development results on extreme ultraviolet (EUV) manufacturability and extendibility, alternative lithography, and related areas of metrology at the SPIE Advanced Lithography 2013 conferences taking place February 25-28 at the San Jose Convention Center and Marriott in San Jose, CA.

“We are enthusiastic about sharing our progress on some of the most critical aspects of the development of EUV infrastructure,” said Stefan Wurm, director of lithography at SEMATECH. “SEMATECH lithographers will recount achievements in multiple areas of EUV to further enable EUVL pilot line readiness and advance EUV extendibility.”

SEMATECH engineers will report progress on EUV mask infrastructure, manufacturability, extendibility and metrology, and will showcase some of their findings in over 30 papers and posters demonstrating breakthrough results in exposure tool capability, resist advances, defect-related inspection, e-beam and nanoimprint. 

More importantly, the results presented will be instrumental in driving timely creation of the remaining infrastructure required to bring EUV to production. In one area of investigation, technologists from SEMATECH’s Mask Blank Development Center will report progress with its multilayer deposition process, including recent defect printability results from an NXE3100 tool with comparison of the imaging to various simulation modeling approaches.

Other SEMATECH papers will showcase advances in metrology techniques, photoresist shrinkage, nanopolishing, scatterometry, through-silicon via (TSV) reveal, transmission electron microscopy (TEM) tomography, critical dimension atomic force microscopy (CD-AFM), critical dimension X-ray scattering (CD-SAXS)—a potential metrology technique for FinFET and 3D memory structures—and a through-focus scanning optical microscopy (TSOM) technique being explored for future defect inspection or to enable high-volume manufacturing of high-aspect ratio features.

Additionally, technologists will present a “big picture” CD metrology gaps analysis, which interrelates the combined results from years of SEMATECH CD metrology studies to summarize the outlook for various tool technologies for different applications.

“We will be showcasing impressive metrology advances achieved through collaborative research, as well as revealing new defect characterization results for EUV mask blanks that form the basis of the technology for SEMATECH’s new Nanodefect Center,” said Michael Lercel, senior director of nanodefectivity and metrology at SEMATECH.

Among the global semiconductor community’s leading gatherings, the SPIE conference series attracts thousands of specialists in various aspects of lithography and related metrology, two of the most challenging areas of advanced microchip production.

wafer revenues decreaseWorldwide silicon wafer revenues declined by 12 percent in 2012 compared to 2011, according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry. Worldwide silicon wafer area shipments declined 0.1 percent in 2012 when compared to 2011 area shipments.

In 2012, silicon wafer area shipments totaled 9,031 million square inches (MSI), down from the 9,043 million square inches shipped during 2011. Revenues totaled $8.7 billion down from $9.9 billion posted in 2011.

"Much like semiconductor unit shipments, semiconductor silicon shipments started out the year strong; however, shipments weakened during the second half of the year,” said Byungseop Hong, chairman of SEMI SMG and director of Global Marketing at LG Siltron. “Despite challenges in the market, 300 mm volume shipments reached record levels.”

Read more: When will the semiconductor industry recover?

Annual Silicon* Industry Trends

 

2007

2008

2009

2010

2011

2012

Area Shipments (MSI)

8,661

8,137

6,707

9,370

9,043

9,031

Revenues ($B)

12.1

11.4

6.7

9.7

9.9

8.7

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or "chips" are fabricated.

This report was compiled and released by the the Silicon Manufacturers Group, which acts as an independent special interest group within the SEMI association. The group’s purpose is to facilitate collective efforts on issues related to the silicon industry, including the development of market information and statistics about the silicon industry and the semiconductor market.

SEMI is the global industry association with over 2,000 members, serving the nano- and microelectronics manufacturing supply chains. 

In the second of two installments, Linx Consulting reports a steady growth in semiconductor production, as released in The Econometric Semiconductor Forecast.  The first installment focused on regional developments that will affect semiconductor industry growth.

Semiconductor production to see steady growth after 2013

The weakness in economic growth spills into end products containing semiconductors in 2012 and early 2013.  Our model relating final demands to aggregate semiconductor production (measured by SEMI’s Million Square Inches of silicon processed, MSI) suggests weak demand was anticipated in 2012, and that by early 2013, enough improvement in end markets occurs to push growth up at a modest pace that averages slightly less than 6% for the full year.   By 2014, growth should recover to long-term potential growth for MSI of approximately 7%/year.

 

Figure 1: Aggregate semiconductor production from 1955 to present, with forecast to 2015.

Key assumptions driving this forecast include some solution to the fiscal cliff dilemma that permits US consumers and businesses to begin to return to more normal conditions.  Removing uncertainty drives a modest expansion US spending on technology goods of around 2.3%, up from the anemic 0.8% growth anticipated for 2012.  Most of that growth will occur in the second half of 2013, as it will take some time for businesses to analyze the new policy environment and then implement investment plans.  Inventory-shipment ratios for technology goods, which are spiking in the last half of 2012, are assumed to recede on a steady pace to more typical levels through 2013.  If shipments in IT goods do not develop as expected, the quarterly pattern above would most likely show a steeper decline in 2012Q4 and a further decline in 2013Q1, followed by strong gains in Q2 or Q3.

 

Figure 2: The difference between Segment Demand and Total Silicon Area (includes test and monitor wafers).

Strongest growth will remain in flash memories and logic devices

The overall picture of MSI growth breaks down into the expected performance of device segments and technology nodes.  Despite the shift to consumer electronics and mobile platforms, we expect growth to be concentrated in CMOS products with a continuing slowing of unit growth and analog and discrete devices.  Strongest growth will remain with flash memories, and advanced foundry logic devices targeted at tablets and phones.

In contrast with advanced memory and logic processing, approximately 56% of the market continues to be produced at design dimensions in excess of 100 nm on wafer sizes at 200 mm or smaller.  This market segment is extremely sensitive to economic volatility and has slowed significantly in the last four years.  Manufacturers of these devices are often capital constrained and extremely cost sensitive, leading to little process innovation and limited capacity expansion.

More silicon area at 32 nm produced in 2012 than any other node

On a technology basis, despite tight capital budgets, the introduction of devices at 28 and 22nm half pitches continues apace, and significant process challenges are driving increased complexity and resultant challenges in patterning, cleaning, CMP and deposition throughout the device manufacturing process.  2012 is forecast to have produced more silicon area at 32nm than any other node, and the introduction of low 20nm half pitches and flash has continued to grow startling rates. 

In total devices manufactured at 65nm and below continued to show strong area growth in 2012 of 14%, with devices at 90nm and above largely offsetting declines from 2011 with 8% growth in 2012, but flat performance on average.

 

 

In the first of two installments, we examine the global issues facing the semiconductor industry, as released by Linx Consulting in The Econometric Semiconductor Forecast. Part two predicts that semiconductor growth should recover by 2014.

United States’ economic outlook 

The January 1st “fiscal cliff” deadline in the US dominates the near term outlook for the world economy.  ANY settlement will stabilize the situation, but any politically acceptable near term agreement in Washington will not be enough to truly begin to solve the longer-term problems. The political dynamics are not yet in place to lead to a long-term solution to debt restructuring or reducing excessive growth in entitlements. The first fiscal cliff compromise, which includes higher taxes on the wealthier income-earners, elimination of the 2% social security tax reduction, and a permanent fix to the alternative minimum tax levels, gave clarity to consumers on their tax situations. Discretionary and entitlement government spending controls or cuts to reduce government debt burdens were deferred, leaving key questions about policy to later negotiations. That extension of uncertainty will dampen investment spending and government purchases of equipment at least into the first half of 2013. Economic growth will stagnate in the beginning of the year, and then bounce briefly when the new policy environment becomes clear.  Post bounce, the longer term issues will begin to re-surface, and economic growth should settle back into a sluggish trend that lags potential output. This modest growth will be slow to lower unemployment.  Without a strong labor market, businesses will plan for very modest gains in consumer spending, relatively low inflation, and no significant change in interest rates.

Europe’s economic outlook

Most economies are in mild recession, as central governments raise taxes and/or cut spending in attempt to reduce debt. Austerity measures, coupled with potential national bankruptcies in Greece, and recessions in Spain and Italy which will likely extend into early 2014, produce severe stress on euro currency. For the euro to survive, Germany and the most troubled countries will need to compromise national needs to develop an approach that will satisfy financial markets.  France introduces a growing uncertainty to the European outlook. It continues to head in the opposite direction from most countries, expanding the central government’s involvement in the economy, ignoring debt growth, and pushing income redistribution measures which could stifle growth. While the Eurozone should survive intact, the political process will likely keep markets uncertain and most countries’ fiscal budgets austere.  Overall economic activity measured by real GDP most likely will contract slightly in 2013.

Asia’s economic outlook

With key developed world markets in recession or growing weakly, Asian economies will have difficulty producing strong expansions in 2013. With the exception of Japan, however, rates of growth are likely to improve from 2012. Led by China, which moved a bit too aggressively to cool its economy in 2012, policies have become slightly more expansive across the region and should produce slightly stronger real growth rates. Growth will come more from internal regional development than export-led growth.

Risks affecting the semiconductor industry 

Negative risks dominate discussions among serious analysts. In Europe, a financial calamity from either a banking system failure or the breakup of the Eurozone would produce a severe recession with global implications. In the US, an imbalanced solution to the fiscal cliff could stifle growth and tumble the economy into a brief recession. Emerging commodity-focused or dependent economies would be negatively impacted by a weaker Asian expansion. Positive risks, which get very little discussion in popular press these days, include a much sharper boost in the US following a settlement of the “fiscal cliff” dilemma, and a slowly improving European situation (most likely led by Germany or a group of northern European economies) that stabilizes more rapidly the fiscal situation in Europe.  A number of US forecasters surveyed by the National Association for Business Economics on December 17th expect US growth to rebound sharply and exceed 3 ½% by the end of 2013 as the uncertainty “discount” is removed from markets. While an equal number expect growth to stagnate around 1%, the upside should be at least acknowledged as a possible upside risk to the current consensus.

A new econometric semiconductor industry forecast predicts semiconductor wafer area production to grow slightly less than 6% in 2013, according to Linx Consulting.

Using a macroeconomic forecasting tool that incorporates measures of economic uncertainty, global economic shocks, and regional volatility, the forecasting service, called The Econometric Semiconductor Forecast, predicts a slow first quarter in 2013 will be followed by a strong second quarter with moderate growth in the second half of the year. This modest growth forecast is believed to be demand-driven, since inventory levels have not shown a significant increase in 2012.

The Econometric Semiconductor Forecast is the first to use global GDP macroeconomic models to provide semiconductor industry forecasts at a quarterly frequency with monthly updates, allowing forecast recipients to plan for short-term fluctuations in the volatile semiconductor industry.

“An unstable global economy leads to wide variations in economic forecasts, making it difficult to develop meaningful demand-side forecasts,” said Mark Thirsk, managing partner of Linx Consulting. “Our econometric forecast model allows us to develop more accurate forecasts on a monthly and quarterly basis, which are vital for operations planning and business forecasting in the semiconductor supply chain.”

Based on a demand-driven equation that captures >98% of the long run variation in semiconductors, the economic forecast model used by Linx Consulting includes global real GDP growth from consensus forecasts, US consumer and business spending on technology goods, inventory-shipments ratio, computer and electronics, and financial crisis shock indicator to capture panic behavior in the latest cycle.

Headwinds in the Global Economy

Uncertainty surrounding government policies and ongoing fallout from the financial crisis combine to restrain growth in 2013. Protracted periods of uncertainty followed financial crises in the past, accompanied by prolonged subdued growth rates as major economic policies changed and debt restructuring dampened investment and spending.  Few of today’s policymakers or business leaders have experience dealing with this type of an environment. That lack of experience adds to the uncertainty in the current outlook, as it tends to increase cautious economic behavior by consumers and businesses. In 2013, policies should become a bit more settled in the first half of the year, improving confidence somewhat.  Global economic growth is unlikely to recover to its longer-term potential until after 2013 as fundamental structural imbalances will improve slowly at best.

In the face of these headwinds, the more than 250 forecasters surveyed in the December 2012 Consensus Forecasts produced a consensus subdued, below-trend global growth of 2.6% in 2013.  This is a slight improvement over the 2.5% now expected for 2012, but less than the 3.1% achieved in 2011 and below the long-term potential real global growth rate of around 3.5%.  While the consensus averages to 2.6% for 2013, there is a relatively wide range in individual forecasts, reflecting the uncertainty in the outlook.  Individual outlooks depend most on how forecasters see developments in the US and Eurozone.

Read more from The Econometric Semiconductor Forecast: Regional developments to affect growth of semiconductor industry

The forecasting service will provide subscribers with monthly updates of quarterly forecasts of total semiconductor production in Million Square Inches of silicon processed, as well as segmentation by device, including DRAM, flash, MPU, ASIC, analog and discrete.