Category Archives: Metrology

Overlay error is the offset in alignment between pattern at one step of a semiconductor process and pattern at the next step. Traditionally overlay error has referred to successive device layers, but in the case of double-patterning lithography, overlay error may stem from interwoven patterns at the same layer. Regardless, controlling overlay error is one of the most difficult issues that lithography engineers face in this era of shrinking design rules and complex, advanced lithography techniques. Because overlay error can affect yield, device performance and reliability, it must be measured precisely, and all sources of systematic overlay error must be discovered and addressed. These may include mask pattern placement error, deviations from wafer planarity, scanner nonlinearities and process variation.

In most cases, overlay error is measured optically by capturing an image of a specially designed alignment mark called an overlay target. Half of the overlay target is printed during the first process step, and the other half of it is printed during the second process step.

 

A standard overlay target is printed in two steps,  indicated in red and blue, and structured to measure the errors in x and y.

An overlay metrology tool captures the image and quantifies the alignment between the first and second parts of the target. The result is reported as a vector quantity, having a magnitude and direction corresponding to the x and y offsets. The procedure is repeated for each of the overlay targets on the wafer. Overlay error maps are comprised of a circular field of tiny vectors, representing the overlay error across the wafer. These maps are used to adjust the scanner or to uncover issues with the mask pattern, the wafer shape or the process. Overlay error maps are also used to disposition wafers.

Flexible, robust multi-layer target allows simultaneous measurement of overlay error within the same layer and between layers.

A recent development in the area of overlay measurement is extension of measurement capability to new layers and new materials (see above). When overlay error between layers is measured, the optical properties of the top layer are critical to the quality of the data. The metrology tool needs to be able to send photons through the top layer to detect the pattern underneath, and the quality of the image of the buried pattern is critical to the quality of the overall measurement. Because semiconductor processes use a variety of materials, and the optical absorption of a given material generally varies with wavelength, the well-equipped metrology system can select from a variety of wavelengths to achieve sufficient image quality for the buried pattern to enable an accurate, repeatable measurement. The alternative—introducing an extra process step to etch a “window” in the top layer before patterning it—adds significant cycle time and may degrade the underlying pattern. Cycle time pressures are ever-present and well known. Furthermore, when the entire overlay error budget is limited to a small number of nanometers, lithographers cannot afford to allot a large portion of the budget to uncertainty in the output of the overlay metrology tool.

Examples of particularly challenging classes of materials are those used to build 3D transistors, and hard mask materials used during litho-etch-litho-etch lithography. Hard mask materials are opaque to visible light, and their optical properties may fluctuate with composition and even with annealing temperature.  The latest overlay metrology systems can provide an appropriate wavelength that penetrates the top layer, making overlay metrology feasible without additional process steps.

Another new development in the field of overlay metrology is the use of multi-layer overlay targets. New target designs now allow a lithography engineer to measure within-layer overlay and between-layer overlay using one target. These innovative targets are small enough to be inserted into the die without consuming an unfeasible amount of valuable real estate. Their designs are flexible and robust, allowing adjustments for specific process and layer requirements. They are compatible with various pitch-splitting and double-patterning schemes. Most importantly, the new multi-layer targets allow lithographers to measure within- and between-layer overlay error with one image and, at the same time, reduce systematic errors that could degrade the measurement if separate targets had been used.

Overlay metrology remains one of the most challenging issues that lithographers currently face. Innovations in overlay metrology tool and target design must continue, to enable our industry to make smaller, faster, lower power, more affordable chips.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Amir Widmann is a senior director in the Optical Metrology division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

September 14, 2012 – Now that the initial dust has settled after Apple’s debut of the new iPhone 5, industry watchers are taking a tally of which semiconductor suppliers stand to gain in the newest must-have smartphone.

Below is a quick tally of the key features and which suppliers likely benefit. (As usual teardown firms prepare their knives, TechInsights has cooked up a preliminary calculation of the iPhone 5’s bill-of-materials.)

— Dual-band WiFi. 4G LTE connectivity, which dramatically accelerates speeds vs. previous models This technology (similar to what the Kindle Fire now uses) increases test times at the module test level, which is a sweetspot for TER’s Litepoint business, points out Credit Suisse’s Satya Kumar. TER already indicated that this unit already saw a boost in 2Q12 attributable to both the iPhone 5 and Kindle Fire. Going forward, this likely means other smartphone vendors will adopt this technology, and eventually 802.11ac next year — both of which "are particularly test-intensive" and thus positives for TER, he notes.

Barclay’s CJ Muse, meanwhile, calls out Qualcomm’s 28nm 4G/LTE baseband and Broadcom’s 40nm WiFi combo chip.

— Upgrade to the A6 logic chip. Apple’s projections of nearly 300m iOS units for 2013 is such a sheer volume that "a seemingly benign metric like SoC die size for iPhone 5 [which is 95 mm2, 22% smaller than the A5] is actually meaningful enough to move the worldwide capex for semiconductor industry by 5% for every 10-sqmm variation," Kumar observes. He factors in 32nm capital intensity, Apple’s unit growth and die size, and determines that Apple’s chip partner Samsung could keep its logic capex spending flat in 2013 just to keep up with manufacturing the new A6 chips. (Apple also is using a dual-core ARM-A15 cores to run at 2× speed for the CPU, which Apple believes is better than Intel’s SoC core roadmap.

Barclays’ Muse points out that anything that means more 28/20nm chips means more litho-intensive processing, which "should benefit ASML disproportionally."

— More DRAM memory content, no extra NAND. DRAM content in the iPhone 5 is doubled to 1GB; Kumar actually had expected an increase in NAND content in the iPhone 5, but apparently Apple’s keeping it steady at 16-32-64GB, which underscores "the cautious commentary on wafer starts and capex from NAND companies," he writes. Among chip tool suppliers possibly affected, KLAC has higher exposure to logic/foundry and LRCX is more heavy into NAND than peers, but the extra DRAM content in the iPhone 5 likely makes up for that. Thus, the extra DRAM and no extra NAND means it’s "a wash" for suppliers.

— Upgraded to in-cell display technology. Putting touch sensors inside the panel, vs. adding a separate touch layer on top of the LCD panel, helps reduce the display’s thickness, which means the phone can be thinner or more features can be improved such as a bigger longer-life battery, explains Vinita Jakhanwal, director for small and medium displays at IHS iSuppli. LG, Sharp, and Japan Display are all potential suppliers of the in-cell display — if they can keep up with demand.

— Audio, antenna upgrades mean more sapphire. Sterne Agee’s Andrew Huang points to Cirrus Logic as a big beneficiary of a new "wideband audio" feature that can fill up more frequency spectrum to improve voice sound quality. Magnachip Semiconductor gets extra business tied to Cirrus Logic, points out Barclays’ Muse. Another winner is Corning, whose Gorilla Glass 2 is likely used as the cover glass for the iPhone 5, he says.

Huang also points out the iPhone 5’s increased used of sapphire, both as a camera lens cover and as the substrate (silicon-on-sapphire) for the antenna switch to automatically switch antenna connections, is a trend worth watching: "Within the next 12-18 months, we believe sapphire content per mobile phones could increase," he writes, suggesting eventually it might supplant the cover glass material. The silicon-on-sapphire trend likely benefits Rubicon (SoS wafer sapphire substrate supplier) and Peregrine Semiconductor (SoS switch component supplier). [Corrected 9/20: Soitec makes the actual SoS wafers for Peregrine.] "Our checks indicate that Rubicon supplies ~30-40% of the market for SoS wafers," he writes, and although a number of other ingot makers are currently getting qualified, "it is much more difficult to core, slice and polish SoS wafers, which suggests margins for SoS wafers are comparable, maybe even lower than those of LED wafers." Muse adds that Magnachip gets a foundry-biz boost from Peregrine, too.

September 13, 2012 – Step aside, scatterometry and AFMs — there’s a new hybrid technique that’s both more precise and less expensive to measure features on a chip.

The National Institute of Standards and Technology (NIST) says it’s combined scanning techniques and statistical data "using a Bayesian approach." They created a library of simulated data based on typical chip feature dimensions, to be compared with actual measurements made with AFM, scatterometry and other means. Comparing that analysis with actual measurements to extract valid measurement values can be costly — until one applies a little Bayesian statistical analysis.

"In essence, if you’ve got a really small uncertainty in your AFM measurement but a big one in your optical measurements, the final uncertainty will end up even smaller than either of them," explains NIST scientist Richard Silver. Adding a few other measured values to the library model reduced uncertainty in some of the measurements — by up to a factor of three in some cases, NIST claims.

This approach, the scientists say, will be a key part of measuring complex 3D transistor structures that are quickly approaching the 16nm node and beyond. In fact, Silver reveals that "IBM and GlobalFoundries have already begun developing the technique since we first described it at a 2009 conference, and they are improving their measurements using this hybrid approach."

The research is described in the Sept. 1 issue of the journal Applied Optics.

A silicon pillar, measuring <100nm along any of its sides, is the type
of semiconductor feature in the crosshairs of a new NIST hybrid metrology
technique to reduce measurement uncertainties. (Credit: NIST)

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September 12, 2012 – Global demand for semiconductor manufacturing equipment slipped -4% in 2Q12 with softness in just about every region — except in Taiwan, which stepped on the pedal during the quarter, according to updated data from SEMI and SEAJ.

Worldwide semiconductor manufacturing equipment totaled $10.34B in 2Q12, down -4% from the previous quarter and about -13% from a year ago. Bookings were also down -4% sequentially, and were off by -10% year-on-year, to $9.70B. Note that these numbers include upwardly revised billings for North America, adding about $120M.

SEMI’s most recent predictions issued earlier this summer at SEMICON West indicated overall chip equipment demand would slip -2.6% in 2012 to $43.53B — and only that slight because the two biggest end-user regions, Korea ($11.48B, +32%) and Taiwan ($9.26B, +8.6%), are still pushing forward. All other regions are expected to reduce their equipment spending by – 15% to -29%. Observers at SEMICON West issued alarms for weak demand in 3Q12 but picking up some in 4Q12.

The latest numbers for 2Q12 support that scenario, at least partially. Taiwan’s demand for chip tools soared 83% in 2Q12 to $3.25B, leapfrogging the region back to the No.1 spot. Korea, meanwhile, slipped -22% Q/Q to $2.59B, a growth-rate decline roughly in line with all the other regions which are expected to be sluggish this year.

* North America was revised up, from 2.16
Figures may not add due to rounding.
(Source: SEMI/SEAJ)

2012 stall could pave the way for a record-breaking 2013

by Christian Gregor Dieseldorff, SEMI Industry Research & Statistics

September 7, 2012 — Consumer and business sentiment has become more important than ever before in the semiconductor industry. As we near the end of the third quarter in 2012, pessimism about the economy prevails given the challenging financial situation in the US, a slowing Chinese economy, and the on-going European debt crisis.

At the beginning of 2012, the outlook for semiconductor revenue was more optimistic, with predicted average growth of about 4 to 6 percent. The macroeconomic situation inspired caution and semiconductor revenue outlook changed to an outlook of flat to 2 percent for this year, with various key companies announcing changes in their revenue outlook. For example, in July, Intel cut its 2012 sales growth target to US$ 55.6-58.7 billion, up 3 to 5 percent from 2011, though Intel expects a stronger second half of 2012. TSMC cut its revenue growth rate by about 1 to 2 percent, expecting a slowdown in 4Q12 and into 1Q13. In July, STMicroelectronics announced it will cut capex for 2012 by 25 percent because of a lower outlook.

Meanwhile, struggling Japanese MCU and Analog/Power-maker Renesas considers options to stay in business, such as consolidating business units or pursuing a fab-lite strategy. Fujitsu announced it will pursue a fab-lite strategy, and recently announced the closure of one assembly and test facility and the transfer of ownership of two other facilities to J-Devices Corp. Also since mid-2012, a number of companies have announced more layoffs — including Siltronic AG, Nokia, Cisco, ON Semi, Google’s Motorola Mobility and Rambus.

2013: Another golden year?

While various industry segments appear to be tapping the brakes, others are revving their engines, hoping for an improved 2013. Increased demand for mobile devices, such as new smartphones, ultraportable PCs, and tablets may push semiconductor revenue higher by 10 percent, making 2013 another golden year.

Semiconductor revenue and capex rise and fall together, such that fab equipment spending generally trends along a similar path.

Frontend fab equipment spending, by product types.
(Source: SEMI World Fab Forecast Reports, August 2012)

In terms of fab equipment spending, 2007 and 2011 were golden years. Although spending in 2012 will decline, it may still turn out to be the third largest spending year on record for overall fab equipment spending.

SEMI’s fab database shows about 200 facilities equipping (including Discrete and LED fabs), suggesting that 2013 has the potential to be another golden year — perhaps an all-time record — with 17 percent growth, almost $43 billion.

Frontend fab equipment spending. (Source: SEMI World Fab Forecast Reports, August 2012)

Key drivers for fab equipment spending in 2012 are the foundries, led by TSMC, Globalfoundries, and UMC with over $10 billion combined spending. Their dominance continues in 2013 with about another $10 billion in spending.

Frontend fab equipment spending by product types, showing largest spending types.
(Source: SEMI World Fab Forecast Reports, August 2012)

Examining fab equipment spending by product type, the DRAM sector is still struggling with declining average selling prices. The industry lost German maker Qimonda in 2009, Powerchip exited DRAM in 2011, and ProMOS is struggling. In order to avoid further ASP declines, DRAM makers ceased investments in new capacity and those who could afford it focused investment in new technologies and upgrading existing fabs. After the bankruptcy of Elpida, at the beginning of 2012, global capital expenditure for DRAM declined to very low levels. This is not expected to change in 2013.

Flash investments also slowed in 2012. For example, at the beginning of 2012, Sandisk announced a pause in Fab 5 capacity expansion. At the end of July, Toshiba announced it will cut its NAND production by 30 percent. However, SEMI data indicates that Flash investments will pick up again in 2013, with big spenders Samsung (mainly Line 16), SK Hynix, Flash Alliance, and Micron.

Samsung turns attention towards System LSI by converting existing Memory fabs into System LSI and building new ones. Spending on a grand scale, Samsung is predicted to pour over $5 billion in 2012 and over $6 billion in 2013, all into this product type.

Although more fab projects have begun than estimated last year, the overall number of fab construction projects has declined year-over-year. Looking at how this affects investments, in 2012 investments for construction projects are expected to decline by 4.4 percent (from about $6.4 billion to $6.1 billion). In 2013, another 10 percent drop will bring fab construction spending to about $5.5 billion.

Foundries perform much better than other industry segments in terms of installed capacity growth. Foundries are even more necessary given industry consolidation and as more IDMs change to a fab-lite or fabless business model. Examining installed capacity by product type, Flash will overtake DRAM in 2012.

Cutbacks in Flash production in 2012 have improved average selling prices so companies will likely increase Flash capacity in 2013 to meet anticipated demand growth. DRAM capacity investments are at "maintenance level," so no increase of installed capacity is expected in 2013. Samsung’s heavy investments in System LSI will singlehandedly grow SLSI capacity (its $4 billion conversion of Austin, TX fab from Flash to 28nm SoC logic devices).

Promising future

While 2012 may not bring positive growth, it may still end up reigning among the top performing years. As the industry continues to consolidate, with more companies moving towards a fab-lite or fab-less model, traditional foundries continue to expand and some big IDMs ramp their foundry services. Investment "engines" may be idling in the near-term, and those investments could gear up for a smooth acceleration into 2013, driven by high demand for mobile devices.

SEMI Industry Research and Statistics Group: A worldwide dedicated team

Since the last fab database publication at the end of May 2012 SEMI’s worldwide dedicated analysis team has made 296 updates to more than 230 facilities (including 52 Opto/LED fabs) in the database. The August edition of the World Fab Forecast, lists over 1,150 facilities (including 300 Opto/LED facilities), with 76 facilities starting production this year and in the near future.

The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs; and in-depth analyses of capital expenditures, capacities, technology and products by fab. Additionally, the database provides forecasts for the next 18 months by quarter. These tools are invaluable for understanding how the semiconductor manufacturing will look in 2012 and 2013, and learning more about capex for construction projects, fab equipping, technology levels, and products.

SEMI’s Worldwide Semiconductor Equipment Market Subscription (WWSEMS) data tracks only new equipment for fabs and test and assembly and packaging houses. The SEMI World Fab Forecast and its related Fab Database reports track any equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size, including new equipment, used equipment, or in-house equipment.

Also check out the Opto/LED Fab Forecast.

Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase and
www.youtube.com/user/SEMImktstats

SEMI
www.semi.org
San Jose, California
September 4, 2012

September 6, 2012 – Rudolph Technologies says it has received an order for its MetaPulse G metrology system from "a premier global industry research center in Asia" for its advanced packaging process development activities.

The unidentified group will use the system, which shipped in August, for thin-film metrology performed in development and control of advanced wafer-level packaging processes that use metal structures, such as redirect layers (RDL) and under bump metallization (UBM) to route signals from the chip to the package.

"In addition to providing the fast and accurate measurements of thickness, density and roughness, its small spot size and ability to measure structures directly on product wafers allow users to see pattern dependent variations that are not detectable with monitor wafers," according to Tim Kryman, Rudolph

Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, is poised to celebrate its 30th anniversary at its annual TECHCON conference Sept. 10-11.

Hosted in Austin, Texas, the technology conference features next-generation research progress among hundreds of university students, faculty and industry experts. The conference brings together those involved in microelectronics research to exchange news about the progress of new materials and processes created by SRC’s network of more than 100 of the top engineering universities.

At the conference, SRC will also celebrate its 30-year anniversary of successful collaboration between industry leaders and university researchers to conduct basic research intended to accelerate semiconductor advancements that enable future generations of chip technology.

Two recognized experts—Charles Vest, president of the National Academy of Engineering and president emeritus of the Massachusetts Institute of Technology, and John Kelly, senior vice president and director of IBM Research—recently expressed strong support for SRC accomplishments over the decades at a SRC 30th anniversary banquet in June.

“SRC has strategically brought together industry, government and academia to both advance technology and help to educate and train the next generation of engineers, scientists and leaders,” said Vest.

“(SRC) has perfected the management of creating complicated technology alliances that others only can hope to imitate,” said Kelly. “Moreover, in these times of tight budgets— both in industry and government—the SRC continues to find new ways to partner between the public and private sector to maximize the value of every dollar spent on both sides.”

SRC President Larry Sumney applauds luminaries like Vest, Kelly and the many others for their support in helping SRC build a successful collaboration among industry, academia and government.

“Collaboration among industry, academia and government accelerates knowledge advancements, lowers risk and enables growth and innovation to continue for the benefit of industry and society as a whole. It represents a win-win-win,” said Sumney. “Industry taps into the expertise and pipeline of talent in academia. University researchers gain understanding of industry needs. And government investments leverage the industry investments and result in research that enables new applications in electronics, health, energy, mobility, transportation and many other areas.”

Along with showcasing the progress of critical industry-guided university research, SRC annually announces two significant awards at TECHCON for professors in SRC-supported, chip-related research. Selected by SRC’s member companies and the SRC staff, the award-winning faculty and research teams are honored for their exemplary impact on semiconductor productivity through cultivation of technology and talent.

At TECHCON 2011, Stanford University professor Robert Dutton received the SRC Aristotle Award for outstanding teaching in leading his research team to pioneer the development of a suite of technology computer-aided design (TCAD) tools for simulation and modeling of integrated circuit fabrication processes.

Additionally, University of California, Berkeley research engineer Alan Mishchenko and professor Robert Brayton received the SRC Technical Excellence Award for their SRC-funded work advancing the synergy of synthesis and verification steps used in testing and validating semiconductor chips.

More than 9,000 students have been prepared by SRC programs, professors and mentors for entry into the semiconductor business. These students provide a path for technology transfer and a source of relevantly educated technical talent for the industry.

“Semiconductors are the building blocks of the digital age, and university research has been instrumental in advancing the industry,” said Dr. Steve Hillenius, SRC executive vice president. “The highly valued researchers and teams we are showcasing and honoring at TECHCON are driving the semiconductor industry forward.”

Check out last year’s coverage of TECHCON, featuring video interviews with students and professors taking part in semiconductor research projects, as well as talks with SRC about the conference and the research organization’s energy initiative.

FEI (NASDAQ: FEIC) announced two new Helios NanoLab systems, the 450HP and 1200HP DualBeam systems, which include new capability that meets the critical requirements for semiconductor process development at the 28nmdevice geometry node and below.

The Helios NanoLab 450HP and 1200HP DualBeam systems can prepare 15nm thick samples with less than a 2nm damage layer in 90 minutes, two times faster than competitive alternatives. iFast automation software maximizes ease-of-use while ensuring consistency among multiple operators and systems. QuickFlip grid holders facilitate inverted sample preparation to improve sample quality while maintaining high throughput. Cell Navigation software allows automated navigation within non-unique memory arrays that can locate a single designated bit cell in a 50nm lateral field. Together, these features enable a robust process to prepare high quality, ultra-thin lamella across multiple tools in a consistent manner—independent of operator skill level.

 “Developing new processes and technologies that include shrinking geometries, new materials and novel device architectures and ramping those processes to high-volume production quickly are driving unprecedented increases in the demand for TEM analysis,” stated Rudy Kellner, vice president and general manager, Electronics Business Unit, FEI. “TEM samples must be ultra-thin, of the highest quality, and generated in a routine and consistent manner across a fleet of tools. Typically, as samples get thinner, the difficulty becomes time to results, operator skill level and subtle differences among equipment. We have designed the 450HP and 1200HP systems to overcome these issues. Ultimately, the system’s ability to yield more good samples at double the throughput allows for potentially significant reductions for both the time-to-answer and the cost-per-answer.”

August 28, 2012 – Brooks Automation, Chelmsford, MA (Nasdaq: BRKS) has released two extensions to its line of vacuum quality monitoring semiconductor manufacturing subsystem components that measure gases and conditions in a vacuum chamber.

The 835 VQM (Vacuum Quality Monitor), consisting of an ion trap mass spectrometer gauge, a VQM controller, and VQM viewer software, lets users see the 20 most prevalent gases, total pressure trending (with optional total pressure gauge), partial pressure trending, spectral display, data logging, data (screen) capture, gas fitting library for 10 gases, and leak check. The mass spectrometer operates from UHV to 10-5 Torr and accurately measures the gases in the vacuum chamber. (Differential pumping is required to reduce the process chamber pressure to the operating range of the VQM, below 1E-5 Torr.)

Among its new features:

— Measurement range has been expanded to 1-300 amu in 125 ms, with 1-145 amu total and partial pressure measurement information in 85 ms.
— A new API links the VQM software to users’ programs to provide complete control over the VQM and allow reading of gas composition data.
— Also new is a "Vacuum Quality Index" function, where users can enter an equation which drives a digital output, an audible alarm, or the start of data logging — for example, starting a process when total pressure is low enough, water level decreases beyond a certain level, and reactive gas level achieves a specified amount.
— A larger A/D, improved electrometer, lower noise, and software data analysis improvements. The electron multiplier is now field-replaceable.

The 835 VQM controller and gauge operate at a maximum of 15 Watts. The gauge can be mounted remotely using a cable from one to 20 meters long. (Here’s the data sheet for the 835 VQM.)

The 835 VQM Differential Pump System (DPS) adds to the 835 VQM DPS with a gate valve with orifice, turbo pump, roughing pump, and 390 Micro-Ion ATM total pressure gauge. It allows for operation and process control in semiconductor, coating, and other higher pressure applications by allowing operation up to 3 Torr. During base out, the gate valve is open providing the VQM with a high conductance path directly to the process chamber for greater sensitivity and accuracy; during process the gate valve is closed and a turbo pump is used to reduce pressure through the limited conductance of the orifice. The valve can be manually or pneumatically controlled. (Here’s the data sheet for the 835 VQM DPS.)

"Customers that have been asking for extended mass range, process control outputs and operation at higher pressures, can now benefit from the VQM ion trap technology," said Joergen Olsson, GM of Brooks Automation’s Instrumentation Group. "The wait is over for those wanting to utilize the speed, simple calibration, and ease of use advantages of the VQM for their applications."

August 27, 2012 – SEMI has created a new information portal to offer news and perspectives about the 450mm wafer-size transition.

The "450 Central" Web-based information service compiles industry news, technology information, new product announcements, SEMI Standards updates, presentations, and other relevant information on 450mm wafer processing.

The transition to using 450mm wafers is one of the semiconductor industry’s most challenging and complex issues, and consortium efforts are underway in both the US and Europe. But that also means semiconductor equipment suppliers need to update their existing 300mm tools, or devise new versions, to handle the bigger wafers which have some special needs in handling and processing. And that means lots of investments: SEMI projects anywhere from $8B to $40B for 450mm R&D, and $25B in capital expenses for first-generation high-volume manufacturing equipment due by 2016-2017. Still, the biggest chipmakers see it as their next major cost-saving implementation — perhaps as much as 30% — so everyone agrees 450mm is necessary and inevitable.

"Robust communication throughout the supply chain is essential for a cost-effective wafer size transition," stated Jonathan Davis, president of the semiconductor business for SEMI. "450 Central provides the necessary link for accurate information for buyers, planners, suppliers, investors, and other key stakeholders in next generation wafer processing."

SEMI says it will work with all IDMs, industry consortia, and suppliers to populate 450mm Central with accurate and timely information. To have your new product, perspective, or other information considered for inclusion, send an email (with Word doc and graphic) to [email protected].

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