Category Archives: New Products

KLA-Tencor Corporation (NASDAQ: KLAC) announced the eS805, a new electron-beam inspection system capable of detecting very small defects, and defects that cause electrical problems such as opens, shorts or reliability issues. The eS805 is also designed to provide supplementary information to the fab’s optical inspection systems, with the goal of boosting the ability of the optical inspectors to preferentially capture defects that matter.

Bobby Bell, executive vice president of KLA-Tencor’s Wafer Inspection Group, said: "We believe that optical inspection will continue as the dominant defect inspection approach; its speed is essential for adequate wafer coverage, and our engineers have demonstrated some impressive ideas for stretching optical sensitivity to meet our customers’ anticipated requirements. Electron-beam inspection will continue to complement optical inspection as needed..”

The high performance of the new eS805 is driven by the following advances:

  • New image computer, new auto-focus subsystem, and higher beam current densities than other commercially available systems, enabling detection of buried electrical defects in "voltage contrast" ("VC") mode over relatively large areas of the die;
  • Architecture designed to elicit significant signal from defects hidden at the bottom of high aspect ratio (HAR) structures such as FinFETs and 3D flash; and
  • Advanced algorithms that, together with the new image computer and auto-focus system, enable efficient capture of small defects within non-periodic structures, such as logic areas of the cell.

The eS805 is upgradeable from any previous eS3x or eS8xx-series e-beam inspection system.

New eS805 e-beam inspection systems have been shipped to leading logic and memory chip manufacturers, where they are being used to upgrade existing e-beam inspection capability or to fulfill requirements for additional inspection capacity in advanced development and production lines. To maintain high performance and productivity, the eS805 tools are backed by KLA-Tencor’s global, comprehensive service network. 

Newport Corporation introduced long-lived deep ultraviolet (UV) excimer laser mirrors with projected lifetimes greater than 30 billion pulses when used in the proper photocontamination controlled environment.  The advanced new mirrors feature all dielectric high reflector coatings to minimize absorption and maximize reflected energy at 193nm.

The high energy laser mirrors are designed with excimer-grade UV-fused silica substrates which are polished to better than λ/10 flatness to preserve wavefront quality and maintain excellent stability.  All coating and testing are done in a special photocontamination controlled deep UV cleanroom that has been qualified to 193nm standards.

According to Optics product manager at Newport, Anna Sansan Wang,“Extensive analysis, research and testing have been done to better understand the conditions at these short wavelengths. Our coating scientists have investigated various conditions including thermal issues, densification of materials, and wavelength shift in order to properly optimize the performance of the mirrors at 193 nm under long term use.”

Newport’s new laser mirrors offer exceptionally high laser damage resistance.  Special Pet-G and metal foil packaging ensure that parts are delivered clean and protected from any environmental photocontamination.  The long-lived deep UV Excimer laser mirrors will be featured at SPIE Photonics West in Newport’s booth #1301 at Moscone Center, San Francisco, CA, February 5 – 7, 2013. 

 

Cadence Design Systems, Inc. (NASDAQ: CDNS) announced the availability of Virtuoso® Advanced Node, a new set of custom/analog capabilities designed for the advanced technology nodes of 20nm and below.Built on the industry-leading Cadence® Virtuoso custom/analog technology, Virtuoso Advanced Node features capabilities that prevent errors before they are created rather than detect them late in the design process. Working in concert with Cadence Encounter® RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node enables the development of mixed-signal chips that power today’s consumer electronics devices.

The new and advanced Virtuoso technologies address layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers. They integrate with the Cadence Integrated Physical Verification System (IPVS) to conduct on-the-fly checks that reduce layout iterations.

LDE analysis using incremental layout — Virtuoso Advanced Node enables engineers to build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end.  It delivers novel technology that helps decrease costly design iterations by allowing designers the ability to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle.  LDEs — such as stress effects, poly and diffusion spacing/length, well proximity effects, and parasitics — are handled with detailed test benches that analyze multiple corners to ensure that the circuit will function as specified.

When this technique is combined with Cadence MODGENs and constraints, IPVS and final hotspot detection and correction with Virtuoso DFM, users can expect up to a 30 percent improvement in their overall verification time.  By methodically building and checking the design, the designer should eliminate massive “rip ups” and “reroutes” that can be found at the end if the circuit wasn’t checked along the way.

Double patterning and color-aware layout—Double patterning, a manufacturing requirement at 20 nanometers, splits the design layers into two masks, separating structures that are too close together. But double patterning brings “coloring” challenges to designers. Virtuoso Advanced Node delivers real-time automated color-aware, design-rule-driven layout to enable the creation of area-optimized layout. It provides engineers the ability to match, lock and store colors on critical nets and geometries (through schematic constraints or directly on the layout), and to identify, debug and fix errors as they go, rather than later in the design process, when they are more difficult to fix.

New routing layers—Foundries require the utilization of new local interconnect (LI) layers, or middle-of-line (MOL) layers, that are used to create densely packed routes inside complex devices. These layers have restricted design rules governing local interconnect and the vias that are used with them, presenting the challenge of maintaining signal integrity from pin to pin of the transistors. Virtuoso Advanced Node technology provides a local interconnect-aware wire editor and router that address the issue of complex LI rules.

Developed specifically for the most cutting-edge designs, the Virtuoso Advanced Node options do not replace the industry-leading 6.x version of the Virtuoso technology, which targets mature and mainstream geometries, and which will continue to be enhanced by Cadence.

“Moving to smaller geometries always creates new obstacles, but the move to 20 nanometers has been especially challenging for our customers, many of whom are reporting that layout is taking two to five times as long as for 28nm on the same circuit,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “Virtuoso Advanced Node enables design teams to optimize their designs for performance, power and area while reducing or even eliminating tasks that would make 20nm design much more time consuming and labor intensive.”

ProPlus Design Solutions, Inc., announced it is shipping a new wafer-level, 1/f noise measurement system. Increasingly, circuit designers are interested in 1/f noise data at higher frequencies. They are concerned also about variation effects at leading-edge process nodes, increasing the need for statistical noise models. Generating statistical noise models requires massive amounts of data collection that is particularly challenging at low frequencies.

The 9812D low-frequency 1/f noise measurement system is designed to measure low-frequency noise characteristics of on-wafer or packaged semiconductor devices, including MOSFETs, bipolar junction transistors (BJTs), junction field effect transistors (JFETs), diodes and diffusion resistors. In addition to frequency domain measurement, 9812D can measure device noise in the time domain and can be used to perform on-wafer auto measurement for flicker (1/f) noise and Radom Telegraph Signal (RTS) analyses.

9812D improves upon 9812B, the company’s 1/f measurement system used for more than a decade by foundries, integrated device manufacturers (IDMs) and research organizations. The system, which has a frequency range that exceeds 10 Megahertz (MHz), has a built-in dynamic signal analyzer (DSA) with multi-threaded processing for improved performance and reduced cost.

“Noise is a key figure of merit for semiconductor process quality and also an intrinsic characteristic impacting circuit performance,” said Dr. Zhihong Liu, executive chairman of ProPlus Design Solutions. “To meet the new challenges at 28 nanometer and beyond, we worked with leading foundries on significant improvements of the 1/f system.”

Wafer fabrication facilities use 7*24 1/f noise measurement data to assess process quality. A three-to-10X throughput improvement of the 9812D system means faster data collection and early detection of process issues.