Category Archives: Packaging and Testing

By Dr. Dan Tracy, Senior Director, Industry Research and Statistics, SEMI

With the recent release of Apple’s 6s and the form factors of internet enabled mobile devices and the emergence of the IoT (Internet of Things), advanced packaging is clearly the enabling technology providing solutions for mobile applications and for semiconductor devices fabricated at 16 nm and below process nodes. These packages are forecasted to grow at a compound annual growth rate (CAGR) of over 15% through 2019.  In addition, the packaging technologies have evolved and continue to evolve so to meet the growing integration requirements needed in newer generations of mobile electronics. Materials are a key enabler to increasing the functionality of thinner and smaller package designs and for increasing the functionality of system-in-package solutions.

Figure 1: Packaging Technology Evolution – Great Complexity in Smaller, Thinner Form Factors, courtesy of TechSearch International, Inc.

Figure 1: Packaging Technology Evolution – Great Complexity in Smaller, Thinner Form Factors, courtesy of TechSearch International, Inc.

The observations related to mobile products include:

  • New package form factors to satisfy high-performance, high-bandwidth, and low power consumption requirements in a thinner and smaller package.
  • Packaging solutions to deliver systems-in-package capabilities while satisfying low-cost requirements.
  • Shorter lifetimes and differing reliability requirements. For example, high-end smartphones and tablets, the key high reliability requirement is to pass the drop test; and packaging material solutions are essential to delivering such reliability.
  • Shorter production ramp times to meet time-to-market demands of end product. This is becoming critical and causes redundancy in capacity to be required, capacity that is underutilized for part of the year

Packaging must provide a low-cost solution and have an infrastructure in place to meet steep ramps in electronic production. The move towards bumping and flip chip has only accelerated with the growth in mobile electronics, though leadframe and wirebond technologies remain as important low-cost alternatives for many devices. Wafer bumping has been a major packaging market driver for over a decade, and with the growth in mobile the move towards wafer bumping and flip chip has only accelerated with finer pitch copper pillar bump technology ramping up. Mobile also drives wafer-level packaging (WLP) and Fan-Out (FO) WLP. New wafer level dielectric materials and substrate designs are required for these emerging package form factors.

Going forward, the wearable and IoT markets will have varying packaging requirements depending on the application, the end use environment, and reliability needs. Thin and small are a must though like other applications cost versus performance will determine what package type is adopted for a given wearable product, so once more leadframe and wirebonded packages could be the preferred solution. And in many wearable applications, materials solutions must provide a lightweight and flexible package.

Such packaging solutions will remain the driver for materials consumption and new materials development, and the outlook for these packages remain strong. Materials will make possible even smaller and thinner packages with more integration and functionality.  Low cost substrates, matrix leadframe designs, new underfill, and die attach materials are just some solutions to reduce material usage and to improve manufacturing throughput and efficiencies.

SEMI and TechSearch International are once again partnering to prepare a comprehensive market analysis of how the current packaging technology trend will impact the packaging manufacturing materials demand and market.  The new edition of “Global Semiconductor Packaging Materials Outlook” (GSPMO) report is a detailed market research study in the industry that quantifies and highlights opportunities in the packaging material market. This new SEMI report is an essential business tool for anyone interested in the plastic packaging materials arena. It will benefit readers to better understand the latest industry and economic trends, the packaging material market size and trend, and the respective market drivers in relation to a forecast out to 2019. For example, FO-WLP is a disruptive technology that impacts the packaging materials segment and the GSPMO addresses this impact.

 

HILLSBORO, Ore. — October 27, 2015 — FEI Company and DCG Systems, Inc. today announced a definitive agreement under which FEI would acquire DCG for $160 million in an all cash transaction. DCG is a leading supplier of electrical fault characterization, localization and editing equipment, serving process development, yield ramp and failure analysis applications for a wide range of semiconductor and electronics manufacturers. Headquartered in Fremont, California, DCG is a profitable private company and was the recipient of Deloitte’s Technology Fast 500 award in 2013 and 2014.

The deal combines FEI’s leading physical failure analysis capabilities for the semiconductor lab with DCG’s complementary portfolio of electrical failure analysis solutions.  DCG’s offerings expand FEI’s served available market through the addition of optical imaging, thermal imaging and nano-probing technologies.  The combined company’s solutions will offer a more complete workflow for customers as they deal with the increasing complexities from process development to advanced 3D packaging.

“The acquisition of DCG expands FEI’s presence and capability in the semiconductor lab and enhances our ability to provide a complete workflow solution,” commented Don Kania, president and CEO of FEI. “The combination brings together leaders in physical and electrical failure analysis and will enable our customers to better connect workflows to improve time to data and efficiency.”

“Together with FEI we have a tremendous opportunity to offer our customers an integrated defect analysis solution,” commented Israel Niv, CEO of DCG. “The DCG team is excited to join forces with FEI and tap into FEI’s strong global presence and significant R&D capabilities to drive further penetration of DCG’s leading electrical failure analysis solutions.  We look forward to working together with FEI to provide integrated solutions to help our customers successfully execute on their future technology roadmaps.”

DCG generated revenue of $76 million in its fiscal year ended January 31, 2015.  The transaction is expected to be slightly accretive to FEI’s 2016 GAAP EPS.  FEI intends to fund the acquisition with cash on hand.

The transaction is expected to close by the end of 2015 and is subject to certain regulatory approvals and customary closing conditions.

Today, in conjunction with the 41st International Symposium for Testing and Failure Analysis (ISTFA), DCG Systems® announced the release of EBIRCH™, a new, unique technology for localizing shorts and other low-resistance faults that may reside in the interconnect structures or the polysilicon base layer of integrated circuits. Named for Electron Beam Induced Resistance Change, EBIRCH offers fault analysis (FA) engineers and yield experts the ability to detect and isolate low-resistance electrical faults without resorting to brute-force binary search approaches that rely on successive FIB* cuts. Its unparalleled ability to quickly isolate low-resistance faults enables EBIRCH to boost the success rate of physical failure analysis (PFA) imaging techniques to well above 90%, accelerating time-to-results and establishing the FA lab as a critical partner organization in solving yield and reliability problems.

“At foundries and IDM* fabs, the process has become more difficult to control using traditional inline measures,” said Mike Berkmyre, business unit manager of the Nanoprobing Group at DCG Systems. “More yield issues are remaining undetected until they show up at final test — and land on the desk of the FA lab manager. The FA engineers must be equipped to localize the fault and supply images of the root cause to process or yield engineers in a timely manner. The ability to quickly and reliably localize low-resistance faults was missing before we developed EBIRCH. With the introduction of EBIRCH, we are helping to solve an FA problem that has been growing in prevalence and importance with each new device node.”

Available on DCG’s current SEM*- based nanoprobing systems, EBIRCH offers the following capabilities:

  • Detects and isolates electrical faults with resistances from < 10 ohm to > 50 Mohm;
  • Finds faults at surface and several levels below concurrently, significantly accelerating the existing work flow; and
  • Can scan areas as large as 1mm by 1mm, and zoom in to areas as small as 50nm by 50nm, providing accurate and actionable fault localization within minutes.

To collect an EBIRCH image, the operator lands two nanoprobes on surface metal layers, straddling the suspected defect site. A bias is applied, and the electron beam rasters across the region of interest. As the e-beam interrogates the defect site, localized heating from the e-beam changes the resistance of the defect, thereby changing the current sensed by the nanoprobe. The EBIRCH map displays the change in current as a function of the e-beam position—typically showing a bright spot at the site of the resistance change. The simultaneously acquired SEM image, together with knowledge of the circuit layout, allows the engineer to determine the exact defect location. The depth at which the defect lies can be explored by optimizing the landing energy as a function of the EBIRCH signal.

Available exclusively on the flexProber™, nProber™ and nProber II™ nanoprobers from DCG Systems, EBIRCH is part of an integrated electron beam current (EBC) module that offers seamless switching from EBAC to EBIRCH, with no re-cabling needed.

Plasma-Therm announced that it has acquired an innovative High Density Radical Flux plasma technology, which enables low-temperature Bosch polymer removal.

High Density Radical Flux — HDRF® —was developed by Nanoplas France as a superior plasma process for low-temperature removal of photoresists and organic polymer residues. These capabilities are especially important for device fabrication steps in the MEMS, LED, and advanced packaging markets.

Plasma-Therm is integrating HDRF technology into its existing suite of plasma etching, deposition, and wafer-dicing products. The Nanoplas-developed HDRF low-temperature photoresist stripping capability is also applicable to Bosch polymer removal after DRIE processing.

“We are eager to make the HDRF technology available to our existing customers and potential customers,” said Ed Ostan, vice president of marketing for Plasma-Therm. “HDRF fits very well into our etch and deposition product line, because this will allow Plasma-Therm to provide multi-step solutions to specialized device manufacturers for both R&D and production use.”

Plasma-Therm will also offer ongoing support to Nanoplas customers. The Nanoplas installed baseis primarily made up of DSB 6000 and DSB 9000 HDRF systems.

HDRF enables removal of photoresist, as well as organic polymers left on trench sidewalls following DRIE processes. These applications are sought for advanced packaging, MEMS, and power devices.

HDRF systems incorporate a multi-zone, remote, inductively coupled plasma (ICP) source, which produces up to 1,000 times greater chemical concentration than a conventional ICP source.

HDRF provides better performance than wet processing and regular plasma processing in terms of selectivity, low damage, flexibility, and high-aspect-ratio efficiency. HDRF provides superior polymer removal efficiency for high-aspect-ratio (greater than 50:1) structures.

With operating temperatures lower than 80° C., and with high selectivity to TiN, Al, Au, SiO2, and Si3N4, HDRF provides damage-free residue removal for ultra-sensitive devices.

Nanoplas introduced the semi-automatic DSB 6000 system in 2008. It was followed in 2011by the fully automatic 200mm DSB 9000 system, which accommodates one or two process modules. Both systems are capable of chemical downstream etching, stripping and cleaning applications. The company also designed the HDRF300 system for advanced cleans for 3D-IC fabrication. Nanoplas customers include global companies utilizing the systems in volume production, and also R&D and pilot line facilities, company officials said.

A report that resulted from a workshop funded by Semiconductor Research Corporation (SRC) and National Science Foundation (NSF) outlines key factors limiting progress in computing—particularly related to energy consumption—and novel device and architecture research that can overcome these barriers. A summary of the report’s findings can be found at the end of this article; the full report can be accessed here.

The findings and recommendations in the report are in alignment with the nanotechnology-inspired Grand Challenge for Future Computing announced on October 20 by the White House Office of Science and Technology Policy. The Grand Challenge calls for new approaches to computing that will operate with the efficiency of the human brain. It also aligns with the National Strategic Computing Initiative (NSCI) announced by an Executive Order signed by the President on July 29.

Energy efficiency is vital to improving performance at all levels. This includes from devices and transistors to large IT systems, as well from small sensors at the edge of the Internet of Things (IoT) to large data centers in cloud and supercomputing systems.

“Fundamental research on hardware performance, complex system architectures, and new memory/storage technologies can help to discover new ways to achieve energy-efficient computing,” said Jim Kurose, the Assistant Director of the National Science Foundation (NSF) for Computer and Information Science and Engineering (CISE). “Partnerships with industry, including SRC and its member companies, are an important way to speed the adoption of these research findings.”

Performance improvements today are limited by energy inefficiencies that result in overheating and thermal management issues. The electronic circuits in computer chips still operate far from any fundamental limits to energy efficiency, and much of the energy used by today’s computers is expended moving data between memory and the central processor.

At the same time as increases in performance slow, the amount of data being produced is exploding. By 2020, an estimated 44 zettabytes of data (1 zettabyte equals 1 trillion gigabytes) will be created on an annual basis.

“New devices, and new architectures based on those devices, could take computing far beyond the limits of today’s technology. The benefits to society would be enormous,” said Tom Theis, Nanoelectronics Research Initiative (NRI) Executive Director at SRC, the world’s leading university-research consortium for semiconductor technologies.

Inspired by the neural architecture of a macaque brain, this neon swirl is the wiring diagram for a new kind of computer that, by some definitions, may soon be able to think. (Credit: Emmett McQuinn, IBM Research - Almaden)

Inspired by the neural architecture of a macaque brain, this neon swirl is the wiring diagram for a new kind of computer that, by some definitions, may soon be able to think. (Credit: Emmett McQuinn, IBM Research – Almaden)

In order to realize these benefits, a new paradigm for computing is necessary. A workshop held April 14-15, 2015 in Arlington, Va., and funded by SRC and NSF convened experts from industry, academia and government to identify key factors limiting progress and promising new concepts that should be explored. The report being announced today resulted from the workshop discussions and provides a guide to future basic research investments in energy-efficient computing.

The report builds upon an earlier report funded by the Semiconductor Industry Association, SRC and NSF on Rebooting the IT Revolution.

To achieve the Nanotechnology Grand Challenge and the goals of the NSCI, multi-disciplinary fundamental research on materials, devices and architecture is needed. NSF and SRC, both individually and together, have a long history of supporting long-term research in these areas to address such fundamental, high-impact science and engineering challenges.

Report Findings

Broad Conclusions

Research teams should address interdisciplinary research issues essential to the demonstration of new device concepts and associated architectures. Any new device is likely to have characteristics very different from established devices. The interplay between device characteristics and optimum circuit architectures therefore means that circuit and higher level architectures must be co-optimized with any new device. Devices combining digital and analog functions or the functions of logic and memory may lend themselves particularly well to unconventional information processing architectures. For maximum impact, research should focus on devices and architectures which can enable a broad range of useful functions, rather than being dedicated to one function or a few particular functions.

Prospects for New Devices

Many promising research paths remain relatively unexplored. For example, the gating of phase transitions is a potential route to “steep slope” devices that operate at very low voltage. Relevant phase transitions might include metal-insulator transitions, formation of excitonic or other electronic condensates, and various transitions involving structural degrees of freedom. Other promising mechanisms for low-power switching may involve transduction. Magnetoelectric devices, in which an external voltage state is transduced to an internal magnetic state, exemplify the concept. However, transduction need not be limited to magnetoelectric systems.

In addition to energy efficiency, switching speed is an important criterion in choice of materials and device concepts. For example, most nanomagnetic devices switch by magnetic precession, a process which is rather slow in the ferromagnetic systems explored to date. Magnetic precession switching in antiferromagnetic or ferrimagnetic materials could be one or more orders of magnitude faster. Other novel physical systems could be still faster. For example, electronic collective states could, in principle, be switched on sub-picosecond time scales.

More generally, devices based on computational state variables beyond magnetism and charge (or voltage) could open many new possibilities.

Another relatively unexplored path to improved energy efficiency is the implementation of adiabatically switched devices in energy-conserving circuits. In such circuits, the phase of an oscillation or propagating wave may represent digital state; devices and interconnections must together constitute circuits that are non-dissipative. Nanophotonic, plasmonic, spin wave or other lightly damped oscillatory systems might be well-suited for such an approach. Researchers should strive to address the necessary components of a practical engineering solution, including mechanisms for correction of unavoidable phase and amplitude errors.

Networks of coupled non-linear oscillators have been explored for non-Boolean computation in applications such as pattern recognition. Potential technological approaches include nanoelectromechanical, nanophotonic, and nanomagnetic oscillators. Researchers should strive for generality of function and should address the necessary components of a practical engineering solution, including devices, circuits, and architectures that allow reliable operation in the presence of device variability and environmental fluctuations.

Prospects for New Architectures

While appropriate circuits and higher level architectures should be explored and co-developed along with any new device concept, certain novel device concepts may demand greater emphasis on higher-level architecture. For example, hysteretic devices, combining the functions of non-volatile logic and memory, might enhance the performance of established architectures (power gating in microprocessors, reconfiguration of logic in field programmable gate arrays), but perhaps more important, they might play an enabling role in novel architectures (compute in memory, weighting of connections in neuromorphic systems, and more). As a second example, there has been great progress in recent years in the miniaturization and energy efficiency of linear and non-linear photonic devices and compact light emitters. It is possible that these advances will have their greatest impact, not in the ongoing replacement of metal wires by optical connections, but rather in enabling new architectures for computing. Computation “in the network” is one possible direction. In general, device characteristics and architecture appear to be highly entwined in oscillatory or energy-conserving systems. Key device characteristics may be inseparable from the coupling (connections) between devices. For non-Boolean computation, optimum architectures and the range of useful algorithms will depend on these characteristics.

In addition to the examples above, many other areas of architectural research might leverage emerging device concepts to obtain order of magnitude improvements in the energy efficiency of computing. Research topics might include architectures for heterogeneous systems, architectures that minimize data movement, neuromorphic architectures, and new approaches to Stochastic Computing, Approximate Computing, Cognitive Computing and more.

Slideshow: 2015 IEDM Preview


October 20, 2015
The 2015 IEDM Conference will be held in Washington DC.

The 2015 IEDM will be held in Washington DC.

This year marks the 61st annual IEEE International Electron Devices Meeting (IEDM). It is arguably the world’s pre-eminent forum for reporting technological breakthroughs in semiconductor and electronic device technology, design, manufacturing, physics, and modeling. The conference focuses not only on devices in silicon, compound and organic semiconductors, but also in emerging material systems.

As usual, Solid State Technology will be reporting insights from bloggers and industry partners during the conference. This slideshow provides an advance look at some of the most newsworthy topics and papers that will be presented at this year’s meeting, which will be held at the Washington, D.C. Hilton from December 7-9, 2015.

Click here to start the slideshow

Check back here for more articles and information about IEDM 2015:

Helpful conference links:

In the early 90s Siborg Systems Inc. released MicroTec: a semiconductor device and process simulator that has become used by more than 140 Universities and more than 40 semiconductor companies for computationally extensive simulations. Siborg has recently made a new version available particularly targeting educational use of the software. Examples are created for a few popular semiconductor process and device text books including “Solid State Electronic Devices” by Ben Streetman, Sanjay Banerjee, Pearson Education, March 9, 2014; “Modern Semiconductor Devices for Integrated Circuits” by Chenming C. Hu, Pearson Education, March 22, 2009; and “Fabrication Engineering at the Micro- and Nanoscale” by Stephen A. Campbell, Oxford University Press, September 5, 2007.

Microtec is a significantly simplified semiconductor TCAD tool while still being a powerful modeling tool for industrial semiconductor process/device design. It is an efficient tool for computationally extensive simulations arising in modeling of power semiconductor devices with large dimensions, and is particularly useful for devices made of SiC, GaN and other materials with a wide bandgap.

The program was widely used in education, including Universities such as UC Berkeley, Waseda University, Tokyo Institute of Technology, and the University of Waterloo; it allows students to learn basic ideas about the modern semiconductor device design in a realistic model environment and create their own virtual devices using realistic process flow and test their performance. MicroTec is an easy-to-use simplified TCAD tool that can be learned Microtec within a few hours while still offering robustness and realistic semiconductor process and device simulation. The program also is an asset to those who need to understand the physics of semiconductor devices without knowing much about computers or numerical methods and who do not have much time for learning new process/device simulation tools.

A simplified limited version of MicroTec semiconductor device simulator was also published by John Wiley and Sons, 2000-02-08, in “Semiconductor Devices Explained: Using Active Simulation”, by Ton Mouthaan, Professor of the Twente University in the Netherlands.

MicroTec is able to simulate 2D silicon process modeling including epitaxy, oxidation, diffusion and implantation and 2D steady-state semiconductor device simulation including SOI-MOSFET, MOSFET, BJT, JFT,IGBT, DMOS, Schottky devices, Solar Cells, etc.

Based on the diffusion-drift model, Microtec employs finite difference technique on a rectangular, automatically generated mesh.

One of the features of MicroTec is the ability to run on virtually any PC. Being a true 32-bit application for Windows, MicroTec needs very little RAM allocation. With no memory threshold, the program can be even be run on computers with only a few Mbytes of memory if a modest number of mesh nodes is used. Typical simulation only take minutes of CPU time on a regular PC.

Microtec includes three main software tools:

  • SiDif for 2D semiconductor process simulation including implantation, diffusion, oxidation and epitaxy
  • SemSim for steady-state 2D semiconductor device simulation
  • SiBGraf for 2D and 1D graphics

New S$150 million joint investment is expected to create 60 jobs for highly skilled scientists, engineers and researchers.

SINGAPORE, October 19, 2015 – Applied Materials, Inc. today announced it plans to establish a new R&D laboratory in Singapore in collaboration with the Agency for Science, Technology and Research (A*STAR). The S$150 million joint investment will focus on developing advanced semiconductor technology to fabricate future generations of logic and memory chips.

The S$150 million joint lab will be housed within A*STAR’s new R&D cluster at Fusionopolis Two and will feature a 400 square meter Class 1 cleanroom with state-of-the-art semiconductor process equipment that has been custom designed and built by Applied Materials. The facility will be staffed by 60 highly skilled researchers and scientists, working together with extended research teams at A*STAR’s other research institutes.

The joint lab combines Applied Materials’ leading expertise in materials engineering with A*STAR’s multi-disciplinary R&D capabilities. A*STAR’s Institute of Microelectronics (IME), Institute of Materials Research and Engineering (IMRE), and Institute of High Performance Computing (IHPC) will contribute to research in low-defect processing, ultra-thin film materials, materials analysis and characterization, and modelling and simulation in many areas. The joint lab is also supported by The Singapore Economic Development Board, and is in line with its efforts to promote leading-edge R&D and advanced manufacturing activities. The intention is for products developed by the joint lab to be manufactured by Applied Materials in Singapore. In addition, Applied Materials plans to conduct experiments on the synchrotron at the Singapore Synchrotron Light Source (SSLS) and work with the National University of Singapore where a new beamline for semiconductor applications is to be developed. Funding for the construction of the new beamline is supported by the National Research Foundation.

Mr. Gary Dickerson, President and Chief Executive Officer of Applied Materials, Inc., said, “A*STAR and the government of Singapore have been great R&D partners for Applied Materials. We are excited to expand our collaboration to develop advanced semiconductor technology for extending Moore’s Law. Applied Materials’ leading expertise in materials engineering can help solve the challenges of producing future generations of logic and memory chips.”    

Mr. Lim Chuan Poh, Chairman, A*STAR, said, “This collaboration will catalyse the development of emerging technologies for the global electronics market and advance Singapore’s position as a key R&D hub for the industry. The joint lab reaffirms A*STAR’s multi-disciplinary R&D capabilities to drive innovation in the electronics sector, a key growth area for Singapore’s economy, and will generate further economic value through the creation of good jobs.”

“The joint lab will strengthen capabilities for Applied Materials in Singapore, as we expand from advanced manufacturing to early stage R&D and designing global products,” said Mr. Russell Tham, Corporate Vice President & Regional President South East Asia, Applied Materials, Inc. “Successful public-private partnerships, leveraging complementary strengths, help create new forms of value from Singapore and keep the local industry competitive.”

Prof. Raj Thampuran, Managing Director, A*STAR, said, “The new joint lab takes the longstanding collaboration between Applied Materials and A*STAR to the next level, and will marshal our combined strengths in research, development, innovation and industrial applications. This technology will pioneer new processes and techniques to advance the fabrication of semiconductor devices.”

The new joint lab marks Applied Materials’ second collaboration with A*STAR. In 2012, Applied and A*STAR’s IME formed a Center of Excellence in Advanced Packaging in Singapore to develop advanced 3D chip packaging technology.

Yamaichi Electronics presents Test Contactors for lab and reliability applications and ultra fine pitch semiconductor devices.

New semiconductor devices, like wafer level CSPs for mobile applications, have ball pitches of 0.35mm. And there is a trend to shrink towards lower pitches.

For testing such devices, Yamaichi Electronics in Europe (European headquarters in Munich, Bavaria) develops test contactors (TC) within the YED254 and YED274 series. The TC is individually modified and designed for different outline dimensions of the package. Very important is a homogeneous force distribution on the device surface to avoid device cracking.

Through Yamaichi Electronics’ experience in developing test and burn-in sockets, the opening and closing mechanism is released for easy handling. The test contactor is designed with compression mount technology, therefore no soldering is needed. Selected materials like air craft aluminum, PEEK, and ceramic PEEK make the socket robust.

This offers the customer a variety of TCs which can be used in any custom application:

  • Evaluation: the first silicon has been received to verify the functionality
  • HAST/HTOL/ELFR: reliability and stress tests for pre-qualification and during silicon production
  • ESD/Latch-Up Test: performed as part of product qualification
  • Failure Analysis: finding device malfunctions during development, production and field

To fulfill these requirements, Yamaichi Electronics has a portfolio of probe pins. The low inductance probe pin for the 0.35mm pitch has a length in working position of only 1.7mm. All pins have been electrical qualified and the standard data are available on request. This helps to select the best performing pin for our customers’ individual needs.

D2S (R), a supplier of GPU-enabled software for semiconductor manufacturing, today announced that it has partnered with Advantest, the world’s largest supplier of semiconductor Automatic Test Equipment, to integrate D2S’ Wafer Plane Analysis engine into Advantest’s Mask MVM-SEM (Multi Vision Metrology Scanning Electron Microscope) systems. This new capability enables fast and highly repeatable CD metrology for complex photomask shapes, including those created by inverse lithography technology (ILT), which enables photomask manufacturers to quickly, accurately and cost-effectively identify mask-level CD uniformity (CDU) issues that will impact the wafer during subsequent lithography processing in the wafer fab.

“We’re pleased to be working with D2S on developing a joint solution to improve mask CDU analysis, which results in a better quality mask for our customers,” stated Takayuki Nakamura, Executive Officer, General Manager of Nanotechnology Business Division, Advantest. “Combining D2S’ expertise in GPU-accelerated simulation technologies with our leading-edge CD-SEM tools–such as our new E3640–allows us to provide a cost-effective platform for extremely fast lithography simulation.”

Advanced photomasks are increasingly adopting non-orthogonal patterns and complex shapes, such as curvilinear mask patterns, due to the need for aggressive optical proximity correction (OPC) and ILT to enable production of leading-edge semiconductor devices with ever-smaller feature sizes. As these mask patterns become more complex, conventional CD metrology that measures CDs on straight lines/spaces no longer works since most mask patterns do not have uniform CDs after OPC and ILT correction. In addition, the number of mask defect issues flagged during mask inspection increases. However, not all of these mask issues will actually result in yield problems on the wafer. As a result, this increases the need for photomask manufacturers to understand the wafer-level impact of mask-level issues.

Wafer plane (aerial) analysis has emerged as a solution for identifying mask-level CDU issues that will impact the wafer. However, optical-based wafer plane analysis solutions are expensive, can be slow to implement, and have difficulty providing repeatable results. Mask manufacturers need a new wafer plane analysis solution that is less expensive, faster, and highly repeatable without requiring new equipment or additions to the mask inspection process.

The D2S Wafer Plane Analysis Engine provides aerial simulation of mask contours extracted by the Advantest MVM-SEM for today’s complex mask patterns, including ILT shapes for memory and logic. It is fully integrated into the Advantest CD-SEM system, which enables mask shops to access the benefits of GPU-accelerated wafer plane analysis without adding costly iterations with a standalone optical system.

“GPU acceleration is a powerful tool for enabling fast and accurate aerial simulation of complex mask patterns. It is particularly advantageous on curvilinear mask contours, which are increasingly being populated in today’s leading-edge photomasks,” stated Dr. Linyong (Leo) Pang, chief product officer and executive vice president of D2S. “The new Wafer Plane Analysis Engine from D2S provides wafer plane analysis capability within seconds. Combining our capability with Advantest’s SEM solutions gives their customers a powerful solution for identifying which mask features truly have a CDU problem on the wafer in order to enable swift and cost-effective correction. It can also be used for mask post-inspection defect review to enable fast dispositioning of defects based on their simulated printability. “