Category Archives: Packaging

The Electronic System Design Alliance, a SEMI Strategic Association Partner, today opened nominations for member company executives to serve on the ESD Alliance Governing Council for the next two-year term.

Elections, normally on a two-year cycle, were postponed in 2018 as the ESD Alliance became a SEMI Strategic Alliance Partner. During this cycle, up to nine members will be elected to a two-year term.

Current Governing Council members are:

  • Simon Segars, chief executive officer (CEO) of Arm Holdings
  • Lip-Bu Tan, president and CEO from Cadence Design Systems
  • Dean Drako, IC Manage’s president and CEO
  • Wally Rhines, CEO emeritus at Mentor, a Siemens Business
  • John Kibarian, president and CEO from PDF Solutions
  • Grant Pierce, CEO of Sonics
  • Aart de Geus, Synopsys’ chairman and co-CEO
  • Bob Smith, executive director of the ESD Alliance

Executives from member companies can nominate themselves or be nominated by someone from within a member company. Forms are available on the ESD Alliance website. Candidate statements will be posted on the website as they are received, with elections in mid-April. Results will be announced in May.

The Governing Council’s charter is to provide input and steer the direction of the organization. The ESD Alliance’s board of directors became the Governing Council when the ESD Alliance transitioned into SEMI as a SEMI Strategic Association Partner.

“Participating on the Governing Council offers executives a chance to help shape our industry, especially as the ESD Alliance’s global footprint expands and we increase our initiatives with the launch of ES Design West,” remarks Smith. “It’s a satisfying experience and we encourage executives from the electronic system and semiconductor design ecosystem to get involved.”

The Inaugural ES Design West

The ESD Alliance will host ES Design West co-located with SEMICON West 2019 at San Francisco’s Moscone Center, July 9-11. Dedicated to promoting the commercial successes of the Design and Design Automation Ecosystem™, ES Design West is the only event in North America that links the electronic system and semiconductor design community with the electronic product manufacturing and supply chain. For more information, visit the ES Design West 2019 website.

About the Electronic System Design Alliance

The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner representing members in the electronic system and semiconductor design ecosystem, is a community that addresses technical, marketing, economic and legislative issues affecting the entire industry. It acts as the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Toshiba Memory Corporation has successfully used the Cadence® CMP Process Optimizer, a model calibration and prediction tool that accurately simulates multi-layer thickness and topography variability for the entire layer stack, to accelerate the delivery of its advanced 3D flash memory devices. With the Cadence solution in place, Toshiba Memory Corporation achieved 95.7 percent accuracy to silicon.

After conducting a thorough competitive evaluation, Toshiba Memory Corporation adopted the Cadence CMP Process Optimizer for its unparalleled feature set that addresses diverse layout topologies of array-based memory designs. The Cadence CMP Process Optimizer is based on a model-based approach versus a traditional, rules-based approach, which enabled Toshiba Memory Corporation to better predict complex, cumulative and long-range effects of chemical mechanical polishing (CMP) effects and CMP yield-limiting hotspots. Also, the Cadence CMP Process Optimizer allowed Toshiba Memory Corporation to perform simulations for the entire design stacks—both the transistor and routing layers—leading to improved accuracy. Toshiba Memory Corporation generated high-precision CMP models with the Cadence CMP Process Optimizer’s innovative capabilities. For more information on the Cadence CMP Process Optimizer, please visit www.cadence.com/go/ccpo.

“Advanced process technologies bring added complexities to the design process, and as a result, CMP effects have become more and more critical for us, particularly for our leading 3D flash memory solutions,” said Susumu Yoshikawa, technology executive, Memory Technology at Toshiba Memory Corporation. “We’ve been particularly impressed by the Cadence CMP Process Optimizer’s unparalleled capabilities, which enabled highly accurate modeling and analysis that we expect to improve product yield and accelerate the delivery of our flash devices.”

The Cadence CMP Process Optimizer offers feature-scale topography prediction and advanced reverse etch-back for accurate modeling and is part of the broader Cadence digital and signoff portfolio. From synthesis through implementation and signoff, the Cadence integrated full-flow digital and signoff tools provide a fast path to design closure and better predictability. The digital and signoff full-flow supports the company’s overall System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

Soitec (Euronext Paris), a designer and manufacturer of innovative semiconductor materials, today announced it is the first materials supplier to join the China Mobile 5G Innovation Center (“Center”), an international alliance chartered to develop 5G communication solutions for China, the world’s largest wireless communications market with 925M mobile subscribers. Both silicon and non-silicon engineered substrates, in which Soitec is the global leader, are essential in bringing to mass deployment 5G mobile communications for applications including self-driving cars, industrial connectivity and virtual reality.

Founded by China Mobile, the world’s largest operator, the Center aims to accelerate the development of 5G by establishing a cross-industry ecosystem, setting up open labs to create new products and applications, and fostering new business and market opportunities. As the first materials supplier to join the Center, Soitec brings its long-standing worldwide partnerships with R&D Centers, fabless semiconductor companies and foundries.

With ongoing investments and advances in capabilities, assets and SOI technology, Soitec’s RF portfolio is 5G-ready and designed to support deployment of 5G solutions across different regions. Soitec’s portfolio features cost-effective SOI and compound material substrates spanning advanced and established technology nodes optimized to balance performance, power efficiency and integration, in less space. Soitec will further support China Mobile through access to Soitec’s engineered substrate development ecosystem.

“As China Mobile works to bring 5G to market, Soitec’s participation in the China Mobile 5G Innovation Center is focused on accelerating the creation and delivery of market-leading 5G material solutions,” said Thomas Piliszczuk, Executive Vice President of Global Strategy for Soitec. “This is a unique opportunity for Soitec to engage with the world’s largest mobile operator and its ecosystem partners. Engineered substrates give foundries, fabless semiconductor companies and IDMs (integrated device manufacturers) the means to improve performance, power, area and cost (PPAC) while also enabling new applications.”

Soitec engineered substrates have been critical in deployment of 4G communication. RF-SOI material is used in 100 percent of smart phones manufactured today and its surface is growing with each new product generation. Also, FD-SOI brings unique RF performance, making it an ideal solution for many applications including mmWave communications such as 5G transceivers as well as enabling full RF and ultra-low-power computing integration for IoT.

GOWIN Semiconductor Corp., an innovator of programmable logic devices, announces the release of GOWIN’s new EDA tool, YunYuan 1.9. With the release of this new toolchain, GOWIN will enable enhanced features and performance capabilities on their current and future FPGA product families.

EDA toolchains are becoming increasingly complex as FPGA applications are integrating more functions for the cloud and endpoint markets. To enable this complexity change, the new toolchain will include Gowin Synthesis, an enhanced front end logic synthesis tool designed and developed by the GOWIN EDA software team. It’s a significant milestone for GOWIN as the total toolchain is now completely designed in-house, allowing for quick quality improvements as well as product updates for customers time to market requirements. While GOWIN’s FPGA’s will be more optimized for IP, performance, and utilization using the new Yun Yuan 1.9 toolchain, the toolchain will additionally support the current Synopsys Synplify Pro synthesis tool already integrated.

“The development of the new synthesis tool is a major step for GOWIN,” said Alan Liu, Director of Software Development, GOWIN Semiconductor. “We can now make tool adjustments in real-time, enhancing the user experience.”

GOWIN EDA (YunYuan®) is an easy-to-use integrated design environment, providing design engineers with a one-stop solution. The complete GUI based environment covers FPGA design entry, code synthesis, place & route, bitstream generation, download, and online debugging of GOWIN FPGA’s on customer’s boards. The new toolchain also incorporates the following updated IP blocks:

Communication:

  • CAN2.0 & CAN-FD IP
  • High-Speed MIPI Interface (1:8 & 1:16 Gear Box)
  • Ethernet 10/100/1000Mhz MAC Controller & Interface to MII/RMII/GMII

Memory Controller:

  • pSRAM Controller IP

Microprocessor:

  • Configurable RISC-V (5-Stage-Pipeline) CPU & System IP

DSP:

  • FIR
  • NLMS Filter
  • FDAF – Frequency Domain Adaptive Filter
  • Cross-Correlation

Synopsys, Inc. (Nasdaq:SNPS) and GLOBALFOUNDRIES (GF) today announced a collaboration to develop a portfolio of automotive Grade 1 temperature (-40C to +150C junction) DesignWare® Foundation, Analog, and Interface IP for the GF 22-nm Fully-Depleted Silicon-On-Insulator (22FDX®) process. By providing IP that is designed for high temperature operation on 22FDX, Synopsys enables designers to reduce their design effort and accelerate AEC-Q100 qualification of system-on-chips (SoCs) for automotive applications such as eMobility, 5G connectivity, advanced driver assistance systems (ADAS), and infotainment. The Synopsys DesignWare IP implements additional automotive design rules for the GF 22FDX process to meet stringent reliability and operation requirements. This latest collaboration complements Synopsys’ broad portfolio of automotive-grade IP that provides ISO 26262 ASIL B Ready or ASIL D Ready certification, AEC-Q100 testing, and quality management.

“Arbe’s ultra-high-resolution radar is leveraging this cutting edge technology that enabled us to create a unique radar solution and provide the missing link for autonomous vehicles and safe driver assistance,” said Avi Bauer, vice president of R&D at Arbe. “We need to work with leading companies who can support our technology innovation. GF’s 22FDX technology, with Synopsys automotive-grade DesignWare IP, will help us meet automotive reliability and operation requirements and is critical to our success.”

“GF’s close, collaborative relationships with leading automotive suppliers and ecosystem partners such as Synopsys have enabled advanced process technology solutions for a broad range of driving system applications,” said Mark Ireland, vice president of ecosystem partnerships at GF. “The combination of our 22FDX process with Synopsys’ DesignWare IP enables our mutual customers to speed the development and certification of their automotive SoCs, while meeting their performance, power, and area targets.”

“Synopsys’ extensive investment in developing automotive-qualified IP for advanced processes, such as GF’s 22FDX, helps designers accelerate their SoC-level qualifications for functional safety, reliability, and automotive quality,” said John Koeter, vice president of marketing for IP at Synopsys. “Our close collaboration with GF mitigates risks for designers integrating DesignWare Foundation, Analog, and Interface IP into low-power, high-performance automotive SoCs on the 22FDX process.”

GLOBALFOUNDRIES & Synopsys at Mobile World Congress 2019

On February 25, 2019, Synopsys will join the GLOBALFOUNDRIES NEXTech Lab Theater Session at MWC19. A panel discussion, with leading industry experts, ​​including Joachim Kunkel, general manager of the Solutions Group at Synopsys, and Mike Cadigan, senior vice president of global sales, business development, customer and design engineering at GF, will offer insights about the importance of intelligent connectivity, the growth, demands, and innovations it is poised to bring, and its impacts across the semiconductor value chain. For more information, visit: https://www.globalfoundries.com/join-gf-mwc19.

Resources

For more information on Synopsys DesignWare IP for automotive Grade 1 temperature operation on GF’s 22FDX process:

Rice University integrated circuit (IC) designers are at Silicon Valley’s premier chip-design conference to unveil technology that is 10 times more reliable than current methods of producing unclonable digital fingerprints for Internet of Things (IoT) devices.

Rice’s Kaiyuan Yang and Dai Li will present their physically unclonable function (PUF) technology today at the 2019 International Solid-State Circuits Conference (ISSCC), a prestigious scientific conference known informally as the “Chip Olympics.” PUF uses a microchip’s physical imperfections to produce unique security keys that can be used to authenticate devices linked to the Internet of Things.

Considering that some experts expect Earth to pass the threshold of 1 trillion internet-connected sensors within five years, there is growing pressure to improve the security of IoT devices.

Yang and Li’s PUF provides a leap in reliability by generating two unique fingerprints for each PUF. This “zero-overhead” method uses the same PUF components to make both keys and does not require extra area and latency because of an innovative design feature that also allows their PUF to be about 15 times more energy efficient than previously published versions.

“Basically each PUF unit can work in two modes,” said Yang, assistant professor of electrical and computer engineering. “In the first mode, it creates one fingerprint, and in the other mode it gives a second fingerprint. Each one is a unique identifier, and dual keys are much better for reliability. On the off chance the device fails in the first mode, it can use the second key. The probability that it will fail in both modes is extremely small.”

As a means of authentication, PUF fingerprints have several of the same advantages as human fingerprints, he said.

“First, they are unique,” Yang said. “You don’t have to worry about two people having the same fingerprint. Second, they are bonded to the individual. You cannot change your fingerprint or copy it to someone else’s finger. And finally, a fingerprint is unclonable. There’s no way to create a new person who has the same fingerprint as someone else.”

PUF-derived encryption keys are also unique, bonded and unclonable. To understand why, it helps to understand that each transistor on a computer chip is incredibly small. More than a billion of them can be crammed onto a chip half the size of a credit card. But for all their precision, microchips are not perfect. The difference between transistors can amount to a few more atoms in one or a few less in another, but those miniscule differences are enough to produce the electronic fingerprints used to make PUF keys.

For a 128-bit key, a PUF device would send request signals to an array of PUF cells comprising several hundred transistors, allocating a one or zero to each bit based on the responses from the PUF cells. Unlike a numeric key that’s stored in a traditional digital format, PUF keys are actively created each time they’re requested, and different keys can be used by activating a different set of transistors.

Adopting PUF would allow chipmakers to inexpensively and securely generate secret keys for encryption as a standard feature on next-generation computer chips for IoT devices like “smart home” thermostats, security cameras and lightbulbs.

Encrypted lightbulbs? If that sounds like overkill, consider that unsecured IoT devices are what three young computer savants assembled by the hundreds of thousands to mount the October 2016 distributed denial-of-service attack that crippled the internet on the East Coast for most of a day.

“The general concept for IoT is to connect physical objects to the internet in order to integrate the physical and cyber worlds,” Yang said. “In most consumer IoT today, the concept isn’t fully realized because many of the devices are powered and almost all use existing IC feature sets that were developed for the mobile market.”

In contrast, the devices coming out of research labs like Yang’s are designed for IoT from the ground up. Measuring just a few millimeters in size, the latest IoT prototypes can pack a processor, flash memory, wireless transmitter, antenna, one or more sensors, batteries and more into an area the size of a grain of rice.

PUF is not a new idea for IoT security, but Yang and Li’s version of PUF is unique in terms of reliability, energy efficiency and the amount of area it would take to implement on a chip. For starters, Yang said the performance gains were measured in tests at military-grade temperatures ranging from 125 degrees Celsius to minus 55 degrees Celsius and when supply voltage dropped by up to 50 percent.

“If even one transistor behaves abnormally under varying environmental conditions, the device will produce the wrong key, and it will look like an inauthentic device,” Yang said. “For that reason, reliability, or stability, is the most important measure for PUF.”

Energy efficiency also is important for IoT, where devices can be expected to run for a decade on a single battery charge. In Yang and Li’s PUF, keys are created using a static voltage rather than by actively powering up the transistor. It’s counterintuitive that the static approach would be more energy efficient because it’s the equivalent of leaving the lights on 24/7 rather than flicking the switch to get a quick glance of the room.

“Normally, people have sleep mode activated, and when they want to create a key, they activate the transistor, switch it once and then put it to sleep again,” Yang said. “In our design, the PUF module is always on, but it takes very little power, even less than a conventional system in sleep mode.”

On-chip area — the amount of space and expense manufacturers would have to allocate to put the PUF device on a production chip — is the third metric where they outperform previously reported work. Their design occupied 2.37 square micrometers to generate one bit on prototypes produced using 65-nanometer complementary metal-oxide-semiconductor (CMOS) technology.

The research was funded by Rice University.

Researchers at CEA-Leti and Stanford University have developed the world’s first circuit integrating multiple-bit non-volatile memory (NVM) technology called Resistive RAM (RRAM) with silicon computing units, as well as new memory resiliency features that provide 2.3-times the capacity of existing RRAM. Target applications include energy-efficient, smart-sensor nodes to support artificial intelligence on the Internet of Things, or “edge AI”.

The proof-of-concept chip has been validated for a wide variety of applications (machine learning, control, security). Designed by a Stanford team led by Professors Subhasish Mitra and H.-S. Philip Wong and realized in CEA-Leti’s cleanroom in Grenoble, France, the chip monolithically integrates two heterogeneous technologies: 18 kilobytes (KB) of on-chip RRAM on top of commercial 130nm silicon CMOS with a 16-bit general-purpose microcontroller core with 8KB of SRAM.

The new chip delivers 10-times better energy efficiency (at similar speed) versus standard embedded FLASH, thanks to its low operation energy, as well as ultra-fast and energy-efficient transitions from on mode to off mode and vice versa. To save energy, smart-sensor nodes must turn themselves off. Non-volatility, which enables memories to retain data when power is off, is thus becoming an essential on-chip memory characteristic for edge nodes. The design of 2.3 bits/cell RRAM enables higher memory density (NVM dense integration) yielding better application results: 2.3x better neural network inference accuracy, for example, compared to a 1-bit/cell equivalent memory.

The technology was presented on Feb. 19, at the International Solid-State Circuits Conference (ISSCC) 2019 in San Francisco in a paper titled, “A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques”.

But NVM technologies (RRAM and others) suffer from write failures. Such write failures have catastrophic impact at the application level and significantly diminish the usefulness of NVM such as RRAM. The CEA-Leti and Stanford team created a new technique called ENDURER that overcomes this major challenge. This gives the chip a 10-year functional lifetime when continuously running inference with the Modified National Institute of Standards and Technology (MNIST) database, for example.

“The Stanford/CEA-Leti team demonstrated a complete chip that stores multiple bits per on-chip RRAM cell. Stored information is correctly processed when compared with previous demonstrations using standalone RRAM or a few cells in a RAM array,” said Thomas Ernst, Leti’s chief scientist for silicon components and technologies. “This multi-bit storage improves the accuracy of neural network inference, a vital component of AI.”

Mitra said the chip demonstrates several industry firsts for RRAM technology. These include new algorithms that achieve multiple bits-per-cell RRAM at the full memory level, new techniques that exploit RRAM features as well as application characteristics to demonstrate the effectiveness of multiple bits-per-cell RRAM at the computing system level, and new resilience techniques that achieve a useful lifetime for RRAM-based computing systems.

“This is only possible with a unique team with end-to-end expertise across technology, circuits, architecture, and applications,” he said. “The Stanford SystemX Alliance and the Carnot Chair of Excellence in NanoSystems at CEA-Leti enabled such a unique collaboration.”

GLOBALFOUNDRIES (GF) and Dolphin Integration, a provider of semiconductor IP, today announced a collaboration to develop a series of adaptive body bias (ABB) solutions to improve the energy efficiency and reliability of system-on-chip (SoC) on GF’s 22nm FD-SOI (22FDX) process technology for a wide range of high-growth applications such as 5G, IoT and automotive.

As part of the collaboration, Dolphin Integration and GF are working together to develop a series of off-the-shelf ABB solutions for accelerating and easing body bias implementation on SoC designs. ABB is a unique 22FDX feature that enables designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects to achieve additional performance, power, area and cost improvements beyond those from scaling alone.

The ABB solutions in development consist of self-contained IPs embedding the body bias voltage regulation, PVT and aging monitors and control loop as well as complete design methodologies to fully leverage the benefits of corner tightening. GF’s 22FDX technology offers the industry’s lowest static and dynamic power consumption. With automated transistor body biasing adjustment, Dolphin Integration can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs.

“We have been working with GF for more than two years on advanced and configurable power management IPs for low power and energy efficient applications,” said Philippe Berger, CEO at Dolphin Integration. “Through our ongoing collaboration with GF, we are focused on creating turnkey IP solutions that allow designers to realize the full benefit of FD-SOI for any SoC design in 22FDX.”

“In order to simplify our client designs and shorten their time-to-market, GF and our ecosystem partners are helping to pave the way to future performance standards in 5G, IoT and automotive,” said Mark Ireland, vice president of Ecosystem at GF. “With the support of silicon IP providers like Dolphin Integration, new power, performance and reliability design infrastructures will be available to customers to fully leverage the benefits of GF’s 22FDX technology.”

Design kits with turnkey adaptive body bias solutions on GF’s 22FDX will be available starting in Q2 2019.

eSilicon, a provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the achievement of multiple milestones related to the company’s growth in the tier one FinFET ASIC market, serving high-bandwidth networking, high-performance computing, AI and 5G infrastructure.

Critical requirements to serve these markets include leading-edge, high-performance, differentiating semiconductor IP that is validated in advanced process nodes, a track record of successful design and fabrication of complex, FinFET-class ASICs and expertise in the design and manufacture of 2.5D package assemblies, including the integration of HBM memory stacks.

In the fall of last year, eSilicon announced availability of its neuASIC™ IP platform for AI ASIC design. The innovative IP platform includes an HBM2 PHY and AI mega/giga cells, including a convolution engine and accelerator builder software, all verified in 7nm technology. In that same time frame, the company announced that its 56G long-reach 7nm DSP SerDes was available for licensing.

In January, 2019, eSilicon announced a new high-performance test system to facilitate customer validation of its SerDes IP. At the recent DesignConshow, eSilicon demonstrated the new test system and its SerDes driving a five-meter copper cable at 56Gbps with very low error rates. Several customer engagements are underway with this SerDes IP, and customer feedback is validating its best-in-class capabilities. Also in January, eSilicon announced the formation of a technical advisory board for its AI initiatives staffed by three prominent technologists from academia and industry.

The company is in active production bring-up with two FinFET designs, including 2.5D technology utilizing its HBM2 PHY. All performance parameters are being met and both designs are on track to achieve full-scale production this year. One of the designs represents the largest ASIC eSilicon has ever built. It is believed to be the largest chip the foundry has ever produced as well.

“Our customers demand best-in-class IP, advanced ASIC and packaging expertise and the resources and technical depth to facilitate production bring-up of the final device,” said Hugh Durdan, vice president of strategy and products at eSilicon. “I am pleased to say we are delivering on all fronts. Recently, a tier one customer reported that they were usually quite critical of all IP. They went on to say they could find nothing to criticize after detailed evaluation of our SerDes.”

eSilicon will be presenting “A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET” at ISSCC in San Francisco on February 18. The company will be demonstrating its SerDes live at ISSCC that day as well. You can also find eSilicon at OFC in San Diego from March 5-7 (booth #5416), where the company will present two high-speed SerDes demonstrations and a demonstration if its HBM2 PHY.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that GLOBALFOUNDRIES (GF) has chosen Cadence as the primary EDA tool vendor for use in Avera Semi, a GF subsidiary, for advanced node chip design projects. The Avera Semi engineering team has come to rely on the features, capacity, speed and scalability of the Cadence® digital and signoff, system and verification, custom IC and PCB design and analysis tools and flows. Establishing Cadence as their primary vendor has enabled them to improve engineering productivity.

Avera Semi has successfully completed several large, complex 12nm and 14nm tapeouts and delivered production designs using Cadence flagship solutions such as the Innovus™ Implementation System, the Genus™Synthesis Solution, the Tempus™ Timing Signoff Solution and Xcelium™Parallel Logic Simulation as well as the Virtuoso® custom IC design platform, Spectre® circuit simulation platform and Allegro® and Sigrity™tools, which are part of following product categories:

  • Digital and Signoff: The parallelized, integrated Cadence digital and signoff solutions provided Avera Semi with a trusted design flow to achieve industry-leading power, performance and area (PPA) results with integrated signoff accuracy for designs with more than 500M instances, complex clocking requirements and chip sizes at the mask reticle limit.
  • System and Verification: The Cadence Verification Suite helped the Avera Semi verification team find bugs more efficiently, quickly implement and bring up complex testbenches for faster project completion and fuel testbench automation, analysis and reuse for increased productivity.
  • Custom IC/Analog Design: The comprehensive analog and mixed-signal simulation capabilities in the Cadence custom IC design platform enabled Avera Semi to consistently, accurately and quickly design and verify complex IP such as the Avera Semi 112G Serial Link. Additionally, the tight integration of Cadence physical verification and design-for-manufacturing (DFM) tools within the Cadence Virtuoso IC design platform accelerated design and implementation.
  • PCB Design and Analysis: Cadence’s PCB design and analysis tools helped Avera Semi achieve a smooth and efficient interface between the chip and packaging teams, helping to manage and track engineering change requests. The tools’ customizability enabled Avera Semi to automate the numerous properties associated with a package, reducing manual errors and design cycle time.

“Today’s announcement is another solid step in our collaborative journey to achieve a higher level of productivity through Cadence’s design flow,” said Kevin O’Buckley, GM at Avera Semi. “We have already deployed the Cadence flows to complete a number of successful production designs for our customers using the GF 12nm and 14nm FinFET process technologies and will extend our collaboration with Cadence on advanced nodes. Standardizing on Cadence’s custom, digital and IC package flows and verification solutions will help us master new challenges encountered at advanced nodes and expand our leadership in designs for data centers, wired communications, and machine learning and artificial intelligence applications.”

“Avera Semi uses Cadence as its primary supplier due to many years of successful collaborations on large, complex designs that met evolving market demands,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “We are always working to optimize design flow speed, throughput and provide differentiated tool features to deliver best-in-class PPA to customers. As we expand upon our longstanding relationship with Avera Semi, their customers can also benefit from our continued innovation and dedication to advancing ASIC design.”