Category Archives: Packaging

Alliance Memory today announced that it is offering several end-of-life 8G DDR3L SDRAMs for which Micron Technology Inc. announced a last time buy date of Jan. 13, 2019. For three of the devices, the company is also offering versions with Alliance Memory part numbers that use the same genuine single-die Micron silicon as the Micron-numbered parts.

The following Micron 8G DDR3L SDRAMs are now available from Alliance Memory:

Micron Part Number Alliance Memory Identical Replacement
MT41K512M16HA-107:A N/A
MT41K512M16HA-107 IT:A N/A
MT41K512M16HA-125:A AS4C512M16D3L-12BCN
MT41K1G8SN-125:A AS4C1G8MD3L-12BCN
MT41K512M16HA-125 IT:A * AS4C512M16D3L-12BIN
*Only available in Alliance Memory branded version.

“We are committed to supporting our customers’ legacy SDRAM needs,” said David Bagby, president and CEO of Alliance Memory. “These are genuine Micron parts with Micron part numbers, and we’re pleased to be extending their life cycle by making them available from Alliance Memory.”

By Serena Brischetto

SEMI met with Jay Zhang, business development director at Corning Incorporated, to discuss recent innovations at Corning that allow fine granularity CTE engineering as well as high Young’s modulus. We also talked about the impact of this work on in-process warp control, as well as the associated production methodology that provides rapid prototyping and high-volume manufacturing. We spoke ahead of his presentation at the 3D & Systems Summit, 28-30 January, 2019, in Dresden, Germany. To register for the event, please click here.

SEMI: What is Corning’s mission and vision and your role within the company?

Zhang: Corning is one of the world’s leading innovators in materials science with a track record of 165+ years of life-changing innovations. We excel in glass science, ceramics science, and optical physics and succeed through sustained investment in RD&E. Our products include Corning® Gorilla® glass, a durable material used on more than six billion mobile devices worldwide, and industry-leading LCD glass for display applications.

We have recently dedicated a unit of the company called Precision Glass Solutions to address the emerging need for glass in the semiconductor industry. Here we apply Corning’s long history of glass science expertise and deep customer relationships in consumer electronics to support cutting-edge applications like wafer-level optics for precise 3D sensing and carrier solutions for temporary bonding applications in semiconductor manufacturing. It’s our most recent work in the Carrier Solutions product line that I’m excited to present: a new carrier glass product optimized for fan-out, called Corning Advanced Packaging Carriers.

SEMI: What projects are you currently working on that you think will make a difference in 2019?

Zhang: My team is excited to introduce Corning Advanced Packaging Carriers this year. This is a new line of product within our portfolio of Carrier Solutions. These ultra-flat glass carriers are specially developed to reduce customers’ challenge of in-process warp by up to 40 percent, which in turn helps advanced packaging customers achieve better yield.

Corning Advanced Packaging Carriers feature high-stiffness properties and are available in a wide range of coefficients of thermal expansion (CTE) in fine granularity. These attributes help customers select an ideal glass carrier that will minimize in-process warp for their package. Furthermore, we make sample quantities of these carriers available in just four to six weeks to help maximize efficiency during customers’ R&D process.

My team is excited about the potential of this new product, but also encouraged by our results. We have already supplied this product and have heard from one of the largest semiconductor companies in Taiwan that it has reduced in-process warp by as much as 150μm.

SEMI: Your presentation at the 3D & Systems Summit will focus on Agile Manufacturing of Glass Carriers for Advanced Packaging. What exactly will you be sharing?

Zhang: There is a lot of interest right now in using glass as a carrier substrate in temporary bonding applications in advanced semiconductor packaging – especially in fan-out processes. We also know that in-process warp is a significant challenge to companies pursuing advanced packaging because different CTE materials are added during the process.

My team has done a lot of work to understand the impact that an ideal CTE glass carrier substrate can have on minimizing in-process warp. We have studied the available levers – both theoretical and in real-life fab environments – that can help address this challenge. I will present our findings on how it is possible to select a glass carrier with the ideal CTE and Young’s modulus to reduce in-process warp by up to 40 percent, and how Corning has developed an agile manufacturing platform to support customers with these ideal carriers from their R&D stage through mass production.

SEMI: What do you think will be a hot topic in the next few years?

Zhang: We expect high-end fanout technology to address more applications beyond just mobile APs. There is also an interesting dynamic playing out between wafer-level and panel-level fan-out technologies. Corning is active in both areas. In developing and offering high performance glass carriers, we hope to help enable our customers to expand the fan-out applications space.

SEMI: What are your expectations regarding the summit in Dresden, and why do you recommend your members and other industry leaders to attend the 2019 3D & Systems Summit?

Zhang: Europe is where some of the most advanced packaging technologies are born. Fan-out also saw early commercialization there. I hope to meet many scientists and technologists at 3D & Systems Summit and exchange technical and business ideas. We also hope to get early feedback from other attendees about the value of our new product offering.

Serena Brischetto is a marketing and communications manager at SEMI Europe.

This originally appeared on the SEMI blog.

Corning Incorporated (NYSE: GLW) today introduced its latest breakthrough in glass substrates for the semiconductor industry – Advanced Packaging Carriers. This enhanced line of glass carrier wafers is optimized for fan-out processes, a type of cutting-edge semiconductor packaging that enables smaller, faster chips for consumer electronics, automobiles, and other connected devices.

Corning Advanced Packaging Carriers feature three significant improvements:

– Fine granularity in a wide range of available coefficients of thermal expansion (CTE)
– High stiffness composition
– Rapid sampling availability

These attributes are important for customers pursuing fan-out packaging because:

– Fine granularity enables customers to more easily select the optimal CTE needed to minimize in-process warp. Precise CTE offerings thereby help reduce customers’ development cycle time.
– Corning’s high stiffness compositions help further reduce in-process warp. Minimizing warp helps maximize their yield of packaged chips.
– Rapid sampling availability also contributes to reduced development time and enables customers to move to the mass production phase more quickly.

“We created Corning Advanced Packaging Carriers especially for our customers pursuing the most challenging types of chip manufacturing processes,” said Rustom Desai, commercial director of Corning Precision Glass Solutions.

“Our deep technical ties in the semiconductor industry, combined with Corning’s core competencies in glass science and manufacturing, enabled us to create an innovative product that can help customers maximize efficiency throughout their development process and mass production ramp,” Desai said.

Corning’s semiconductor glass carriers are one of several products in Corning’s portfolio of Precision Glass Solutions designed to address the emerging need for glass across microelectronics. This portfolio provides customers with a one-stop shop for world-class capabilities including proprietary glass and ceramic manufacturing platforms, finishing processes, bonding technologies, best-in-class metrology, automated laser glass-processing, and optical design expertise.

Soitec (Euronext Paris), a designer and manufacturer of semiconductor materials, announced today an expanded collaboration with Samsung Foundry to ensure the volume supply of fully depleted silicon-on-insulator (FD-SOI) wafers. This agreement extends the current  partnership and provides a solid foundation for both companies to strengthen the FD-SOI supply chain and guarantee high-volume manufacturing for customers.

With the leadership from the two companies, today FD-SOI is one of the standard technologies for cost-effective, low-power devices used in high-volume consumer, 4G/5G smartphones, IoT, and automotive applications. The agreement is built on the existing close relationship between the companies and guarantees wafer supply for Samsung’s FD-SOI platform starting with 28FDS process.

“This strategic agreement validates today’s high-volume manufacturing adoption of FD-SOI,” said Christophe Maleville, Soitec’s Executive Vice President, Digital Electronics Business Unit. “Soitec is ready to support Samsung’s current and long-term growth for ultra-low power, performance-on-demand FD-SOI solutions.”

FD-SOI relies on a very unique substrate whose layer thickness is controlled at the atomic scale. FD-SOI offers remarkable transistor performance in terms of power, performance, area and cost tradeoffs (PPAC), making it possible to cover low-power to high-performance digital applications with a single technology platform. FD-SOI delivers numerous unique advantages including the ability to mitigate process, temperature, voltage and aging variations through body bias, near-threshold supply capability, ultra-low sensitivity to radiation, and very high intrinsic transistor speed, making it most likely the fastest RF-CMOS technology on the market.

“Samsung has been committed to delivering transformative industry leading technologies.  FD-SOI is currently setting a new standard in many high-growth applications including IoT with ultra-low-power devices, automotive systems such as vision processors for ADAS and infotainment, and mobile connectivity from 5G smartphones to wearable electronics,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “Through this agreement with Soitec, our long-term strategic partner, we hope to lay the foundation for steady supply to meet high-volume demands of current and future customers.”

By Rohit Sharma

Constant coverage of an invigorating topic like machine intelligence in the media often urges us to consider its use in EDA technology. As is often the case, there are many myths and falsehoods that consume our time and effort when trying to apply machine intelligence to EDA. This article aims to uncover the myths and to provide helpful advice on applying machine intelligence to your EDA project or product.

Value Proposition

First, there needs to be a clear value proposition for adding machine intelligence to an EDA product. Using machine intelligence to create a me-too product adds no value. EDA customers are too busy to understand or care about an EDA tool’s underlying technology. They just want to use the tool and get results. If the tool delivers value, if it delivers tangible benefits, then they’ll use it. Otherwise, they won’t.

Currently, EDA tool developers are already experimenting with AI and machine intelligence without considering this fundamental truth – without a higher-end objective. AI must deliver something better or new, whether a speed advantage, a performance advantage, new features, new insights, or perhaps even something pleasantly surprising. Before you write a single line of AI-enhanced code, you need to clearly understand how AI will enhance the product. What is the value proposition?

Use Model

There’s a major barrier to customer adoption of AI and machine intelligence technology for EDA tools: EDA users are averse to make decisions based on probabilistic results. Instead, half a century of EDA tool use has conditioned them to expect deterministic outcomes from their tools.

Back in 2003, a prominent visionary and EDA investor was quoted in an interview, saying: “If I open my eyes five years from now, all static analysis in VLSI will be statistical.” Many EDA luminaries have been proven wrong over time for betting that EDA users will accept statistical results. As enthusiastic as I am about using machine intelligence to improve EDA tools, I must urge caution based on the history of EDA failures that employed a probabilistic use model. Decision-makers and EDA tool users want to see deterministic answers to questions about yield or slack, not probabilistic ones.

Our experiences at Paripath in developing the PASER (Paripath Accelerated Simulation Environment) tool also bear this out. We discovered that delivering results 50x faster but with 92% accuracy was simply not good enough for end users. EDA users only started to use PASER when its answers became 98+% accurate. To be adopted in the production flow, the tool had to deliver 99% accuracy.

Data Engineering

There are specific ways to achieve these accuracy goals. The first is data engineering. Machine intelligence is a new approach to EDA tool development and it needs to be trained on a data set. If the data is poor or incomplete, training will create an inaccurate model. Fundamental software-development rules still apply. Garbage in, garbage out.

Without good training data, there’s no way for you to build good neural-network models. If you train a model with garbage data, you’ll get a garbage model. You must cleanse the data before you use it for training. Otherwise, the model will draw inaccurate conclusions and customers will not use your tool. The model is not to blame here. The model’s not wrong. The problem lies in poor data engineering, poor data cleansing, and a lack of discipline to prepare input data.

High Dimensionality

Next, machine intelligence has a unique ability to quickly solve problems of high dimensionality. Pure EDA problems often have high dimensionality. Over the years, EDA developers have perfected the art of segmenting the problems into sequencing solutions with lower dimension. Machine intelligence technology can handle problems with thousands of dimensions, but you need to be careful when tackling problems that have high dimensionality. Too many dimensions can produce confused or inaccurate results with AI and deep-learning technology.

It helps to visualize the problem and to analyze the data set before using the data to train an AI-enhanced EDA tool. Several visualization methods can help. For example, t-SNE (t-Distributed Stochastic Neighbor Embedding) lets you reduce a data set’s dimensionality from a very large number to a much lower number. Figure 1 shows a high-dimension dataset with a dimensionality of 2000, which has been reduced to a low dimensionality of 3.

Figure 1: Visualizing the Data Set with Lower Dimensionality

Reducing the dimensionality of a data set to 3 using t-SNE and visualization allows you to quickly see whether the data set defines an easy or a difficult problem. If the problem is difficult, you’ll likely need to lower the problem’s and the data set’s dimensionality before using the data to train a neural network.

Technology Selection

One factor that determines whether it will be easy or difficult to incorporate machine intelligence into your EDA tool is your choice of AI development tools. AI researchers have developed a long list of frameworks, libraries, and languages that they use to develop AI and machine-learning software. Frameworks and libraries such as TensorFlow, Caffe and MXNet are most popular for developing deep-learning models.

However, these tools are not yet popular with the EDA development community. The languages of choice in the EDA community are traditionally C and C++ for development and Tcl for prototyping and creating user interfaces. The rest of the software world has moved on to newer development languages such as Python, Java, R, and such. Moreover, machine-learning development segments into two distinct processes: training (i.e. generating the model) and inference (i.e. using the model).

Another question to consider is where to generate the model – at the vendor site or the customer site?

Consequently, fitting AI and deep-learning development into EDA development environments can feel like fitting a square peg into a round hole. You may need to create corners in your hole.

EDA is a very small player in the overall software market. Relatively few software developers are familiar with writing EDA tools. It’s best to select AI and deep-learning development tools that can provide some sort of interface that’s compatible with EDA’s development tools of choice. Some AI frameworks have lower-level C and C++ interface layers that provide a familiar entry point for experienced EDA developers.

At Paripath, we chose TensorFlow for exactly this reason. TensorFlow has a lower-level C/C++ interface. Although the resulting development path becomes a longer one using this approach, it’s a more familiar path for EDA developers and therefore it’s a path that can ultimately lead your EDA development team to success. An elaborate study of comparing these frameworks has been published in the book Machine Intelligence in Design Automation.

Integration into Legacy Systems

When you understand the value that you expect machine intelligence to add to your new EDA tool, when you’ve cleansed and then analyzed the data set, and when you have selected an appropriate set of development tools, you’re finally ready to add machine intelligence to your EDA development. There are two use models for AI-enhanced EDA tools. The first uses a trained model to guide the EDA tool’s decision-making. In this use case, the trained neural network doesn’t change. The software’s accuracy doesn’t improve with use unless the company that developed the EDA tool retrains the underlying neural network. This use case follows the familiar, existing use case associated with EDA tools developed using deterministic algorithms.

For the second use case, the end user is able to retrain the underlying neural network, which allows the EDA tool to produce better, more accurate results over time. This use case produces a win/win situation because end users are able to hone their tools and improve them over time, without help from the EDA tool vendor’s application engineers. If the retrained models are also sent back to the EDA developer for incorporation into newer versions of the tool, all users benefit from other users’ training data.

It’s not clear how you’d support this second use case in the current EDA business environment where most data sets are proprietary and are carefully guarded. Most large EDA tool customers want to keep their data in house under tight control. Even with this somewhat restrictive situation, however, EDA tools benefit from the incorporation of machine intelligence because each EDA tool customer can customize the tool and improve its results.

Machine intelligence has much to add to EDA tools’ capabilities. Only time will tell if the customers want and will accept these new capabilities.

Rohit Sharma, founder and CEO of Paripath Inc., is an engineer, author and entrepreneur. He has published many papers in international conferences and journals. He has contributed to electronic design automation domain for over 20 years learning, improvising and designing solutions. He is passionate about many technical topics including machine learning, analysis, characterization, and modeling. It led him to architect guna – an advanced characterization software for modern nodes. 

Sharma has written a book titled “Machine Intelligence for Design Automation.” You can download code examples and other information here.

This originally appeared on the SEMI blog.

IC Insights is in the process of completing its forecast and analysis of the IC industry and will present its new findings in The McClean Report 2019, which will be published later this month.  Among the semiconductor industry data included in the new 400+ page report is an analysis of semiconductor merger and acquisition agreements.

The historic flood of merger and acquisition agreements that swept through the semiconductor industry in 2015 and 2016 slowed significantly in 2017 and then eased back further in 2018, but the total value of M&A deals reached in the last year was still nearly more than twice the annual average during the first half of this decade.  Acquisition agreements reached in 2018 for semiconductor companies, business units, product lines, and related assets had a combined value of $23.2 billion compared to $28.1 billion in 2017, based on data compiled by IC Insights.  The values of M&A deals struck in these years were significantly less than the record-high $107.3 billion set in 2015 (Figure 1).

Figure 1

The original 2016 M&A total of $100.4 billion was lowered by $41.1 billion to $59.3 billion because several major acquisition agreements were not completed, including the largest proposed deal ever in semiconductor history—Qualcomm’s planned purchase of NXP Semiconductor for $39 billion, which was raised to $44 billion before being canceled in July 2018.  Prior to the explosion of semiconductor acquisitions that erupted four years ago, M&A agreements in the chip industry had a total annual average value of $12.6 billion in the 2010-2014 timeperiod.

The two largest acquisition agreements in 2018 accounted for about 65% of the M&A total in the year.  In March 2018, fabless mixed-signal IC and power discrete semiconductor supplier Microsemi agreed to be acquired by Microchip Technology for $8.35 billion in cash.  Microchip said the purchase of Microsemi would boost its position in computing, communications, and wireless systems applications.  The transaction was completed in May 2018.  Fabless mixed-signal IC supplier Integrated Device Technology (IDT) agreed in September 2018 to be purchased by Renesas Electronics for $6.7 billion in cash.  Renesas believes the IDT acquisition will strengthen its position in automotive ICs for advanced driver-assistance systems and autonomous vehicles.  The IDT purchase is expected to be completed by June 2019.

Just two other semiconductor acquisition announcements in 2018 had values of more than $1 billion.  In October 2018, memory maker Micron Technology said it would exercise an option to acquire full ownership of its IM Flash Technology joint venture from Intel for about $1.5 billion in cash. Micron has started the process of buying Intel’s non-controlling interest in the non-volatile memory manufacturing and development joint venture, located in Lehi, Utah.  The transaction is expected to be completed in 2H19.  In September 2018, China’s largest contract manufacturer of smartphones, Wingtech Technology, began acquiring shares of Nexperia, a Dutch-based supplier of standard logic and discrete semiconductors that was spun out of NXP in 2017 with the financial backing of Chinese investors.   Wingtech launched two rounds of share purchases from the Chinese owners of Nexperia with a combined value of nearly $3.8 billion.  The company hopes to take majority ownership of Nexperia (about 76% of the shares) in 2019.

Rambus Inc. today announced it has acquired the assets of Diablo Technologies to broaden its portfolio in the hybrid DRAM and Flash memory markets. These patented innovations augment the existing Rambus NVDIMM portfolio and complement its high-bandwidth, low-power memory technologies. Specific terms of the deal are not disclosed.

For over ten years, Diablo Technologies was a pioneer in the development of NVDIMM technologies for high-speed, low-power, and low-latency bridging and switching products targeted at the server and storage markets. Having developed memory buffer and software solutions leveraging an all-Flash memory sub-system, Diablo Technologies enabled an architecture to rewrite the rules of data center performance and economics. Rambus’ investment in these technology areas provide a foundation for integrating existing DRAM and Flash along with emerging memories into advanced hybrid memory systems in the future.

Expanding emerging memory technology for high memory bandwidth interfaces is key to Rambus’ strategic core business. The company has also been collaborating with IBM to research hybrid memory systems, as announced previously.

“Adding these breakthrough innovations from Diablo Technologies will continue to grow Rambus’ leadership in non-volatile and hybrid DRAM and Flash memory technologies with foundational patents,” said Kit Rodgers, SVP of Technology Partnerships and Corporate Development, Rambus. “Diablo Technology’s patented innovations were ahead of their time and nicely complement our offerings for existing and new customers.”

Rudolph Technologies, Inc. (NYSE: RTEC) announced today that it has received orders for over $15 million of legacy and new process control systems from a memory manufacturer based in Asia. The systems will be used by a top-tier memory chip maker as they rapidly transition high-end DRAM (DDR4, DDR5) and HBM DRAM packaging from wire bonding to advanced packaging architectures. The shift from wire bonding is needed to achieve higher data speeds, superior power distribution and thermal properties using copper pillars, micro-bumps, and through silicon vias (TSVs) for stacked chip-to-chip interconnects.

Delivery of systems will be completed by the end of the first quarter, with additional orders expected throughout 2019 as memory manufacturers transition their high-speed DRAM from wire-bonded architecture to advanced packaging.

“Rudolph began working with our customers’ R&D teams nearly ten years ago to develop 2D/3D measurements of the emerging copper bump process. That long-term customer engagement has resulted in systems and software that we believe to be the industry standard for advanced packaging metrology,” stated Cleon Chan, vice president of global field operations at Rudolph. “Stacking die using TSVs and micro-bumps for HBM DRAM packages requires precise control of the copper features that will ultimately make the electrical connections between the stacked memory chips and the logic chip in the same package. After significant development in the package and the process control methods, these devices are now beginning high-volume manufacturing, which is being driven by the data speed and capacity demands from big data servers and graphics applications. These new, non-wire bonded memory architectures are creating a very healthy demand for our back-end process control systems. This customer is also using Rudolph systems for post-saw film-frame inspection looking for package defects.”

A combination of Rudolph’s 2D/3D inspection systems and metal metrology systems provide a total process control solution to help assure that height, diameter, location and coplanarity of copper micro-bumps, pillar bumps, and TSVs are precisely controlled. After the packages are molded and separated by sawing, additional Rudolph inspection systems provide outgoing quality checks for sidewall delamination and/or hairline cracks, which are considered killer defects for advanced memory packages.

By Emmy Yi

SEMI Taiwan Testing Committee founded to strengthen the last line of defense to ensure the reliability of advanced semiconductor applications.

Mobile, high-performance computing (HPC), automotive, and IoT – the four future growth drivers of semiconductor industry, plus the additional boost from artificial intelligence (AI) and 5G – will spur exponential demand for multi-function and high-performance chips. Today, a 3D IC semiconductor structure is beginning to integrate multiple chips to extend functionality and performance, making heterogeneous integration an irreversible trend.

As the number of chips integrated in a single package increases, the structural complexity also rises. Not only will this make identifying chip defects harder, but the compatibility and interconnection between components will also introduce uncertainties that can undermine the reliability of the final ICs. Add to these challenges the need for tight cost control and a faster time to market, and it’s clear that semiconductor testing requires disruptive, innovative change. Traditional final-product testing focusing on finished components is now giving way to wafer- and system-level testing.

In addition, the traditional notion of design for testing, an approach that enhances testing controllability and observability, is now coupled with the imperative to test for design, which emphasizes drawing analytics insights from collected test data to help reduce design errors and shorten development cycles. Going forward, the relationship among design, manufacturing, packaging, and testing will no longer be un-directional. Instead, it will be a cycle of continuous improvement.

This paradigm shift in semiconductor testing, however, will also create a need for new industry standards and regulations, elevate visibility and security levels for shared data, require the optimization of testing time and costs, and lead to a shortage of testing professionals. Solving all these issues will require a joint effort by the industry and academia.

“With leading technologies and $4.7 billion in market value, Taiwan still holds the top spot in global semiconductor testing market,” said Terry Tsao, President of SEMI Taiwan. “When testing extends beyond the manufacturing process, it can play a critical role in ensuring quality throughout the entire life cycle from design and manufacturing to system integration while maintaining effective controls on development costs and schedules. Taiwan’s semiconductor industry is in dire need of a common testing platform to enable the cross-disciplinary collaboration necessary for technical breakthroughs.”

The new SEMI Taiwan Testing Committee was formed to meet that need, gathering testing experts and academics from MediaTek, Intel, NXP Semiconductors, TSMC, UMC, ASE Technology, SPIL, KYEC, Teradyne, Advantest, FormFactor, MJC, Synopsys, Cadence, Mentor, and National Tsing Hua University to collaborate in building a complete testing ecosystem. The committee addresses common technical challenges faced by the industry and cultivates next-generation testing professionals to enable Taiwan to maintain its global leadership in semiconductor testing.

The SEMI Taiwan Testing Platform spans communities, expositions, programs, events, networking, business matching, advocacy, and market and technology insights. For more information about the SEMI Taiwan Testing platform, please contact Elaine Lee ([email protected]) or Ana Li ([email protected]).

Emmy Yi is a marketing specialist at SEMI Taiwan.  

This story originally appeared on the SEMI blog.

IC Insights is in the process of completing its forecast and analysis of the IC industry and will present its new findings in The McClean Report 2019, which will be published later this month.  Among the semiconductor industry data included in the new 400+ page report is an in-depth analysis of semiconductor capital spending.

The semiconductor industry is expected to allocate the largest portion of its capex spending for flash memory again in 2019, marking the third consecutive year that flash has led all other segments in spending (Figure 1).  Flash memory trailed the foundry segment in capex in 2016, but took an extra-large jump in 2017, growing 92% to $27.6 billion and increased another 16% to $31.9 billion in 2018 as manufacturers expanded and upgraded their production lines for 3D NAND to meet growing demand.  With much of the expansion now completed or expected to be wrapped up in 2019, flash capex is forecast to decline 18% this year to $26.0 billion, which still is a very healthy spending level.

Figure 1

•    In 2018, SK Hynix completed and opened M15 its new wafer fab facility in Cheongju, South Korea.  First devices produced from the factory were 72-layer 3D NAND flash.

•    Micron allocated significant resources to upgrade its two existing flash fabs in Singapore and broke ground on construction of a third NAND wafer fab there.

•    Toshiba Memory completed construction of a new 300mm wafer plant (Fab 6) at its Yokkaichi site in 1H18.  Operations at Phase 1 of the facility are expected to begin in early 2019.  Also, Toshiba announced that its next flash memory fab after Fab 6 would be located in Kitakami, Iwate.  The company broke ground on this fab in July 2018.

•    XMC/Yangtze River Storage Technology (YMTC), which is owned by Tsinghua Unigroup, completed construction of its new fab, installed equipment, and began small-volume production of 32-layer 3D NAND flash.

•    Samsung and all of the other “legacy” flash suppliers are well aware of the big plans that China has to be a player in the 3D NAND flash market.  Samsung will continue to invest heavily to stay far ahead of existing competitors or new startups and maintain its competitive edge against any who think they can wrestle marketshare away.  Samsung spent $13.0 billion on flash capex in 2017 and $9.0 billion in 2018, accounting for 28% of the total $31.9 billion in flash memory capital spending last year.  IC Insights estimates Samsung will spend another $7.0 billion for flash capex in 2019.