Category Archives: Packaging

Ever-growing data generation driven by mobile devices, the cloud, the IoT , and big data, as well as novel AI applications, all part of the megatrends, requires continuous advancements in memory technologies. Emerging NVM takes benefit of this dynamic ecosystem.

After more than 15 years in development, PCM, one of the emerging NVM technologies, has finally taken off thanks to the strong involvement of two leading companies, Micron and Intel, announces Yole Développement (Yole). The growth mainly arises from stand-alone applications. “Although momentum is building around emerging NVM for embedded applications, stand-alone memories will be the dominant market, which will be mainly driven by SCM enterprise and client applications,” comments Simone Bertolazzi, PhD, Technology & Market Analyst at Yole.

The market research and strategy consulting company Yole proposes today a technology & market survey dedicated to the emerging non-volatile memory technologies and markets, Emerging Non-Volatile Memory.

Yole and its partners System Plus Consulting and Knowmade, deeply investigate the memory business. The Group set up this year valuable memory services and reports to deliver world class research, data and insight. The emerging NVM report is part of them.

“With our memory activities including a dedicated webcasts program covering DRAM & NAND and emerging NVM, Yole Group of Companies provides valuable expertise and knowledge to its clients and allow them to understand the evolution of this competitive industry,” asserts Emilie Jolivet, Director, Semiconductor & Software from Yole.

The emerging NVM report is a comprehensive analysis of the semiconductor memory ecosystem with the following technologies (STT-) MRAM, RRAM and PCM, plus an introduction to standard memory, flash NAND, DRAM, NVDIMMs. It provides a deep understanding of the NVM applications and details the related market forecasts until 2023. NVM technologies are well described with the companies involved. In this new report, Yole’s Semiconductor & Software team highlights the competitive landscape with supply chain, market positioning and market shares analysis.
What is the status of the emerging NVM business? Yole Group of Companies invite you to enter in the memory world.

Since its latest edition, Yole’s analysts point out today market evolution and technical innovations. According to Yann de Charentenay, Senior Technology & Market Analyst at Yole, DRAM scaling will continue in the next five years, though at slower pace. NAND density will keep increasing thanks to continuous advancements in 3D integration approaches. And emerging NVM will not replace NAND and DRAM but they will rather complement them in “combined” memory solutions. In addition, SCM will be the main emerging NVM market and will be dominated by 3DXPoint for the next 5 years.
From a technology point of view, (STT-) MRAM is gaining momentum for embedded MCU applications since all big foundries are getting involved in this area. Stand-alone RRAM will try to catch market share to PCM on SCM applications. And emerging NVM sales will grow by more than one order of magnitude in the next three years, thanks to SCM applications.

In parallel, Yole’s team identified an increased foundry involvement in (STT-) MRAM and RRAM market segment. Key players such as GlobalFoundries, TSMC, UMC, SMIC and Samsung Foundry Services develop a strong expertise with related capabilities to offer attractive services. This trend is showing a growing foundries’ interest in memory business. As an example, the leading semiconductor company, TSMC announced possible acquisition of a memory company. Moreover, analysts point out the growing number of players including Chinese companies.

In the stand-alone business, emerging NVMs will not replace DRAM and NAND but will be used in combination with them inside memory modules, e.g. SSDs, DIMMs, and NVDIMMs. In 2023, PCM will maintain its lead in the stand-alone memory market thanks to the increasing adoption of 3D XPoint as an enterprise and client SCM. It is worth noting that Samsung and Toshiba took a different strategic path by developing 3D NAND-based SCM solutions such as Z-NAND (Samsung) and XL-Flash (Toshiba, showcased in August 2018). However, these technologies will be used in enterprise SSDs and will not compete with DDR4-compatible Optane DIMMs, which we expect will represent more than 50% of overall 3D XPoint sales.

RRAM was expected to be the first stand-alone technology to compete with 3D XPoint, but it has suffered repeated delays due to technical challenges. We presume that RRAM could return in the race for SCM after 2020, and possibly start competing with NAND for mass storage applications. STT-MRAM, thanks to its high speed and high endurance, is promising for enterprise storage SCM. However, its success will be much lower compared to stand-alone PCM due to higher costs, greater fabrication complexity, and challenging scalability.

Compared to stand alone, the embedded emerging NVM market is relatively small, representing ~3% of the emerging NVM market in 2017. The market is dominated today by RRAM, since only a few RRAM based MCUs are available on the market. However, all top foundries are now getting ready with 28/22nm technology processes for STTMRAM whereas RRAM adoption has been delayed by approximately two years by SMIC and UMC.

Therefore, we expect that STT-MRAM will be the first to take-off in the coming years and will lead the embedded emerging NVM market, especially MCUs, which represent the most important embedded segment. Emerging memory will first replace eFlash, which is facing major scaling challenges due to rising fabrication complexity/costs for technology nodes ≤ 28nm. The adoption of STT-MRAM as an embedded cache memory (SRAM or eDRAM) in high-end processors and mobile application processors (AP) will occur later due to more strict scalability requirements (≤ 14nm).

AI on the edge is the most innovative application for embedded emerging NVM. Crossbar recently demonstrated various AI applications, i.e. face recognition, through the use of RRAM chips. We expect that such RRAM-based AI devices will enter the market after 2021.

Yole Group of Companies leverage decades of industry experience while partnering with its clients to make sure they are consistently well-informed on this dynamic memory market. These years were indeed impressive, not only in terms of revenues, but also in pricing and capital expenditure. Mike Howard, VP of DRAM & Memory Research and Walt Coon, VP of NAND & Memory Research at Yole describe in a dedicated interview published last week, the memory ecosystem and its players, highlighting the latest technology advancements and the future evolutions of the market: click Memory business: what’s next?.

Synopsys, Inc. (Nasdaq: SNPS) announced today another milestone in its longstanding partnership with imec, a research and innovation hub in nanoelectronics and digital technologies, with the successful completion of the first comprehensive sub-3 nanometer (nm) parasitic variation modeling and delay sensitivity study of complementary FET (CFET) architectures. With the potential to significantly reduce area versus traditional FinFETs, CFET is a promising option to maintain area scaling beyond 3nm technology.

In 3-nm and 2-nm process technologies, the magnitude of variation increases significantly for middle of line (MOL) parameters, as well as interconnect, due to high resistance of metal lines, vias, and surface scattering. Therefore, modeling parasitic variation and sensitivity is a critical factor in bringing CFET to mainstream production.

Prediction at early stages of process development will allow foundries to create more robust and variation-tolerant transistors, standard cells, and methodologies for metal interconnect. Using the QuickCap® NX 3D field solver, in a close collaboration between Synopsys R&D and imec research teams, allowed for fast and accurate modeling of parasitics for a variety of device architectures and to identify the most critical device dimensions and properties. This allowed the optimization of CFET devices for better power/performance trade-offs. As part of a comprehensive set of tools that includes Raphael™ TCAD extraction to StarRC™ parasitic extraction for the largest system-on-chips (SoCs), QuickCap NX effectively helps process engineers understand the sensitivity of circuit performance to variations in process parameters and improves modeling accuracy by establishing golden reference values.

“This work has allowed us to accurately model and analyze cell and interconnect variation at advanced processes and architectures, such as Complementary FET,” said Anda Mocuta, director, Technology Solutions and Enablement at imec. “Our collaboration with Synopsys continues a legacy of successful collaborations that enable us to search for technological breakthroughs below 3 nanometers. The capabilities of Synopsys tools, such as QuickCap NX, have been key to our joint research on variability.”

“Imec is at the forefront of research into semiconductor technology. Our collaboration with imec to develop variation-aware solutions down to 2 nanometer processes will benefit the entire semiconductor industry,” said Antun Domic, chief technology officer at Synopsys. “Utilizing the flexibility of Synopsys’ QuickCap NX 3D parasitic extraction interface, engineers can better target and significantly reduce the number of trials needed to optimize circuit performance in the presence of process variation and reduce circuit sensitivity. This significantly reduces the overall turnaround time for device and circuit optimization.”

Leti, a research institute at CEA Tech, has reported breakthroughs in six 3D-sequential-integration process steps that previously were considered showstoppers in terms of manufacturability, reliability, performance or cost.

CoolCubeTM, CEA-Leti’s 3D monolithic or 3D sequential CMOS technology allows vertically stacking several layers of devices with a unique connecting-via density above tens of million/mm2. This MoreMoore technology decreases dice area by a factor of two, while providing a 26 percent gain in power. The wire-length reduction enabled by CoolCubeTM also improves yield and lowers costs. In addition to power savings, this true 3D integration opens diversification perspectives thanks to more integration of functions. From a performance optimization and manufacturing-enablement perspective, processing the top layer in a front end of line (FEOL) environment with a restricted thermal budget requires process modules optimization.

CEA-Leti’s recent 3D sequential integration results were presented Dec. 3 at IEDM 2018 in the paper, “Breakthroughs in 3D Sequential Integration”. The breakthroughs are:

  • Low-resistance poly-Si gate for the top field-effect transistors (FETs)
  • Full LT RSD (low temperature raised source and drain) epitaxy, including surface preparation
  • Stable bonding above ultra low-k (ULK)
  • Stability of intermediate back end of line (iBEOL) between tiers with standard ULK/Cu technology
  • Efficient contamination containment for wafers with Cu/ULK iBEOL, enabling their re-introduction in front end of line (FEOL) for top FET processing, and
  • Smart CutTM process above a CMOS wafer.

 

To obtain high-performance top FETs, low gate access resistance was achieved using UV nano-second laser recrystallization of in-situ doped amorphous silicon. Full 500°C selective silicon-epitaxy process was demonstrated with an advanced LT surface preparation and a combination of dry-and-wet etch preparation.  Epitaxial growth was demonstrated with the cyclic use of a new silicon precursor and dichlorine Cl2 etching. At the same time, the project paved the way to manufacturability of 3D sequential integration including iBEOL with standard ULK and Cu-metal lines.

A bevel-edge contamination containment strategy comprised of three steps (bevel etch, decontamination, encapsulation) enabled reintroducing wafers in an FEOL environment following the BEOL process. In addition, the project also demonstrated for the first time the stability of line-to-line breakdown voltage for interconnections submitted to 500°C. The work also demonstrated a Smart CutTM transfer of a crystalline silicon layer on a processed bottom level of FD-SOI CMOS devices, as an alternative to the SOI bonding-and-etch back process scheme for top channel fabrication.

Researchers from Intel Corp. and the University of California, Berkeley, are looking beyond current transistor technology and preparing the way for a new type of memory and logic circuit that could someday be in every computer on the planet.

In a paper appearing online Dec. 3 in advance of publication in the journal Nature, the researchers propose a way to turn relatively new types of materials, multiferroics and topological materials, into logic and memory devices that will be 10 to 100 times more energy-efficient than foreseeable improvements to current microprocessors, which are based on CMOS (complementary metal-oxide-semiconductor).

Single crystals of the multiferroic material bismuth-iron-oxide. The bismuth atoms (blue) form a cubic lattice with oxygen atoms (yellow) at each face of the cube and an iron atom (gray) near the center. The somewhat off-center iron interacts with the oxygen to form an electric dipole (P), which is coupled to the magnetic spins of the atoms (M) so that flipping the dipole with an electric field (E) also flips the magnetic moment. The collective magnetic spins of the atoms in the material encode the binary bits 0 and 1, and allow for information storage and logic operations. Credit: Ramamoorthy Ramesh lab, UC Berkeley

The magneto-electric spin-orbit or MESO devices will also pack five times more logic operations into the same space than CMOS, continuing the trend toward more computations per unit area, a central tenet of Moore’s Law.

The new devices will boost technologies that require intense computing power with low energy use, specifically highly automated, self-driving cars and drones, both of which require ever increasing numbers of computer operations per second.

“As CMOS develops into its maturity, we will basically have very powerful technology options that see us through. In some ways, this could continue computing improvements for another whole generation of people,” said lead author Sasikanth Manipatruni, who leads hardware development for the MESO project at Intel’s Components Research group in Hillsboro, Oregon. MESO was invented by Intel scientists, and Manipatruni designed the first MESO device.

Transistor technology, invented 70 years ago, is used today in everything from cellphones and appliances to cars and supercomputers. Transistors shuffle electrons around inside a semiconductor and store them as binary bits 0 and 1.

In the new MESO devices, the binary bits are the up-and-down magnetic spin states in a multiferroic, a material first created in 2001 by Ramamoorthy Ramesh, a UC Berkeley professor of materials science and engineering and of physics and a senior author of the paper.

“The discovery was that there are materials where you can apply a voltage and change the magnetic order of the multiferroic,” said Ramesh, who is also a faculty scientist at Lawrence Berkeley National Laboratory. “But to me, ‘What would we do with these multiferroics?’ was always a big question. MESO bridges that gap and provides one pathway for computing to evolve”

In the Nature paper, the researchers report that they have reduced the voltage needed for multiferroic magneto-electric switching from 3 volts to 500 millivolts, and predict that it should be possible to reduce this to 100 millivolts: one-fifth to one-tenth that required by CMOS transistors in use today. Lower voltage means lower energy use: the total energy to switch a bit from 1 to 0 would be one-tenth to one-thirtieth of the energy required by CMOS.

“A number of critical techniques need to be developed to allow these new types of computing devices and architectures,” said Manipatruni, who combined the functions of magneto-electrics and spin-orbit materials to propose MESO. “We are trying to trigger a wave of innovation in industry and academia on what the next transistor-like option should look like.”

Internet of things and AI

The need for more energy-efficient computers is urgent. The Department of Energy projects that, with the computer chip industry expected to expand to several trillion dollars in the next few decades, energy use by computers could skyrocket from 3 percent of all U.S. energy consumption today to 20 percent, nearly as much as today’s transportation sector. Without more energy-efficient transistors, the incorporation of computers into everything – the so-called internet of things – would be hampered. And without new science and technology, Ramesh said, America’s lead in making computer chips could be upstaged by semiconductor manufacturers in other countries.

“Because of machine learning, artificial intelligence and IOT, the future home, the future car, the future manufacturing capability is going to look very different,” said Ramesh, who until recently was the associate director for Energy Technologies at Berkeley Lab. “If we use existing technologies and make no more discoveries, the energy consumption is going to be large. We need new science-based breakthroughs.”

Paper co-author Ian Young, a UC Berkeley Ph.D., started a group at Intel eight years ago, along with Manipatruni and Dmitri Nikonov, to investigate alternatives to transistors, and five years ago they began focusing on multiferroics and spin-orbit materials, so-called “topological” materials with unique quantum properties.

“Our analysis brought us to this type of material, magneto-electrics, and all roads led to Ramesh,” said Manipatruni.

Multiferroics and spin-orbit materials

Multiferroics are materials whose atoms exhibit more than one “collective state.” In ferromagnets, for example, the magnetic moments of all the iron atoms in the material are aligned to generate a permanent magnet. In ferroelectric materials, on the other hand, the positive and negative charges of atoms are offset, creating electric dipoles that align throughout the material and create a permanent electric moment.

MESO is based on a multiferroic material consisting of bismuth, iron and oxygen (BiFeO3) that is both magnetic and ferroelectric. Its key advantage, Ramesh said, is that these two states – magnetic and ferroelectric – are linked or coupled, so that changing one affects the other. By manipulating the electric field, you can change the magnetic state, which is critical to MESO.

The key breakthrough came with the rapid development of topological materials with spin-orbit effect, which allow for the state of the multiferroic to be read out efficiently. In MESO devices, an electric field alters or flips the dipole electric field throughout the material, which alters or flips the electron spins that generate the magnetic field. This capability comes from spin-orbit coupling, a quantum effect in materials, which produces a current determined by electron spin direction.

In another paper that appeared earlier this month in Science Advances, UC Berkeley and Intel experimentally demonstrated voltage-controlled magnetic switching using the magneto-electric material bismuth-iron-oxide (BiFeO3), a key requirement for MESO.

“We are looking for revolutionary and not evolutionary approaches for computing in the beyond-CMOS era,” Young said. “MESO is built around low-voltage interconnects and low-voltage magneto-electrics, and brings innovation in quantum materials to computing.”

Leti, a research institute of CEA-Tech, and Silvaco Inc., a global provider of software, IP and services for designing chips and electronic systems for semiconductor companies, today announced during the IEDM 2018 conference a project to create innovative and unified SPICE compact models for the design of advanced circuits using nanowire and nanosheet technologies.

The new predictive and physical compact model under development, Leti-NSP, builds on Leti’s 15 years of model development, including the popular Leti-UTSOI model for FD-SOI technology. The Leti-NSP compact model uses a novel methodology for the calculation of the surface potential, including quantum confinement. The model is able to handle arbitrary cross-section shapes of stacked planar and vertical GAA MOSFETs (circular, square, rectangular). It provides an excellent tool for design exploration of nanowire and nanosheet device architectures.

This three-year collaboration will make the new device models available to designers through SmartSpiceTM, Silvaco’s high-performance parallel SPICE simulator for use by circuit designers. The corresponding model-parameters extraction flow will be implemented in Utmost IVTM, Silvaco’s database-driven environment for characterizing semiconductor devices, to ensure an accurate fit between simulated and measured device characteristics.

Accuracy of analysis at the nanometer scale is essential for co-optimization of silicon process technology and circuit performance. Besides accurate device characterization and simulation, a complete solution includes TCAD simulation, and 3D parasitic extraction. Silvaco’s partnership with leading research institutions for atomistic TCAD, and its proven in-house extraction solver technology, will provide the most accurate Design Technology Co-Optimization (DTCO) solution for nanometer technologies.

“Over two decades, CEA-Leti and Silvaco have collaborated on design-technology co-optimization, ranging from innovative TCAD simulation to the design of advanced nanoelectronics, and thus expanded and strengthened Silvaco’s suite of tools for designers,” said Emmanuel Sabonnadière, CEA-Leti CEO. “This project continues that partnership, andwhen these physics-based compact models are made available to designers worldwide, they will be able to evaluate the potential of advanced nanowire-based CMOS technologies under development at CEA-Leti.”

“DTCO, including circuit simulation, is fundamental to the development of electronic devices, and shrinking silicon geometries are placing an even greater premium on accuracy to capture and evaluate all the new physical effects in nanometer design,” said Eric Guichard, vice president of Silvaco’s TCAD Division. “Building on past successes of Leti and Silvaco’s collaboration, this project will provide circuit designers and technologists with powerful, advanced design flows that combine CEA-Leti’s physical, predictive, and easy-to-use models with Silvaco’s high-accuracy EDA tools.”

MagnaChip Semiconductor Corporation (“MagnaChip”) (NYSE: MX), a designer and manufacturer of analog and mixed-signal semiconductor platform solutions, today announced that volume production has commenced for an IGBT product for power module targeted to high-voltage industrial applications. IGBT is one of a MagnaChip family of Power standard products called Insulated Gate Bipolar Transistors.

The new IGBT P-series (“MBW100T120PHF”) has both high current and high voltage capabilities of 1200V and 100A, and has achieved a low saturation voltage Vce(sat) of 1.71V and low switching losses by using Field-Stop Trench technology. MBW100T120PHF allows designers to operate devices at an improved switching frequency, which enables reducing the size and cost of capacitors and inductive devices in circuits.

To product designers, this translates into high power density, small size and low material cost of products. MBW100T120PHF is operable up to four times the rated current, and with a wide SOA (Safe Operating Area) well-suited for industrial applications which require high power. In addition, by optimizing the resistance embedded inside the chip, MBW100T120PHF enables a parallel structure design, which allows multiple chips to operate simultaneously.

MBW100T120PHF is expected to improve overall system stability and energy efficiency of applications by reducing the power loss from DC-AC power conversions for high-voltage industrial applications, such as 10kW+ 3-phase motor and photovoltaic inverter systems.

“We are pleased to launch our newest IGBT P-series product for industrial power modules, with high-voltage and high-current capabilities of 1200V and 100A,” said YJ Kim, CEO of MagnaChip. “The introduction of this IGBT P-series product will further expand our IGBT power product portfolio and enhance our reputations as a market leader of high-voltage power standard products.”

Mentor, a Siemens business, today announced that DECA Technologies has become the latest member of Mentor’s (outsourced assembly and test) OSAT Alliance – a program to help drive faster adoption of new, high-density advanced packaging (HDAP) technologies like 2.5D IC, 3D IC and fan-out wafer-level packaging (FOWLP) for customer integrated circuit (IC) designs. The Alliance enables mutual customers to better leverage Mentor’s proven HDAP flow to quickly bring to market innovations for internet of things (IoT), automotive, high-speed communications, computing and artificial intelligence (AI). DECA is supporting this objective by making available to Mentor and DECA’s mutual customers a new assembly design kit (ADK) for DECA’s M-Series advanced fan-out wafer-level package (FOWLP) process to be used with Mentor software.

Through the alliance, the two companies are offering a comprehensive tool flow that gives mutual customers the ability to create and evaluate multiple complex IC package assemblies and interconnect scenarios in an easy-to-use, data robust graphical environment prior to and during physical design implementation.

The Mentor flow from DECA Technologies features industry-leading tools:

  • Xpedition® Substrate Integrator – for engineers to evaluate M-Series package and configuration before committing to design; and for DECA configuration of customer designs into selected M-Series package.
  • Xpedition® Package Designer – for engineers to design/layout a single or multi-die M-Series package.
  • Calibre® 3DSTACK – for signoff leveraging the M Series ADK – ensures die or multiple dice and package design conform to M-Series manufacturing rules.

The DECA ADK provides mutual customers with a verified sign-off fabrication rule deck for Calibre 3DSTACK that will enable companies to converge on sign-off faster and with less verification cycles.

“Being part of the Mentor OSAT Alliance has allowed DECA to fast-track the creation of a Mentor-based ADK for our breakthrough M-Seriesä FO-WLP technology,” said Chris Scanlan, senior vice president at DECA Technologies. “Since the Mentor flow includes Calibre, the golden signoff solution for the fabless ecosystem, our customers are able to quickly close any physical verification issues for their entire solution, resulting in faster time to market.”

Mentor continues to spearhead the EDA industry by enabling the entire ecosystem to adopt new technologies via its OpenDoor program and the various alliances that fall under the program. The OSAT Alliance program helps promote the adoption, implementation and growth of HDAP throughout the semiconductor eco-system and design chain, enabling system and fabless semiconductor companies to have a friction-free path to emerging packaging technologies.

“We are pleased that HDAP technology pioneer DECA Technologies has joined the Mentor OSAT Alliance,” said AJ Incorvaia, vice president and general manager of Mentor’s Electronic Board Systems Division. “In doing so, and by providing a fully validated ADK for DECA’s M-Series FOWLP process for Mentor’s proven HDAP tool flow, we have enabled customers to more easily transition from classic chip design to 2.5 and 3D solutions.”

Toshiba Machine Co., Ltd. (TOKYO:6104) has developed the new DC-KT Series Die Casting Machines to meet the needs of the Southeast Asian market and has started sales and production at its plant in Thailand.

DC-KT Series Features

  • Enhanced functions for meeting the unique needs of the Southeast Asian market. The Thai plant has been engaged in the manufacture and sales of die casting machines for four years. The knowledge gained about local market needs over this period led to the development of these new die casting machines with features not found in previous machines, namely, a preset function for casting pressure, 2-level injection settings for low speed, and intensification accumulator in standard configurations. Also, the machine control panel incorporates a touch panel for intuitive, simple operation and control.
  • Lineup with 280-ton and 400-ton die-locking force models. The product lineup includes 280-ton and 400-ton models providing even higher die-locking force than previous models for enabling support for casting of larger products. Improved high-speed acceleration performance and maximum injection force allow casting of complex-shaped products, products with large thicknesses, and a wide array of other product types. “Local production-local consumption”, providing optimum support to customers in Southeast Asia.
  • Production and shipping at the Thai plant near the market enables faster delivery times, more stable production, and quicker response to customer requests for modifications, overhauls, and other services.

Company president Tanabe of Toshiba Machine (Thailand) Co., Ltd, expressed his intention to expand in the Southeast Asian market; “We want to aggressively expand sales using this new model, which was developed based on feedback from our customers in the Southeast Asian market.”

Toshiba Machine will launch these new die casting machines to assist Southeast Asia region customers in attaining even higher productivity.

MIRPHAB, a European Commission project to create a pilot line to fabricate mid-infrared (MIR) sensors by 2020, is accepting proposals from companies that want to develop and prototype new MIR devices that operate in gas-and-liquid media.

The project produces MIR photonic devices via assembled and/or packaged devices for laser-based, analytical MIR sensors, and expert design for sensor components that are fabricated on the pilot line. The platform is organized so that development of novel sensors and sensing systems is based on MIR integrated optic components and modules already incorporated in MIRPHAB’s portfolio.

The aim of the MIRPHAB pilot line is to provide each customer with a unique chemical spectroscopic system by combining sources, photonic circuits and detectors in standard packaging.

“European industry requires more efficient control processes to gain greater productivity and operational efficiency, and this project will deliver the devices required to improve those processes,” said CEA-Leti’s Sergio Nicoletti, who is coordinating the project. “MIRPHAB also will develop new sensor technology that provides novel analytical tools for companies to help improve people’s overall quality of life via environmental monitoring (e.g to measure VOC), food quality control (e.g. food spoilage or  adulteration ) and fast clinical diagnoses (e.g. provide cancer cells images). These are some of the areas where MIR sensors will play an increasingly significant role.”

In addition to providing device-design services for customers, the MIRPHAB team will help them develop sound business cases and strong business plans to commercialize their new devices. Potential cost-and-performance breakthroughs will be shown for reliable MIR sensing products based on building blocks provided by MIRPHAB. MIRPHAB also will be a sustainable source of key components for new and highly competitive MIR sensors, and will support their successful market introduction, while strengthening the competitiveness of European industry.

Mid-infrared light interacts strongly with molecular vibrations as each molecule gives a unique absorption spectrum that provides a simple solution for sensing. The sensors’ reduced size and flexible design make them ideal candidates for integration into already existing equipment for in-line/on-line detection.

The MIRPHAB team will host a booth, #ZB24, at the Sensors USA event in Santa Clara, Calif., Nov. 14-15, 2018.

MIRPHAB is funded by the Photonics Public Private Partnership. The project brings together 18 leading European organizations and is coordinated by CEA-Leti. For more information visit the project’s website.

Micron Technology, Inc., (Nasdaq: MU) today announced at Electronica 2018 that it will collaborate with the BMW Group to further advance the development of automotive memory solutions used in vehicles. Memory and storage are key components in accelerating the intelligence and user experience of next-generation systems in vehicles, including in-cabin infotainment as well as advanced driver-assistance systems (ADAS) technology, which together play an important role in making self-driving autonomous cars a reality.

Micron and the BMW Group will intensify their existing efforts toward testing and development of automotive memory solutions at Micron’s state-of-the-art lab in Munich, Germany. Using the Test Automation Framework of the BMW Group as a car emulator platform, the two companies will work together to define and validate memory and storage solutions for next-generation platforms. The collaborative effort will leverage Micron’s memory and storage technology expertise, along with its broad portfolio of DRAM, NAND, and NOR technologies, including LPDRAM, e.MMC, UFS and SSD storage solutions.

As a proven memory partner for automotive manufacturers, Micron recognizes the importance of validating and testing new automotive memory technologies for robustness and reliability before releasing them into the market. Micron’s customer lab expertise in developing innovative automotive memory technologies will enable the BMW Group to raise the quality of the driving experience in automobiles of the future.

“The incorporation of new features and capabilities in advanced in-vehicle infotainment (IVI) and ADAS, such as voice recognition, hand gesturing and image recognition, are driving an explosive growth in both volatile and nonvolatile memory embedded in vehicles, accelerating intelligence at the edge,” said Giorgio Scuro, vice president of Micron’s automotive division. “Micron has a long-standing record working with automotive industry partners, and this joint initiative with the BMW Group is a testament to our expertise in bringing innovative automotive memory technologies to market.”

As a leading memory partner with more than 25 years of experience, Micron provides advanced automotive memory solutions that meet stringent quality, reliability and compliance requirements. Micron’s broad portfolio of volatile and nonvolatile memory products are optimized for automotive and supported by a formal product longevity program.