Category Archives: Semicon West

Intel has won SEMI’s 2018 Award for the Americas. SEMI honored the celebrated chipmaker for pioneering process and integration breakthroughs that enabled the first high-volume Integrated Silicon Photonics Transceiver. The award was presented yesterday at SEMICON West 2018.

SEMI’s Americas Awards recognize technology developments with a major impact on the semiconductor industry and the world.

The Intel® Silicon Photonics 100G CWDM4 (Coarse Wavelength Division Multiplexing 4-lane) QSFP28 optical transceiver, a highly integrated optical connectivity solution, combines the power of optics and the scalability of silicon. The small form-factor, high-speed, low-power consumption 100G optical transceivers are used in optical interconnects for data communications applications, including large-scale cloud and data centers, and in Ethernet switch, router, and client telecommunications interfaces.

Dr. Thomas Liljeberg, senior director of R&D for Intel Silicon Photonics, accepted the award on behalf of Intel. Dr. Liljeberg is one of the technologists responsible for bringing Intel’s silicon photonics 100G transceivers to high-volume production.

“Every year SEMI honors key technological contributions and industry leadership through the SEMI Award,” said David Anderson, president, SEMI Americas. “Intel was instrumental in delivering technologies that will influence product design and system architecture for many years to come. Congratulations to Intel for this significant accomplishment.”

“The 2018 Award recognizes the enablement of high-volume manufacturing through technology leadership and collaboration with key vendors in the supply chain,” said Bill Bottoms, chairman of the SEMI Awards Advisory Committee. “Intel’s collaboration is a model for how the industry can accelerate innovation in the future.”

SEMI established the SEMI Award in 1979 to recognize outstanding technical achievement and meritorious contributions in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

The SEMI Americas award is the highest honor conferred by the SEMI Americas region. It is open to individuals or teams from industry or academia whose specific accomplishments have a broad commercial impact and widespread technical significance for the entire semiconductor industry. Nominations are accepted from individuals of North American-based member companies of SEMI. For a list of past award recipients, visit www.semi.org/semiaward.

SEMI yesterday honored two industry leaders at SEMICON West 2018 for their outstanding accomplishments in developing Standards for the electronics and related industries. The SEMI Standards awards were announced at the SEMI International Standards reception.

The Technical Editor Award recognizes the efforts of a member to ensure the technical excellence of a committee’s Standards. This year’s recipient is Sean Larsen of Lam Research. Mr. Larsen has led the North America EHS Committee and multiple EHS task forces for over a decade. His knowledge of the Regulations, Procedure Manual, and Style Manual, combined with his vast experience in the industry, ensures that complex safety matters are explained in a clear, consistent manner, and ballot authors frequently rely on him for his technical skills in preparing ballots.

In addition to co-chairing the North America EHS Committee, Mr. Larsen is currently the co-leader of the SEMI S22 (Electrical Design) Revision TF, the SEMI S2 Non-Ionizing Radiation TF, the SEMI S2 Korean High Pressure Gas Safety TF, and the Control of Hazardous Energy TF.

The Corporate Device Member Award recognizes the participation of the user community and is presented to individuals from device manufacturers. This year’s recipient is Don Hadder of Intel. Mr. Hadder has been actively involved in the Standards Program for several years, and currently leads the Chemical Analytical Methods Task Force and chairs the North America Liquid Chemicals Committee. He has successfully re-energized the committee, which is now focused on enabling continued process control improvements for advanced nodes. He recently drove the development of a critical new standard: SEMI C96, Test Method for Determining Density of Chemical Mechanical Polish Slurries, the first document in a series of SEMI Standards that will be devoted specifically to CMP slurry users, IDMs, slurry suppliers, metrology manufacturers and OEM equipment suppliers.

Mr. Hadder has worked at Intel for 23 years, where his experience and system ownership has been in Diffusion, Wet Etch, Planar-CMP, Ultra-Pure Water, Waste Treatment Systems, Abatement and Vacuum Systems, Bulk and Specialty Gas, Bulk Chemical Delivery and Planar Chemical Delivery.

9:00 am – 9:35 am
KEYNOTE: Machine Learning The Potential to Transform the Semiconductor Industry
Mark Papermaster, Advanced Micro Devices
Yerba Buena Theater

9:35 am – 9:50 am
KEYNOTE: The Future of Autonomy: Semiconductors in the Driver’s Seat
Wolfgang Juchmann, AutonomouStuff
Yerba Buena Theater

9:50 am – 10:30 am
KEYNOTE: Industrial AI Applications and Edge Intelligence
Amir Husain, SparkCognition
Yerba Buena Theater

10:30 am – 12:30 pm
SMART MANUFACTURING: Machine Learning and AI in Microelectronics Manufacturing
Moscone South, Smart Manufacturing Pavilion

10:30 am – 11:30 am
PANEL: Federal Strategy for Semiconductor and Microelectronics Innovation
Yerba Beuna Theater

2:00 pm – 4:00 pm
SMART TRANSPORTATION: Future of Automobility Supply Chain: Semiconductors and the New Technology Stack
Moscone North, TechXPOT North

Data economy era begins


July 10, 2018

By Shannon Davis

Speaking at imec ITF Forum on Tuesday, Scott DeBoer, Executive Vice President of Technology Development at Micron opened his keynote address with a video that featured astounding statistics: Micron memory and storage is a part of storing the data generated by practically every type of smart device and high speeding computer processing – nearly 2.5 quintillion bytes per day.

“We’re turning information into insights and activating data to reach your higher realms of productivity and innovation,” the video’s narrator said. “We are Micron, and we are transforming how the world uses information to enrich lives.”

This would be the central theme of DeBoer’s talk, as he outlined the disruptive technology advancements taking place in the memory world and the markets they impact. According to DeBoer, we are in the early stages of the data economy.

The data economy in 2017, DeBoer indicated in his presentation, reported about 22,000 billion gigabytes created that year, compared to previous computer eras in the earlier part of the century, when about 250 billion gigabytes were created per year on average. The early stages of artificial intelligence, smart businesses, smart homes, and the interconnection of so many devices led DeBoer to make an astonishing prediction.

“Looking forward to 2021,” he said, “I’m projecting now: 62,000 billion gigabytes [per year]. Just a phenomenal growth path.”

DeBoer said continued scaling of DRAM and 3D NAND as well as the emergence of 3D XPoint memory technology would be responsible for helping maintain this kind of explosive growth in the memory sector. 3D XPoint memory technology is considered a storage class memory, and, according to DeBoer, is the only emerging memory currently.

“The way that we approach memory technology today…is quite different,” said DeBoer.

DRAM technology 15 years ago, he said, was built around enabling a personal computer system, where the quality requirements for power and performance were well-defined, and scaling continued along an expected path for many years. Today, however, the broad spectrum of technologies available and emerging markets today puts varying requirements on DRAM technology

“The same DRAM component that is ideal for a data center is absolutely not ideal for either automotive or for a mobile kind of application,” said DeBoer.

In addition to scaling, Micron has had to identify different kinds of innovations, thinking outside the box to get the kinds of performance and cost effectiveness through the years in ways that were different than just scaling memory chips.

“It’s not just about scaling, it’s about coming up with other kinds of ideas for being able to improve performance and cost structure to get those high densities for these applications,” DeBoer said. One example of this he discussed was CMOS under array, which is taking 3D technology and performance to a new level: “By taking that logic technology and putting it all underneath your array and changing the architecture of the memory, you can fundamentally change the cost structure and you fundamentally changed the performance.”

DeBoer explained that this technology take a manufacturable density of NAND and basically uses the infrastructure of that technology, and the new technology is simply the interconnect between the two layers. This, he said, takes the pressure off of the equipment industry in terms of a variety of process capabilities. It also paves the way for future NAND scaling.

Near the end of his presentation, the audience chuckled along with him as DeBoer talked about building a computer at home with his son over the fourth of July holiday weekend.

“I’m probably one of the only people that actually appreciated the fact that the memory cost was very high,” he laughed.

BY DEBRA VOGLER, SEMI, Milpitas, CA

With chipmakers looking toward 5nm manufacturing, it’s clear that traditional scaling is not dead but continuing in combination with other technologies. The industry sees scaling enabled by 3D architectures such as die stacking and the stacking of very small geometry wafers. Interconnect scaling also comes into play. This year’s Scaling Technologies TechXPOT at SEMICON West (Scaling Every Which Way! – Thursday, July 12, 2:00PM-4:00PM) will provide an update on the evolution of scaling and describe how the various players (foundry, IDM, fabless, and application developers) are jockeying for innovation leadership. As a prelude to the event, SEMI asked speakers to provide insights on important scaling trends. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/scaling-every-which-way.

Challenges for gate-all-around (GAA) and FinFET devices

Common performance boosters for gate-all-around (GAA) FETs and FinFETs include lower access resistance, lower parasitic capacitance, and stress. “However, one specific performance booster that only applies to GAA is the reduction of the spacing between the vertical wires or sheets,” says Diederik Verkest, imec distinguished member of technical staff, Semiconductor Technology and Systems.

“This reduces parasitic capacitance without affecting drive current and hence benefits both performance and power.” He further notes that imec demonstrated the first stacked gate-all-around (GAA) devices in scaled nodes. “In fact, we are the only ones that published working circuits – ring oscillators in a scaled node using industry-standard processes – in our case replacement metal gate (RMG), and embedded in situ doped source/drain (S/D) epitaxy.”

“There are two elements of the stacked GAA architecture that need to be addressed,” says Verkest. “The first is that this architecture uses epitaxially-grown layers of Si and SiGe to define the device channel. The use of grown materials for the channel and the lattice mismatch between the two materials represent a departure from the traditional fabrication of CMOS devices, so the industry needs to develop and gain confidence in novel metrology that allows for good control of the layers and also proves their low defectivity.” The second aspect is the three-dimensional nature of the GAA devices. “During the processing of these devices, we have ‘non-line-of-sight’ hidden features that are difficult to control and characterize and may also lead to new defect mechanisms that would impact yield, and possibly product reliability.”

Huiming Bu, director, Advanced Logic/Memory Research – Integration and Device, IBM Research, Semiconductor Group, says that naming of technology nodes has been used extensively for marketing strategies in “foundry land,” but the designations have lost much of their meaning as technology scaling differentiators. “That said, when it comes to technology innovation and value proposition, IBM, in conjunction with Samsung and GLOBALFOUNDRIES, has developed the GAA NanoSheet transistor for 5nm to provide a full technology node scaling benefit in density, power and performance,” says Bu (FIGURE 1). The key parameters for intrinsic device optimization when scaling to the 3nm node, explains Bu, are the NanoSheet width for better electrostatic characteristics, and the number of sheets for increased current density. Also necessary are strain engineering for carrier transport enhancement, and interconnect innovations for parasitic RC reduction.

“Beyond that, the industry needs to look into something different, something more disruptive.”

Materials challenges

Materials challenges are also a concern as the industry moves to 5nm and below. “We see increasing complexity in the material systems that are being used,” explains Verkest. One example he cites in scaled FinFET or GAA technologies is the use of two to three layers of different materials–typically metals such as TiN – to which small amounts of other elements are added to set device characteristics such as the threshold voltage. “At the same time, the requirements for the thickness of these materials, driven by gate dimensions for example, or the distance between the wires, are increasingly challenging.” Other examples of materials challenges are the use of two to three different types of insulators in the middle-of-the- line, each with different etch contrasts. “We use novel materials such as carbon containing oxides or oxynitrides that have lower dielectric constants in order to boost the performance of circuits,” he says, noting that the materials list “is quite long.”

Several critical dimensions in transistors at advanced technology nodes have already reached a few monolayers of atoms, fueling expectations for innovation at the material level for transistor scaling, Bu notes. “The other argument is that there is a growing gap between computing demand and the slowdown of technology advancement driven by conventional scaling,” says Bu. One trend that addresses this gap is integrating more computing functions that make the technology solution more modular, which naturally leads to the incorporation of more materials for more applications. Bu cautions, however, that intro- ducing new materials in semiconductor technology has never been easy. “It takes many years of R&D to reach this implementation point, if it ever happens. So, do we need new materials when the industry moves to 5nm and 3nm? Yes, though I expect new material implementation to be a lot faster in interconnect and packaging at these nodes rather than intrinsic to the transistor.”

Challenges in developing atomic-level processes

There will be challenges in developing atomic-level processes used in scaling, such as atomic layer depositions (ALD) and atomic layer etches, notes Verkest. “These classes of processes are both required to handle the scaled dimensions at the 5nm and 3nm nodes, and also the 3D nature of the scaled technologies – and here we are talking about logic and memories,” Verkest says. “With respect to depositions, we would need to develop thermal ALD processes (not plasma-based) that enable accurate and conformal depositions in non-line-of-sight structures.”

Adhesion and wetting, smoothness, and throughput would also need to be addressed. “Longer term, these processes need to facilitate selectivity and self-alignment to address gap-fill challenges in highly scaled structures,” he says. Other concerns he notes with respect to atomic layer etches are selectivity to various materials, and fidelity requirements that increase the requirements for metrology accuracy. “Throughput is also a concern.”

Bu believes that a new device architecture beyond FinFET is required to provide a full technology node scaling benefit (i.e., density, power and performance) at 5nm and 3nm.
“Beyond 3nm, we may need to continue the transistor scaling in the vertical direction and start to stack them together,” Bu says. He also cites the need for parasitic R/C reduction in the interconnect to take advantage of the intrinsic transistor benefit at the circuit and chip levels. “We see a lot of opportunity in atomic-level processes, especially in atomic layer etch and selective material deposition, to address these challenges in the transistor and the interconnect.”

By Pete Singer

Increasingly complicated 3D structures such finFETs and 3D NAND require very high aspect ratio etches. This, in turn, calls for higher gas flow rates to improve selectivity and profile control. Higher gas flow rates also mean higher etch rates, which help throughput, and  higher rates of removal for etch byproducts.

“Gas flow rates are now approaching the limit of the turbopump,” said Dawn Stephenson, Business Development Manager – Chamber Solutions at Edwards Vacuum. “No longer is it only the process pressure that’s defining the size of the turbopump, it’s now also about how much gas you can put through the turbopump.”

Turbopumps operate by spinning rotors at very high rates of speed (Figure 1). These rotors propel gases and process byproducts down and out of the pump. The rotors are magnetically levitated (maglev) to reduce friction and increase rotor speed.

Figure 1. Spinning rotors propel gases and process byproducts out of the pump.

The challenge starts with processes that have high gas flow rates, over a thousand sccm, and lower chamber pressures, below 100 mTorr.  Such processes include chamber clean steps where high flows of oxygen-containing gases are used to remove and flush the process byproducts from inside the chamber, through Silicon via (TSV) in which SF6is widely used at high gas flowrates for deep silicon reactive ion etch (RIE) and more recently, gaseous chemical oxide removal (COR) which typically uses HF and NH3to remove oxide hard masks.

However, the challenge is intensified with the more general trend to higher aspect ratio etch across all technologies.

Stephenson said the maximum amount of gas you can put through a maglev turbo is determined by two things: the motor power and the rotor temperature. Both of these are affected adversely by the molecular weight of the gas. “The heavier the molecule, the lower the limit. For motor power, if the gas flow rate is increased, the load on the rotor is increased, and then you need more power. Eventually you reach a gas flow at which you exceed the amount of power you have to keep the rotor spinning and it will slow down,” she said.

The rotor temperature is an even bigger limiting factor. “As gas flow rates increase, the number of molecules hitting the rotor are increased. The amount of energy transferred into the rotors is also increased which elevates the temperature of the rotor. Because the rotor is suspended in a vacuum and because it’s levitated, it’s not very easy to remove that heat from the rotor because its primary thermal transfer is through radiation,” she explained.

Pumping heavier gases, particularly ones that have poor thermal conductivity, cause the rotor temperature to rise, leading to what is known as “rotor creep.”Rotor creep is material growth due to high temperature and centrifugal force (stress).  Rotor creep deformation over time narrows clearances between rotor and stator and can eventually lead to contact and catastrophic failure (Figure 2).

Figure 2. Edwards pumps have the highest benchmark for rotor creep life temperature in the industry, due to the use of a premium aluminum alloy as the base material for its mag-lev rotors, combined with a low stress design.

Where it gets even worse are in applications where the turbopump is externally heated to reduce byproduct deposition inside the pump. Such a heated pump will have a higher baseline rotor temperature and significantly lower allowable gas flowrates than an unheated one. This becomes a challenge particularly for the heated turbopumps on semiconductor etch and flat panel display processes using typical reactant gases such as HBr and SF6.  “Those are very heavy gases with low thermal conductivity and the maximum limit of the turbopump is actually quite low,” Stephenson said.

The good news is that Edwards has been diligently working to overcome these challenges. “What we have done to maximize the amount of gas you can put into our turbopumps is to  ensure our rotors can withstand the highest possible temperature design limit for a 10 year creep lifetime.   We use a premium alloy for the base rotor material and then beyond that we have done a lot of work with our proprietary modeling techniques to design a very low stress rotor because the creep is due to two factors: the temperature and the centrifugal stress. Because of those two things combined, we’re able to achieve the highest benchmark for rotor creep life temperature in the industry,” she said.

Furthermore, the company has worked on thermal optimization of the turbopump platform. “That means putting in thermal isolation where needed to try to help keep the rotor and motor cool. At the same time, we also need to keep the gas path hot to stop byproducts from depositing. We have also released a high emissivity rotor coating that helps keep the rotor cool,” Stephenson said. A corrosion resistant, black ceramic rotor coating is used to maximize heat radiation, which helps keep the rotor cool and gives more headroom on gas flowrate before the creep life temperature is reached.

Edwards has also developed a unique real-time rotor temperature sensor: Direct, dynamic rotor temperature reporting eliminates over-conservative estimated max gas flow limits and allows pump operation at real maximum gas flow in real duty cycle while maintaining safety and lifetime reliability.

In summary, enabling higher flows at lower process pressures is becoming a critical capability for advanced Etch applications, and Edwards have addressed this need with several innovations, including optimized rotor design to minimize creep, high emissivity coating, and real time temperature monitoring.

By Dave Lammers

The semiconductor industry is collecting massive amounts of data from fab equipment and other sources. But is the trend toward using that data in a Smart Manufacturing or Industry 4.0 approach happening fast enough in what Mike Plisinski, CEO of Rudolph Technologies, calls a “very conservative” chip manufacturing sector?

“There are a lot of buzzwords being thrown around now, and much of it has existed for a long time with APC, FDC, and other existing capabilities. What was inhibiting the industry in the past was the ability to align this huge volume of data,” Plisinskisaid.

While the industry became successful at adding sensors to tools and collecting data, the ability to track that data and make use of it in predictive maintenance or other analytics thus far “has had minimal success,” he said. With fab processes and manufacturing supply chains getting more complex, customers are trying to figure out how to move beyond implementing statistical process control (SPC) on data streams.

What is the next step? Plisinski said now that individual processes are well understood, the next phase is data alignment across the fab’s systems. As control of leading-edge processes becomes more challenging, customers realize that the interactions between the process steps must be understood more deeply.

“Understanding these interactions requires aligning these digital threads and data streams. When a customer understands that when a chamber changes temperature by point one degrees Celsius, it impacts the critical dimensions of the lithography process by X, Y, and Z. Understanding those interactions has been a significant challenge and is an area that we have focused on from a variety of angles over the last five years,” Plisinski said.

Rudolph engineers have worked to integrate multiple data threads (see Figure), aligning various forms of data into one database for analysis by Rudolph’s Yield Management System (YMS). “For a number of years we’ve been able to align data. The limitation was in the database: the data storage, the speed of retrieval and analysis were limitations. Recently new types of databases have come out, so that instead of relational, columnar-type databases, the new databases have been perfect for factory data analysis, for streaming data. That’s been a huge enabler for the industry,” he said.

Rudolph engineers have worked to integrate multiple data threads into one database.

Leveraging AI’s capabilities

A decade ago, Rudolph launched an early neural-network based system designed to help customers optimize yields. The software analyzed data from across a fab to learn from variations in the data.

“The problem back then was that neural networks of this kind used non-linear math that was too new for our conservative industry, an industry accustomed to first principle analytics. As artificial intelligence has been used in other industries, AI is becoming more accepted worldwide, and our industry is also looking at ways to leverage some of the capabilities of artificial intelligence,” he said.

Collecting and making use of data with a fab is “no small feat,” Plisinskisaid, but that leads to sharing and aligning data across the value chain: the wafer fab, packaging and assembly, and others.

“To gain increased insights from the data streams or digital threads, to bring these threads all together and make sense of all of it. It is what I call weaving a fabric of knowledge: taking individual data threads, bringing them together, and weaving a much clearer picture of what’s going on.”

Security concerns run deep

One of the biggest challenges is how to securely transfer data between the different factories that make up the supply chain. “Even if they are owned by one entity, transferring that large volume of data, even if it’s over a private dedicated network, is a big challenge. If you start to pick and choose to summarize the data, you are losing some of the benefit. Finding that balance is important.”

The semiconductor industry is gaining insights from companies analyzing, for instance, streaming video. The network infrastructures, compression algorithms, transfers of information from mobile wireless devices, and other technologies are making it easier to connect semiconductor fabs.

“Security is perhaps the biggest challenge. It’s a mental challenge as much as a technical one, and by that I mean there is more than reluctance, there’s a fundamental disdain for letting the data out of a factory, for even letting data into the factory,” he said.

Within fabs, there is a tug of war between equipment vendors which want to own the data and provide value-add services, and customers who argue that since they own the tools they own the data. The contentious debate grows more intense when vendors talk about taking data out of the fab. “That’s one of the challenges that the industry has to work on — the concerns around security and competitive information getting leaked out.” Developing a front-end process is “a multibillion dollar bet, and if that data leaks out it can be devastating to market-share leadership,” Plisinski said.

Early adopter stories

The challenge facing Rudolph and other companies is to convince their customers of the value of sharing data; that “the benefits will outweigh their concerns. Thus far, the proof of the benefit has been somewhat limited.”

“At least from a Rudolph perspective, we’ve had some early adopters that have seen some significant benefits. And I think as those stories get out there and as we start to highlight what some of these early adopters have seen, others at the executive level in these companies will start to question their teams about some of their assumptions and concerns. Eventually I think we’ll find a way forward. But right now that’s a significant challenge,”Plisinski said.

It is a classic chicken-and-egg problem, making it harder to get beyond theories to case-study benefits. “What helped us is that some of the early adopters had complete control of their entire value chain. They were fully integrated. And so we were able to get over the concerns about data sharing and focus on the technical challenges of transferring all that data and centralizing it in one place for analytical purposes. From there we got to see the benefits and document them in a way that we could share with others, while protecting IP.”

Aggregating data, buying databases and analytical software, building algorithms – all cost money, in most cases adding up to millions of dollars. But if yields improve by .25 or half a percent, the payback comes in six to eight months, he said.

“It’s a very conservative industry, an applied science type of industry. Trying to prove the value of software — a kind of black magic exercise — has always been difficult. But as the industry’s problems have become so complex, it is requiring these sophisticated software solutions.”

“We will have examples of successful case studies in our booth during SEMICON West. Anyone wanting further information is invited to stop by and talk to our experts,” adds Plisinski.

SEMI today announced the re-election of 10 current members to the SEMI International Board of Directors in accordance with the association’s by-laws.

The 10 board members were re-elected for two-year terms:

  • Martin Anstice, CEO, Lam Research Corporation
  • Kevin Crofton, president, SPTS Technologies, and corp. V.P., Orbotech
  • Jon D. Kemp, vice president, DuPont
  • Mitsunobu Koshiba, president and representative director, JSR Corporation
  • Yong Han Lee, chairman, Wonik
  • Sue Lin, vice chairman, Hermes Epitek
  • Tadahiro Suhara, president, SCREEN Semiconductor Solutions Co., Ltd.
  • Tetsuo Tsuneishi, executive chairman of the board and representative director, TEL
  • Tien Wu, management director and chief operating officer, ASE Group
  • Guoming Zhang, senior V.P. and chief strategy officer, NAURA Technology Group Co., Ltd.

The SEMI Executive Committee confirmed Tetsuo Tsuneishi, chairman of the board of TEL, as chairman of the SEMI Executive Committee. SEMI also confirmed Bertrand Loy, president and CEO of Entegris, as vice-chairman.

The leadership appointments and the elected board members’ tenure become effective at the annual SEMI membership meeting on July 11, during SEMICON West 2018 in San Francisco, California.

“The SEMI Board of Directors is comprised of global business leaders who represent SEMI members and the industry, ensuring that SEMI develops and delivers member value in all regions,” said SEMI president and CEO Ajit Manocha. “We congratulate the re-elected members and greatly appreciate all of our board members’ contributions to the industry.”

SEMI’s 19 voting directors and 11 emeritus directors represent companies from Europe, China, Japan, Korea, North America, and Taiwan, reflecting the global scope of the association’s activities. SEMI directors are elected by the general membership as voting members of the board and can serve a total of five two-year terms.

By Ed Korcynzski

Industry R&D consortium imec runs a series of technology forums around the world, starting in June in Antwerp, Belgium, and including a stop in July in San Francisco in coordination with SEMICON West. Greg McIntyre, imec Director of Advanced Patterning, discussed the state-of-the-art in Extreme Ultra-Violet (EUV) lithography technology with Solid State Technology during the Antwerp event. While still focusing on “path-finding” R&D for industry, the recent technology challenges associated with commercializing EUV lithography has pulled imec into work on patterning ecosystem materials such as resists and pellicles.

With each NXE:3400B model EUV stepper from ASML valued at US$125 million it costs $1 billion to invest in a set of 8 tools to begin high-volume manufacturing, and the entire lithography materials supply-chain is engaged in improving availability and throughput of this expensive tool-set. For high performance logic ICs we need EUV to reach the smallest and most powerful FETs possible, so EUV is in pilot production for logic chips at Samsung and TSMC this year, and will likely begin pilot ramps at Intel and GlobalFoundries next year.

The first use of EUV in IC HVM will be as “cut-masks” for use in self-aligned multi-patterning (SAMP) process flows that start with argon-fluoride-immersion (ArFi) deep ultra-violet (DUV) steppers. Such a first use allows for substitution of three ArFi “multi-color” cut-masks in place of the one EUV mask, in case there are unanticipated issues with the new EUV steppers. Second use in HVM will then happen using a single-exposure of EUV to pattern metal layers, but with no ability to use multiple ArFi exposure as a back-up.

“We will not put EUV in our critical path,” commented Dr. Gary Patton, GlobalFoundries’ CTO and SVP of Worldwide R&D, during a presentation in Antwerp, “But it’s clear that it’s coming and it will offer compelling advantages.” Patton said the company is experimenting with two of ASML’s EUV steppers in a New York fab, and will launch the company’s “7-nm-node” finFET production first with ArFi and then move to EUV when the throughput and uptime of the process make it affordable in their cost models.

Figure 1 shows the extremely small patterning process window around 18nm half-pitch line arrays (P36) using EUV lithography with Dipole source-mask optimization (SMO):  micro-bridging between lines starts below 15.5nm, while breaks within lines start above 18nm. These stochastic failures (Ref:  “Waddle-room for Black Swans:  EUV Stochastics”, SemiMD.com) are caused by variations in the photons absorbed by the resist (a.k.a. “shot noise”), the quantum efficiency of photo-acid generation (PAG) and diffusion, thequencher distribution,and optical and chemical interactions with under-layers for adhesion, anti-reflective coatings, and hardmasks.

Figure 1. Stochastic failures due to atomic-scale variability are shown in top-down CD-SEM images taken from 36-nm Pitch (P36) line/space arrays of post-etched photoresist that had been patterned using EUV lithography, which define the limits of the patterning process window when plotted as Percent Not-OK (%NOK) within an inspected area. (Source: imec)

Every nanometer of resolution is difficult to achieve when patterning below 20nm half-pitch, with many parameters contributing noise to the signal. For EUV lithography using reflective optics, the mask surface causes undesired “flare” reflections from the un-patterned area, such that bright-field masks inherently distort images more than dark-field masks. Since cuts typically only expose <20% of the field, these masks will be much less noisy as dark-fields.

Given the need for dark-field cut-masks, the ideal photoresist will be positive-tone (PT) which means that reformulations of Chemically-Amplified Resists (CAR) based on organic molecules can be used. Standard organic CAR tuned for ArFi lithography provides some sensitivity to EUV, and blends of standard CAR molecules can be tuned to improve trade-offs within the inherent Resolution, Line-Edge-Roughness (LER), and Sensitivity trade-off triangle. Consequently, all of the suppliers of ArFi CAR are capable of supplying some EUV CAR. Since stochastic effects are interdependent, resist vendors have to explore integration options within the entire stack of patterning materials.

JSR co-founded with imec the EUV Resist Manufacturing & Qualification Center NV (EUV RMQC) in Leuven, Belgium, where an EUV stepper at imec is available for experiments. “RMQC is running at full speed, and shipping out production lots,” said McIntyre. “Intel’s Britt Turkot mentioned at SPIE this year that the resist qualification work being done at IMEC has been very beneficial.”

ASML now owns the critical-dimension scanning-electron microscopy (CD-SEM) technology of Hermes Microvision Inc (HMI), and Neal Callan, ASML’s Vice President of Pattern Fidelity Metrology, spoke with Solid State Technologyabout controlling EUV patterning. Electron-beams cause shrinkage in organic films like CAR, and that shrinkage results in a CD bias that can be more than one nanometer. Different CAR formulations from different vendors shrink at different rates, and the effect is more difficult to model in 2D structures. ”We’re being pushed for accurate metrology in terms that can be quantified,” explained Callan. “The biggest issues are in terms of CD-bias with 2D features. We need to build more accurate models to create better data for OPC and for computational lithography, and also for our etch modeling peers.”

“Design rules for EUV need to be stochastically aware,“ confided McIntyre. “Designers need to know how much can be sacrificed in a design rule such as tip-to-tip spacing depending on the pattern pitch. There are different ways that we can think about minimizing stochastic effects.”

While stochastics and systematic yield losses increase in relative importance with decreasing device dimensions, losses due to random defects are also more difficult to control. Figure 2 shows second-generation EUV pellicles made from carbon nano-tubes (CNT) by imec to protect EUV masks from random particles while transmitting ~95%. First-generation pellicles reportedly transmit <90%.

Figure 2. Second generation EUV pellicles based on carbon nano-tubes (CNT) demonstrate increased transmission of ~95% while maintaining sufficient mechanical stability to protect reticles. (Source: imec)

“Today, new purity challenges are not only faced by the fab but also by their materials suppliers driving sharp increases in the use of filtration and purification systems to prevent wafer defects and process excursions,” explained Clint Harris, Senior Vice President and General Manager, Microcontamination Control Division, Entegris, to Solid State Technology.“The transition from 45nm- to 10nm-node has resulted in a 2.5x increase in the changeout frequency of filters as well as a 4x reduction of maximum allowable contaminant size. This trend is expected to continue as device parametric performance becomes more sensitive to particles, gels, metals, mobile ions, and other organic contaminants.

[As a TECHCET Analyst, Ed Korczynski writes the TECHCET Critical Materials Report (CMR) on Photoresists & Ancillaries. https://techcet.com/product/photoresists-and-photoresist-ancillaries/]

9:00 am – 9:30 am
KEYNOTE: Breakthrough Innovators Who Changed the World
Melissa Schilling, PhD, New York University and Author
Yerba Buena Theater

9:45 am – 10:10 am
KEYNOTE: The Era of Artificial Intelligence
Dr. John E. Kelly, III, Cognitive Solutions and IBM Research
Yerba Buena Theater

10:10 am – 11:00am
PANEL: AI Design Forum—Overcoming the Memory Wall
Yerba Buena Theater

11:00 am – 11:25 am
KEYNOTE: AI—The Perfect Storm—An Industry Call to Action
Gary Dickerson, Applied Materials
Yerba Buena Theater

2:00 pm – 2:30 pm
KEYNOTE: William Dally, Efficient Hardware and Methods for Deep Learning
Yerba Buena Theater Tuesday, July 10

2:30 pm –  3:30 pm
SEMI Bulls & Bears
Yerba Buena Theater Tuesday, July 10 2:30pm to

5:00 pm – 9:00 pm
Leti Workshop
W Hotel – 181 3rd St., San Francisco