Category Archives: Semicon West

Edwards Vacuum, a manufacturer of vacuum and abatement solutions for the semiconductor industry, will promote technology innovation and STEM education at SEMICON West this year. Industry professionals and students alike will be intrigued by the scientifically-accurate virtual reality (VR) game (featured at their space #628 on the show floor) that demonstrates the significant role the company’s products play in reducing the environmental impact of semiconductor manufacturing processes.

“The development of an electronic circuit or flat panel display involves a complex manufacturing process that uses a variety of global warming gases. CF4, a perfluorinated compound, is one of the worst offenders because it has an atmospheric lifetime of 50,000 years,” said Scott Balaguer, General Manager North America, Edwards. “The good news is that Edwards’ abatement solutions can minimize this impact significantly. Abatement is a very complex science that Edwards has over 30 years of experience in the making, backed by nearly 100 years of vacuum process technology development. We created the Molecule Blaster VR game as a fun approach to teaching the industry about the science of abatement; people enjoy saving the Earth from harmful greenhouse gases.”

Edwards, a sponsor of the SEMI High Tech U, will host high school students at the show as part of the company’s STEM outreach campaign. Students will experience the Molecule Blaster VR game and learn about chemistry.

“SEMICON West presents an opportunity for high school students to see science in action and have fun learning. We hope this experience will encourage them to consider careers in the semiconductor industry,” adds Balaguer.

SEMICON West 2018 will also feature:

  • Erik Collart, Global Product Manager, Edwards, will give a presentation in the Smart Manufacturing Pavilion on why sub-fab data management is critical to overall fab process and yield and optimization on Wednesday, July 11, from 1:30-4:30pm.
  • Mike Czerniak, Environmental Solutions Business Development Manager, Edwards, has co-authored the “Semiconductor Manufacturing Handbook” and will be available at the Edwards lounge for book signing on Tuesday, July 10, from 2:30-3:30pm.
  • Don’t miss happy hour – Edwards will be serving wine, beer and canapes in their lounge near the Smart Manufacturing Pavilion in the South Hall on Tuesday and Wednesday from 4pm-5pm.

SEMICON West takes place July 10-12, 2018 at the Moscone Center, San Francisco, Calif. SEMICON West is organized by SEMI Americas to connect more than 2,000-member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMICON West is celebrating its 47th year as the flagship event for the semiconductor industry. For more information visit: www.semiconwest.org

Smart technologies take center stage tomorrow as SEMICON West, the flagship U.S. event for connecting the electronics manufacturing supply chain, opens for three days of insights into leading technologies and applications that will power future industry expansion. Building on this year’s record-breaking industry growth, SEMICON West – July 10-12, 2018, at the Moscone Center in San Francisco – spotlights how cognitive learning technologies and other disruptors will transform industries and lives.

Themed BEYOND SMART and presented by SEMI, SEMICON West 2018 features top technologists and industry leaders highlighting the significance of artificial intelligence (AI) and the latest technologies and trends in smart transportation, smart manufacturing, smart medtech, smart data, big data, blockchain and the Internet of Things (IoT).

Seven keynotes and more than 250 subject matter experts will offer insights into critical opportunities and issues across the global microelectronics supply chain. The event also features new Smart Pavilions to showcase interactive technologies for immersive, virtual experiences.

Smart transportation and smart manufacturing pavilions: Applying AI to accelerate capabilities

Automotive leads all new applications in semiconductor growth and is a major demand driver for technologies inrelated segments such as MEMS and sensors. The SEMICON West Smart Transportation and Smart Manufacturing pavilions showcase AI breakthroughs that are enabling more intelligent transportation performance and manufacturing processes, increasing yields and profits, and spurring innovation across the industry.

Smart workforce pavilion: Connecting next-generation talent with the microelectronics industry

SEMICON West also tackles the vital industry issue of how to attract new talent with the skills to deliver future innovations. Reliant on a highly skilled workforce, the industry today faces thousands of job openings, fierce competition for workers and the need to strengthen its talent pipeline. Educational and engaging, the Smart Workforce Pavilion connects the microelectronics industry with college students and entry-level professionals.

In the Workforce Pavilion “Meet the Experts” Theater, recruiters from top companies are available for on-the-spot interviews, while career coaches offer mentoring, tips on cover letter and resume writing, job-search guidance, and more. SEMI will also host High Tech U (HTU) in conjunction with the SEMICON West Smart Workforce Pavilion. The highly interactive program supported by Advantest, Edwards, KLA-Tencor and TEL exposes high school students to STEM education pathways and useful insights about careers in the industry.

Releasing its Mid-Year Forecast at the annual SEMICON West exposition, SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that worldwide sales of new semiconductor manufacturing equipment are projected to increase 10.8 percent to $62.7 billion in 2018, exceeding the historic high of $56.6 billion set last year. Another record-breaking year for the equipment market is expected in 2019, with 7.7 percent forecast growth to $67.6 billion.

The SEMI Mid-Year Forecast predicts wafer processing equipment will rise 11.7 percent in 2018 to $50.8 billion. The other front-end segment, consisting of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, is expected to jump 12.3 percent to $2.8 billion this year. The assembly and packaging equipment segment is projected to grow 8.0 percent to $4.2 billion in 2018, while semiconductor test equipment is forecast to increase 3.5 percent to $4.9 billion this year.

In 2018, South Korea will remain the largest equipment market for the second year in a row. China will rise in the rankings to claim the second spot for the first time, dislodging Taiwan, which will fall to the third position. All regions tracked except Taiwan will experience growth. China will lead in growth with 43.5 percent, followed by Rest of World (primarily Southeast Asia) at 19.3 percent, Japan at 32.1 percent, Europe at 11.6 percent, North America at 3.8 percent and South Korea at 0.1 percent.

SEMI forecasts that, in 2019, equipment sales in China will surge 46.6 percent to $17.3 billion. In 2019, China, South Korea, and Taiwan are forecast to remain the top three markets, with China rising to the top. South Korea is forecast to become the second largest market at $16.3 billion, while Taiwan is expected to reach $12.3 billion in equipment sales.

The following results are in terms of market size in billions of U.S. dollars:

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Billings Report, which offers an early perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (SEMS), a detailed report of semiconductor equipment bookings and billings for seven regions and over 22 market segments; and the SEMI Mid-year Forecast, which provides an outlook for the semiconductor equipment market. For more information or to subscribe, please contact SEMI customer service at 1.877.746.7788 (toll free in the U.S.). For more information online, visit: http://info.semi.org/semi-equipment-market-data-subscription

By Paula Doe

Chip testing is becoming smarter and more complex, creating growing requirements to stream data in real time and ensure it is ready to use for analysis, regardless of the vendor source.

Adaptive testing using machine learning to predict die performance in a downstream test can reduce the number of cycles by as much as 40 per cent without compromising test performance, notes Dan Sebban, VP of data analysis, OptimalPlus, who’ll speak on machine learning challenges at SEMICON West’s Test Vision 2020 program. “As devices and their test requirements grow in complexity, the motivation for automating adaptive test greatly increases,” he states, adding that characteristics such as die location on the wafer, defects on neighboring die, condition of the tester, and test values near the specification limits can help predict which die are likely to be good.

“The big issue we see is that while everyone likes the idea of machine learning, it remains a black box model, with little visibility into why it makes the decisions it does,” adds Sebban. In addition, a suitable infrastructure to run, deploy and assess a machine learning model in real time is required. “There is still some hesitation to adopt machine learning. It’s a big change of mindset. While building the confidence to use machine learning will take time and experience, using the technology to automate big data analysis with the relevant infrastructure may be our best alternative to reduce test cost.”

Systems test and parts-per-billion quality become the rule

Systems test will continue to become more prominent and more complex as chips and packages shrink, affirms Stacy Ajouri, Texas Instruments system integration engineer and Test Vision 2020 event chair. “Even IC makers now need to start doing more systems test.” And as more ICs are used in automotive applications, the distinction between consumer and automotive requirements is blurring, driving demand in other markets for higher precision test with parts-per-billion defectivity requirements.

“Intelligent test gets increasingly challenging as devices become more complex and as testing moves from distinguishing good from bad devices to figuring out how to repair and trim marginal devices to make them good,” adds Derek Floyd, Advantest director of business development, this year’s program chair.

“We’re highlighting efforts to create the infrastructure the industry needs to manage big data for machine learning with test platforms from different vendors,” says Ajouri, citing work on new standards for streaming data from the testers and labeling critical steps in consistent language to simplify the use of data from different platforms in real time. “I have 10 platforms from multiple vendors, and I need them to mean exactly the same thing by ‘lot’ so I don’t have to sort it out before I can use the data,” she says.

Are devices becoming too complicated to test at the required price point?

Can testing be economical with up to a million die per wafer, 50 data points per die, a requirement for parts-per-billion accuracy, and the need to identify parts that test good now but that might fail in the future? Organizers of the event invite chipmakers and test suppliers to debate the issue. “The speed of innovation in the semiconductor industry challenges test to keep pace,” notes Floyd. “The product we’re testing is always ahead of the product we have to test it with.”

The two-day event features sessions on automotive test; big data and machine learning for adaptive test; handling and interface issues such as over-the-air testing;  and a general session covering memory and RF test.

SEMICON West next week will host a White House-led discussion of the anticipated national leadership strategy for semiconductors, a multi-agency initiative led by top U.S. government national security and economic organizations.

On Wednesday, July 11, a panel of U.S. officials representing agencies involved in leading the strategy will address federal research and development (R&D), investment and acquisition priorities aimed at ensuring the U.S. remains the global leader in the semiconductor industry.

As global economic trends and technologies such as artificial intelligence evolve, and foreign governments increasingly lure microelectronics manufacturing investments overseas, the U.S. strategy for manufacturing advanced semiconductors and driving research and development (R&D) in technology innovation has become an economic priority.

The White House selected SEMICON West, organized by SEMI, as the site for the discussion and this urgent call to action because of the event’s central role in bringing together critical industries across the global electronics supply chain. The multi-agency panel will outline activities and new policies under development to ensure U.S. strategic leadership in microelectronics, including focused investment in innovations key to the next generation of devices for commercial and government use. The initiative also includes public-private partnerships to accelerate the capabilities of advanced semiconductors for critical applications such as artificial intelligence (AI), cyber, secure communications, the internet of things (IoT) and big data analytics.

PANEL:
National Strategy for Semiconductor and Microelectronic Innovation
TIME AND DATE:
10:30 to 11:30 a.m., Wednesday, July 11
LOCATION:
Yerba Buena Theater, 700 Howard St., San Francisco
MODERATOR:
Dr. Lloyd Whitman, Principal Assistant Director, Physical Sciences and Engineering, White House Office of Science and Technology Policy
PANELISTS:
Dr. Sankar Basu, Program Director, Computer and Information Science and Engineering, National Science Foundation
Dr. Eric W. Forsythe, Flexible Electronics Team Leader, U.S. Army Research Laboratory
Dr. Jeremy Muldavin, Deputy Director of Defense Software & Microelectronics Activities, Office of the Deputy Assistant Secretary of Defense for Systems Engineering
Dr. Robinson Pino, Acting Research Division Director, Advanced Scientific Computing Research, Office of Science, Department of Energy

 

SEMICON West is organized by SEMI Americas to connect more than 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMICON West is celebrating its 47th year as the flagship event for the semiconductor industry. Find more at www.semiconwest.org.

By Paula Doe, SEMI

The fast-maturing infrastructure that is enabling applications for big data and artificial intelligence means disruptive change not just at individual companies but also in data connections among companies across the microelectronics manufacturing value chain. SEMI checked in with some leading players on the changes they see coming in the next several years for this article series. The trade group is expanding its programming on smart manufacturing to address these industry-wide developments at SEMICON West, July 10-12 in San Francisco.

“The ramp of EUV, and the smaller geometries and smaller process margins, will drive an exponential increase in the amount of metrology data to manage,” says Neal Callan, ASML vice president, Silicon Valley. Callan notes that moving to multibeam e-beam inspection will increase data volume from megabytes per second to gigabytes per second and from thousands of data points to millions of data points. “The process is so tight and the margin so small that stochastic variation, or noise, becomes more dominant – at least it’s noise until we can learn to understand and control it. And understanding and controlling this variation will be key to delivering 5nm patterning,” he says.

Single-beam e-beam inspection is already driving large increases in data as engineers extend the slow technology to broad, high-speed defect metrology applications by more intelligently instructing the system where to look for problems. Callan says ASML is now using the scanner data on wafer focus, alignment and leveling. The company is also using the computational lithography model from the design to identify the smallest process windows in the pattern that are most likely to see problems. The model then quantifies the number and significance of those instances.

“The collection of all this diverse data means that tools will need to be plug-and-play so all tool data is instantly available to all systems and software,” says Doug Suerich, PEER Group product evangelist. “We need tools that can be discovered automatically by the network so it can start slurping up data immediately. The adoption of the Interface A (EDA) standard is accelerating and fabs are starting to ask for it. The proliferation of sensors also needs to self-discover. If you are going to add thousands of new sensors into a facility, you can’t afford a time-consuming integration process.”

“We are now seeing that engineers are greedy for more data – if they can get the data, it’s becoming a need-to-have,” adds Tom Ho, BISTel America president. “Getting more data from more sensors, from the sensors on the tool that are not being fully utilized, and from untapped data sources like vibration is another big coming opportunity.”

Process complexity drives demand for feed forward between silos with computational models

ASML co-optimizes its scanner process with etch and reticle process steps. Source: ASML

In addition to the drive for trace-back of data, the increasing complexity of interrelated processes is also driving demand for feed-forward of data. “Feed-forward is becoming more important,” notes Ho. He points to the example of 3D NAND features, now getting so deep that identifying the layer being measured is a challenge unless the signal at the step before can be recognized.

“We need partnerships with our peers to understand how to take advantage of the sensors they use, integrate them with our data, and then feed-forward corrections to the other systems,” concurs Callan. “To drive the best CD uniformity and overlay, we need to co-optimize litho and etch,” agrees Henk Niesing, ASML director of product management. He notes that the company is working with etcher makers to measure the overlay and CD, decompose the finger prints, and then use models to steer automated control that best adjusts both the scanner and the etcher. ASML is also working with Zeiss on co-optimization between the scanner and the reticle to make even higher-order corrections by locally modifying the reticle.

These higher-order corrections, applied on each exposed field, drive the need for even more data, and at higher speed but without higher cost, notes Jan Mulkens, ASML senior fellow. These corrections increase demand for computational metrology, which combines various metrology sources with physics and deep learning models trained on real data to predict and control process results in real time. “We’re working on computational metrology to ideally use all the knobs we have in the fab,” he says.

So far this effort has largely involved linking data between two companies. More consistent data formats would enable data exchange to be extended to more companies. “The software versions also need to be managed for upgrades so they still match after one party updates the system on its tool,“ notes Niesing.

Speakers on these issues of smart manufacturing and data handling at SEMICON West include Active Layer Parametrics, Applied Materials, Applied Research & Photonics, ASML, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital,  Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Seimens, Stanford University, TEL, TIBCO Software. See semiconwest.org

By Paula Doe, SEMI

The fast-maturing infrastructure now enabling applications for big data and artificial intelligence means disruptive change not just at individual companies but also in data connections among companies across the microelectronics manufacturing value chain. SEMI expands its smart manufacturing program with a Smart Manufacturing Pavilion with displays and three full days of talks to address these industry-wide developments at SEMICON West, July 10-12 in San Francisco.

Autonomous autos’ demand for zero-defect systems and 100 percent traceability back to the manufacturing data for each die is driving a push to traceability across the chip sector. “Far more chips are being used by the automotive sector, and its very different requirements are driving demand for traceability,” says Tom Ho, president of BISTel America. “Our chipmaker customers are looking for traceability solutions and the trend is the same in backend packaging and assembly – automotive applications are driving the sector to traceability.”

Traceability is also driven by the growth of systems in a package as fabless chipmakers look to connect back to the packaging companies’ fault analysis labs and die interconnect history to diagnose and fix the cases where known-good die are failing in the system, adds Mike Plisinski, CEO of Rudolph Technologies. Plisinski adds that makers of consumer products like phones that can also see harsh conditions are demanding higher quality and traceability as well.

The EMS sector also must establish an architecture for traceability to collect critical manufacturing-related data and to interface with OSATs and semiconductor fabs. The reason is that EMS companies are adding traditional OSAT processes such as assembly of products with bare die and complex optics modules requiring clean rooms. “A unified sand-to-smart-phone smart manufacturing roadmap should be established,” says Dan Gamota, vice president of  Engineering and Technology Services at Jabil. “We need to identify protocols for manufacturing data communications that can be adopted across the supply chain.”

To enable smart manufacturing, vendors need to collaborate on getting their production equipment to interoperate and support factory analytics and data management systems. Source: SEMI

One big challenge, of course, is how to format this diverse data so it can be linked and used by  various supply chain stakeholders. “Smart data needs to be contextual and it needs data standards across the supply chain so it’s easy to link from the front end to the back end, follow common lot IDs front and back end, and have a way to map streaming data from sensors to a discrete lot ID,” notes Ho. New approaches to metrology, analysis and test that increasingly exploit machine learning on simulations will also be needed to help predict which die and connections that test well now may fail in the future as conditions change.

Another issue is how to securely share the needed data across companies without jeopardizing IP. “On the equipment side we collect data across customers on how the tool is running to improve the equipment,” notes Neal Callan, ASML VP Silicon Valley. “Next we need to integrate performance and reliability data that today is not as well shared.”

 

The other big hurdle is how to pay for data sharing. “The challenge is that the final manufacturers reap the benefit of traceability, but since they expect their suppliers to deliver good die, they don’t want to pay more for it,” notes Plisinski.  He suggests that over the next two to three years, traceability and predictive fault prevention will become the norm as the automotive sector is compelled to invest in it to assure safety. Meanwhile, fabless companies will face so much complexity in integrating different die from different suppliers in SiP that they will no longer be able to afford to simply use the cheapest supplier, potentially driving a fundamental shift in relations and division of labor among fabless chipmakers, OSATs and fabs.

Standards extend across supply chain

SEMI member committees are collaborating to build the infrastructure to enable these developments. Standards committees are updating standards for higher bandwidth data exchange and extending semiconductor-like vertical and two-way horizontal equipment communication standards to flow shops to enable assembly players to optimize and trace back results across players. The SMT/PCBA community is integrating its smart manufacturing work into SEMI standards, and the SEMI A1 standard was a key reference document in the development of the Japan Robotics Association’s Equipment Link Protocol.

Speakers addressing these issues at SEMICON West include Active Layer Parametrics, Applied  Materials, Applied Research & Photonics, ASML, Bosch Rexroth, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital,  Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Qualcomm, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Siemens, Stanford University, TEL, TIBCO Software. See semiconwest.org

By Paula Doe, SEMI

For medtech applications to flourish, sensors need a supporting infrastructure that translates the data they harvest into actionable insights, says Qualcomm Life director of business development Gene Dantsker, who will speak about the future of digital healthcare in the Medtech program at SEMICON West. “Rarely can one device give a complete diagnosis,” he notes. “What’s missing is the integration of all the sensor data into prescriptive information.”

The maturing medtech sector has developed to the point where sensors can now capture massive amounts of data, conveniently collected from people via mobile devices. The sector now has higher compute capacity to process the data, and improving software can produce actionable insight from the information. The next challenge is to seamlessly integrate these components into legacy medical systems without disrupting existing workflow. “Doctors and nurses don’t have time for disruptive technology – a new system has to be invisible and frictionless to use, with one or fewer buttons, no training and truly automatic Bluetooth-like pairing,” he says. “So device makers need to pack all system intelligence into the circuits and software.”

Getting actionable healthcare information from sensors requires integration into the existing medical infrastructure. Source: Qualcomm Life

One interesting example is United Healthcare’s use of the Qualcomm Life infrastructure to collect data from the fitness trackers of 350,000 patients. The insurance company then pays users $4 a day, or ~$1500 a year, for standing, walking six times a day and other behaviors that clinical evidence shows will both improve patient health and reduce healthcare costs. “It’s a perfect storm of motivations for all stakeholders,” he says.

Next hot MEMS topics: Piezoelectric devices, environmental sensors, near-zero power standby

With sensor technology continuing to evolve, look for coming innovations in MEMS in piezoelectric devices, environmental sensors and near zero-power standby devices, says Alissa Fitzgerald, Founder and Managing Member of A.M. Fitzgerald and Associates, who will provide an update on emerging sensor technologies in the MEMS program at SEMICON West.

Piezoelectric devices can potentially be more stable and perhaps even easier to ramp to volume than capacitive ones, with AlN devices for microphones and ultrasonic sensors finding quick success. Now the maturing infrastructure for lead zirconate titantate (PZT) is enabling the scaling of production of higher performing piezo material with thin film deposition equipment from suppliers like Ulvac Technologies and Solmates and in foundry processes at Silex and STMicroelectronics, she notes.

In academic research, where most new MEMS emerge, market interest is driving development of environmental sensors and zero-power standby devices. With demand for environmental monitoring growing, much work is focusing on technologies that improve the sensitivity, selectivity and time of response of gas and particulate sensors. Research and funding is also focusing on zero or near-zero power standby sensors, using open circuits that draw no power until a physical stimulus such as vibration or heat wakes them up.

MEMS, however, likely won’t find as much of a market in autonomous vehicles as once thought. “While the automotive sensor market will need many optical sensors, MEMS players are competing with other optical and mechanical solutions,” says Fitzgerald. “And here the usual MEMS advantage of small size may not matter much, and the devices will have to meet the challenging automotive requirements for extreme ruggedness.”

By Paula Doe, SEMI

With artificial intelligence (AI) rapidly evolving, look for applications like voice recognition and image recognition to get more efficient, more affordable, and far more common in a variety of products over the next few years. This growth in applications will drive demand for new architectures that deliver the higher performance and lower power consumption required for widespread AI adoption.

“The challenge for AI at the edge is to optimize the whole system-on-a-chip architecture and its components, all the way to semiconductor technology IP blocks, to process complex AI workloads quickly and at low power,” says Qualcomm Technologies Senior Director of Engineering Evgeni Gousev, who will provide an update on the progress of AI at the edge in a Data and AI program at SEMICON West, July 10-12 in San Francisco.

Qualcomm Snapdragon 845 uses heterogeneous computing across the CPU, GPU, and DSP for power-efficient processing for constantly evolving AI models. Source: Qualcomm

A system approach that optimizes across hardware, software, and algorithms is necessary to deliver the ultra-low power – to a sub 1-milliwatt level, low enough to enable always-on machine vision processing – for the usually energy-intensive AI computing. From the chip architecture perspective, processing AI workloads with the most appropriate engine, such as the CPU, GPU, and DSP with dedicated hardware acceleration, provides the best power efficiency – and flexibility for dealing with rapidly changing AI models and growing diversity of applications.

“But we’re going to run out of brute force options, so the future opportunity is more innovations with new architectures, dedicated hardware, new algorithms, and new software.” – Evgeni Gousev, Qualcomm Technologies

“So far it’s been largely a brute force approach using conventional architectures and cloud-based infrastructure,” says Evgeni. “But we’re going to run out of brute force options, so future opportunities lie in developing innovative architectures, dedicated hardware, new algorithms, and new software. Innovation will be especially important for AI at the edge and applications requiring always-on functionality. Training is mostly in the cloud now, but in the near future it will start migrating to the device as the algorithms and hardware improve. AI at the edge will also  remove some privacy concerns,  an increasingly important issue for data collection and management.”

Practical AI applications at the edge where resources are constrained run the gamut, spanning smartphones, drones, autonomous vehicles, virtual reality, augmented reality and smart home solutions such as connected cameras. “More AI on the edge will create a huge opportunity for the whole ecosystem – chip designers, semiconductor and device manufacturers, applications developers, and data and service providers. And it’s going to make a significant impact on the way we work, live, and interact with the world around us,” Evgeni said.

Future generations of chips may need more disruptive systems-level change to handle high data volumes with low power

A next-generation solution for handling the massive proliferation of AI data could be a nanotechnology system, such as the collaborative N3XT (Nano-Engineered Computing Systems Technology) project, led by H.S. Philip Wong and Subhasish Mitra at Stanford. “Even with next-generation scaling of transistors and new memory chips, the bottlenecks in moving data in and out of memory for processing will remain,” says Mitra, another speaker in the SEMICON West program. “The true benefits of nanotechnology will only come from new architectures enabled by nanosystems. One thing we are certain of is that massively more capable and more energy-efficient systems will be necessary for almost any future application, so we will need to think about system-level improvements.”

Major improvement in handling high volumes of data with low high energy use will require system-level improvements, such as monolithic 3D integration of carbon nanotube transistors in the multi-campus N3XT chip research effort. Source: Stanford University

That means carbon nanotube transistors for logic, high density non-volatile MRAM and ReRAM for memory, fine-grained monolithic 3D for integration, new architectures for computation immersed in memory, and new materials for heat removal. “The N3XT approach is key for the 1000X energy efficiency needed,” says Mitra.

“One thing we are certain of is that massively more capable and more energy efficient systems will be necessary for almost any future application, so we will need to think about system-level improvements.” – Subhasish Mitra, Stanford University

Researchers have demonstrated improvements in all these areas, including multiple hardware nanosystem prototypes targeting AI applications. The researchers have transferred multiple layers of as-grown carbon nanotubes to the target wafer to significantly improve CNT density. They have developed a low-power TiN/HfOx/Pt ReRAM whose low-temperature CNT and ReRAM processes enable multiple vertical layers to be grown on top of one another for ultra-dense and fine-grained monolithic 3D integration.

Other speakers at the Data and AI TechXpot include Fram Akiki, VP Electronics, Siemens; Hariharan Ananthanarayanan, motion planning engineer, Osaro; and David Haynes, Sr. director, strategic marketing, Lam Research.  See SEMICONWest.org.

Each year at SEMICON West, the “Best of West” awards are presented by Solid State Technology and SEMI. More than 26,000 professionals from the electronics manufacturing supply chain attend SEMICON West and the co-located Intersolar. The “Best of West” award was established to recognize new products moving the industry forward with technological developments in the electronics supply chain.

Selected from over 600 exhibitors, SEMI announced today that the following Best of West 2018 Finalists will be displaying their products on the show floor at Moscone Center from July 10-12:

  • Advantest: T5503HS2 Memory Tester— The T5503HS2 memory tester is the industry’s most productive test solution for the fastest memory devices available today as well as next-generation, super-high-speed DRAMs.  The new system’s flexibility extends the capabilities of the T5503 product family in the current “super cycle,” in which global demand for memories is skyrocketing. (South Hall Booth #1105)
  • BISTel: Dynamic Fault Detection (DFD®) – The DFD system offers full trace data coverage and eliminating the need for timely and costly modeling and set up. DFD® is also a bridge to smart factory manufacturing because it integrates seamlessly to legacy FDC systems meaning customers can access the most comprehensive, and accurate fault detection system on the market. (South Hall Booth 1811)
  • Rudolph Technologies: Dragonfly System with Truebump Technology– Rudolph’s Dragonfly System with Truebump Technology was designed to provide a complete solution for “total bump process control.” Using a unique approach, Truebump Technology combines 2D inspection and measurement information from image-based techniques with 3D data from separate high-precision and high-throughput laser-based techniques to deliver accurate and complete characterization at production-capable throughputs. (North Hall Booth #6170)

Congratulations to each of the Finalists. The Best of West Award winner will be announced during SEMICON West (www.semiconwest.org) on Wednesday, July 11, 2018.

About SEMI

SEMI® connects over 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMI members are responsible for the innovations in materials, design, equipment, software, devices, and services that enable smarter, faster, more powerful, and more affordable electronic products. FlexTech, the Fab Owners Alliance (FOA) and the MEMS & Sensors Industry Group (MSIG) are SEMI Strategic Association Partners, defined communities within SEMI focused on specific technologies. Since 1970, SEMI has built connections that have helped its members prosper, create new markets, and address common industry challenges together. SEMI maintains offices in Bangalore, Berlin, Brussels, Grenoble, Hsinchu, Seoul, Shanghai, Silicon Valley (Milpitas, Calif.), Singapore, Tokyo, and Washington, D.C.  For more information, visit www.semi.org and follow SEMI on LinkedIn and Twitter.

About Extension Media

Extension Media is a publisher of over 20 business-to-business magazines (including Solid State Technology), resource catalogs, newsletters and web sites that address high-technology industry platforms and emerging technologies such as chip design, embedded systems, software and infrastructure, intellectual property, architectures, operating systems and industry standards. Extension Media publications serve several markets including Electronics, Software/IT and Mobile/Wireless. Extension Media is a privately held company based in San Francisco, Calif. For more information, visit www.extensionmedia.com