Category Archives: Semicon West

Sparking conversation is a goal of SEMICON West, and SEMI Americas and Applied Materials invite working journalists across the electronics spectrum to a special AI Design Forum luncheon on Tuesday, July 10, from noon to 1:30 p.m., at The Forum at the Yerba Buena Center for the Arts, 701 Mission Street, in San Francisco. The event is presented in conjunction with SEMICON West at the Moscone Center.

In addition to the exchange of fresh news, ideas and insights on industry trends, executives from SEMI Americas and Applied Materials will host an interview by John Markoff of The New York Times with Dr.  David Patterson of Google. Patterson is known for his pioneering contributions to reducing the design complexity of MIPS, RISC and other microprocessors found in most chips today. A former professor of computer science at UC Berkeley and a distinguished engineer at Google, he is co-recipient of the 2017 Turing Award, widely regarded as the Nobel Prize for computer science.

Like this special lunch session, almost everything about SEMICON West is stronger this year.  Led by 200 industry leaders and visionaries, conversation topics are far-ranging, with special focus on five industries that promise to define future electronic devices: artificial intelligence (AI), automotive electronics, biotechnology, smart manufacturing and IoT. The event will also tackle the tough question of how to attract new talent into a global industry that requires greater creativity, innovation, and ingenuity to deliver the electronic advantages for tomorrow.

To reserve your seat at this special luncheon event, request your press credentials for free attendance at www.semiconwest.org/registration. Seating is limited and available until June 26 per your RSVP to [email protected].

What’s on the SEMICON West Program

Keynote speakers:

  • Dr. John E. Kelly, III, Senior Vice President, IBM Cognitive Solutions and IBM Research
  • Gary Dickerson, Chief Executive Officer, Applied Materials
  • Amir Husain, Chief Executive Officer, SparkCognition
  • Dr. Melissa Schilling, Professor, New York University
  • Dr. William Dally, Chief Scientist, nVIDIA
  • Mark Papermaster, Chief Technology Officer, Advanced Micro Devices
  • Dr. Wolfgang Juchmann, Vice President, Business Development, AutonomouStuff

 

  • AI Design Forum: The AI era is expected to be the largest and longest-lived of any in electronics history. This Forum, sponsored by Applied Materials, will present new approaches to computing and device architectures required to drive widespread AI adoption.
  • Semi Venture Funding Gaps and Solutions: With semiconductor and hardware investments dwindling in the U.S. and Europe due to rising capital requirements and development costs, a map will be shared for how to maintain technological leadership in future semiconductors.
  • Smart Manufacturing Pavilion: Marked by explosive growth in data availability, AI, biomed, IoT and other information sources are driving demand for new technologies. The Pavilion features data-sharing breakthroughs that can create smarter manufacturing processes, increase yields and profits, and spur innovation across the industry.
  • Smart Transportation Pavilion: Leading all new application spaces for chip growth, the transportation market promises great potential for related segments like FHE and MEMS and Sensors.
  • Smart Workforce Pavilion: Sustaining the industry’s pace of innovation and growth has become a top priority for companies. With chip businesses facing stiff competition from other tech-related segments, the Pavilion’s mission is to inform entry-level prospects that microelectronics is a smart career choice.

SEMICON West is organized by SEMI Americas to connect more than 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMICON West is celebrating its 47th year as the flagship event for the semiconductor industry.

With the rapid rise of AI providing overwhelming possibilities for industry growth, SEMICON West has been designed to help the microelectronics industry get a firm handle on how best to enable and take advantage of AI’s potential. From the lab to the fab, and from design through system, the benefits from conversations at the event will be felt across transportation, medical, manufacturing, IoT and Big Data.

With the world’s interest racing toward how Artificial Intelligence (AI) can accelerate so many things, six visionary keynoters will reveal what lies ahead for semiconductors and society. Forecasting tomorrow’s trends and their impacts, the keynoters plan to illustrate the semiconductor’s path to enabling a global state of “Beyond Smart.” Complementing the keynotes, nearly 120 experts from multiple disciplines will analyze pivotal aspects of trends that are driving the emerging markets for microelectronics. This year’s preeminent event, SEMICON West, will be held at the Moscone Center in San Francisco, July 10-12.

“SEMICON West is the timeless home where the world’s next innovations are previewed and accelerated,” said David Anderson, President of SEMI Americas. “With the dawn of the AI era ramping up globally, we’ve assembled the richest lineup of talent and resources in SEMI history.”

BEYOND SMART

Through both artificial and organic cognition, the ways that intelligence is being cultivated will be profiled and mapped by world-renowned keynoters:

  • Dr. John E. Kelly, III, Senior Vice President, IBM Cognitive Solutions and IBM Research
  • Gary Dickerson, Chief Executive Officer, Applied Materials
  • Amir Husain, Chief Executive Officer, SparkCognition, and author of The Sentient Machine: the Coming Age of Artificial Intelligence
  • Dr. Melissa Schilling, Professor, New York University Stern School of Business and author of Quirky: The Remarkable Genius of Breakthrough Innovators Who Changed the World
  • Mark Papermaster, Chief Technology Officer, Advanced Micro Devices
  • Dr. Wolfgang Juchmann, Vice President, AutonomouStuff

Dr. Kelly of IBM has shared in interviews that he was an “early-on” believer in Moore’s Law, where he built much of his career. Now, he sees the industry embarking on the early part of an “AI’s Law.” He is focused on IBM’s investments in several new and future areas of the fastest-growing and most strategic parts of the information technology market. He also oversees the specialization of IBM Watson into various industries and domains.

Gary Dickerson of Applied Materials is as well-versed as anyone about the history, and future, of the chip business. In addition to Applied, he also has led semiconductor equipment companies Varian Equipment and KLA-Tencor in their top executive positions for 25 years. His insights to be presented at SEMICON West will include first-hand knowledge of how the markets are changing and where will be the opportunities for the toolmaking and chipmaking businesses.

Amir Husain of SparkCognition argues — from his background as an inventor and computer scientist — that with AI, the chip industry is on the cusp of writing its next, and greatest, creations. Also author of The Sentient Machine, he’ll examine for the audience what complex computer science and AI concepts will mean for a wide variety of chip technologies, including the resulting cultural benefits and challenges. Husain is an advocate for embracing AI in order to advance the state of the art in many critical fields, including security, resource management, finance and energy.

Dr. Melissa Schilling of NYU’s Stern School of Business will speak about “creative genius” as partial reflection of her research focus on innovation and strategy in high-tech industries such as smartphones, gaming, pharmaceuticals, biotechnology, electric vehicles and renewable energies. She’s well-studied in platform dynamics, networks, creativity and breakthrough innovation. As author of several innovation strategy textbooks and the recently released book Quirky, she suggests that regardless of whether an innovator is a one-hit wonder or a serial disruptor, a common thread among those introverts and extroverts alike is their cultivation of talents for the benefit of society.

Mark Papermaster of AMD is a veteran of silicon engineering at Apple, Cisco and IBM. He’s responsible for corporate technical direction, product development including system-on-chip (SOC) methodology, microprocessor design, I/O and memory, and advanced research. He also oversees Information Technology to deliver AMD’s compute infrastructure and services. From his leadership roles managing the development of products — from microprocessors to mobile devices and high-performance servers — Papermaster will offer his insights and forecasts around the inflection points for semiconductor applications and AI.

Dr. Wolfgang Juchmann of AutonomouStuff is expert in future automotive options and with the technologies that enable perception sensors, LiDAR and autonomous vehicles. He will include discussion of how and where advanced autonomous driving tasks will rely on new capabilities for radar, vision and ultra-sonic sensors, real-time 3D data fusion middleware, fully by-wire controllable autonomous development vehicles and modular software algorithms.

By Deb Vogler

This year’s Advanced Lithography TechXPOT at SEMICON West will explore the progress on extreme ultra-violet lithography (EUVL) and its economic viability for high-volume manufacturing (HVM), as well as other lithography solutions that can address the march to 5nm and onward to 3nm. Several session speakers offered their insights into the readiness of EUVL for 5nm and how other lithography solutions will enable 3nm. See the full list of speakers and program agenda at http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.

Diverging viewpoints on EUVL readiness for 5nm

Mike Lercel, Director of Strategic Marketing at ASML

ASML expects its first customer to start volume manufacturing with EUV at the 7nm logic node and the mid-10nm DRAM node in the 2018/2019 timeframe. “EUV will replace the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future,” said Lercel. “For the 5nm logic node, more layers are expected to migrate to EUV.”

Three ASML customers have early-access versions of the next-generation TWINSCAN NXT:2000i for the development of advanced logic and DRAM nodes. “This system delivers 2.0nm cross-matched on-product overlay, achieved through several hardware advancements,” noted Lercel. “It is also significant because this mix-and-match use with EUV features a significantly different hardware platform.” TWINSCAN NXT:2000i features a new alignment sensor and improved wafer table flatness, endurance, and clamping mechanism to enhance matching to EUV.

ASML has achieved good industrialization progress of its pellicle, with tests confirming that pellicles can withstand 245W source power and an offline power lifetime test indicating 400W capability. Compared to the 7nm logic node, the requirements for EUV masks will become tighter at 5nm, but Lercel noted that ASML sees good progress with the industry infrastructure to support 5nm in areas such as reducing mask blank defects. “We will continue to improve pellicle transmission for enhanced throughput, but there are no fundamental changes in pellicle requirements for 5-3nm logic nodes. We see no infrastructure showstoppers for the introduction of EUVL at the 5nm node.”

Stephen Renwick, Director of Imaging Physics at Nikon Research Corporation of America

Renwick said that the 7nm logic node is expected to be fabbed mostly using 193i lithography. “EUV will struggle to be ready for 5nm, limited by yield issues caused by stochastic effects in the resist,” said Renwick. “Ready or not, though, it will be used.” Renwick suggests that introducing multiple-patterning with EUV may be needed but would increase costs. “193i lithography will continue to be used with quadruple-patterning and in combination with other techniques – there is no single solution.”

Figure 1. Normalized cost/layer vs. lithography method. SOURCE: Nikon Research Corporation of America

When choosing between immersion lithography and EUV for different customer segments at 5nm, Renwick noted that the cost depends on the layer. “Some time ago, we calculated that the costs of either 193i triple-patterning or 193i SADP with two cuts were roughly equal to single-patterning with EUV,” explained Renwick (Figure 1). “That agreed with chipmakers’ public estimates and meant that the choice of lithography method depended more on the performance tradeoffs involved, such as 193i’s better line-edge roughness. At the 5nm node, we are probably faced with quad-patterning from 193i, double-patterning from existing EUV tools, or single-patterning from as-yet undelivered high-numerical aperture (NA) EUV tools.” Renwick believes that the competition between low-NA EUV double-patterning and 193i quad-patterning will be similar to the current situation (i.e., comparison of 193i triple-patterning or 193i SADP with two cuts vs. single-patterning with EUV), but for high-NA EUV tools he believes it’s too early to say.

Other challenges Renwick sees on the horizon for EUVL at 5nm are stochastic effects in EUV resists. “They cause yield problems on contact arrays and unacceptable line-edge roughness on line/space patterns,” said Renwick. “It’s unlikely that these effects will go away without increasing the litho dose, which will further challenge throughput performance.” He also questions whether EUV pellicles, though under development, will be “ready for prime time.”

Harry Levinson, Sr. Director of Strategic Lithography Technology and Sr. Fellow at GLOBALFOUNDRIES

Levinson said additional fundamental engineering work is needed to ready EUV lithography for 5nm. “Among the top problems are stochastics-induced resist defects, which increase significantly as dimensions shrink below those for 7nm,” explained Levinson (Figure 2). “Higher exposure doses will be required to address these issues related to stochastics at 5nm, which will require higher source output” (than 7nm).

Levinson said there will be greater motivation to use EUVL at the 5nm node vs. at 7nm to offset the large number of exposures associated with 193nm immersion multiple-patterning solutions. “The primary application of EUV lithography at 7nm will be for contact, via and cut layers,” Levinson noted. “It will be important to enable EUVL for metal masks at the 5nm node, which increases the need for an ample supply of very low defect EUV mask blanks.” Levinson added that the 7nm node is already stressing defect inspection capabilities, and no actinic defect inspection system is yet available for patterned masks. “This situation becomes more problematic with widespread application of EUVL to metal layers.”

Mask development for 5nm

Christopher C. Progler, CTO & Strategic Planning at Photronics

Progler said that the basic infrastructure for delivering EUV masks is available, especially for dark field layers and near in nodes. “The interconnected or more open frame patterns will need refinements to the processes and two to three nodes out will need certain new infrastructure,” said Progler. Overall, the main challenges for initial insertion are about creating a cost-effective and rapid-turn EUV mask process, he said. “The industry can certainly deliver EUV masks in some form. It is more a question of doing it efficiently and productively to match the stated value proposition of EUV over other lithographic methods. We don’t want a pick two of ‘cost, cycle time, capability’ sort of mask solution.”

More specifically, Progler explained that after the initial EUV mask development for 5nm focused on contacts and block layers, the major push for N5 switched to delivering single-exposure EUV metal patterning as early as possible. “This has opened some new challenges for masks given the resolution, critical pattern density and tight pitch defect requirements of the re-aggregated single-layer metal mask designs,” said Progler. “For example, on the resolution side, we are accelerating the insertion of higher dose photoresists and also driving patterning module improvements in CD control, mask LER and sidewall angle.” Progler added that at N5, the mask 3D structure itself – including the sidewall – will have a greater impact on lithography because it is tied to stochastic error rates on the wafer.

“Reliable, wide-area metrology for some of these 2D and 3D mask parameters is currently hard to come by. We may see an evolution of the blank structure at some point in N5, including hard mask options for pattern stability and expect earlier insertion of EUV mask process correction with model-based hot spot detection and rule checking as well. We also hope mask-scanner dedication is not needed, but there are some indications process sensitivity may push us earlier in this direction.” He added that to reduce metal layer defects, more attention needs to be devoted to advanced repair and model-based validation. “We are, unfortunately, still in a situation of blurry vision and high native defect counts alongside possible in situ contamination during mask changes.”

Figure 2. Resist stochastics-induced defects. Graph courtesy of Peter DeBisschop, imec; Source: GLOBALFOUNDRIES

Progler pointed out that, with the advent at 5nm, metal masks will require some level of actinic blank inspection for yield, increasing the cost of an already expensive mask technology. “So, unless we want to contend with double and triple photomasks’ starts to deliver a single metal layer, it will be very important to tighten the multi-sensor inspection, defect abatement, and repair loops,” said Progler. He does see some clouds forming around high-volume manufacturing pellicles for metal layers. “This remains an open question, mainly for thermal and materials reasons, not to mention cost and cycle time,” Progler said. “We may be pessimistic, but we do not see an HVM pellicle solution converging in the required timeframe, which means leaning even more on a wafer-level inspection in the validation loop.” He believes that streamlining validation will be a differentiator. “I can imagine one losing most of the EUV cycle time benefits by endlessly circling masks around if this is not done well.”

How does the industry get to 3nm?     

ASML plans to ship its first high-NA EUV prototope/pilot systems between 2020 and 2023 to support 3-2nm process development. “System designs are now being finalized and the platform is starting to come to life,” said Lercel. ASML supplier ZEISS is building a high-NA cleanroom for optics production. ASML believes that EUV, high-NA and DUV systems will be used together at the most advanced nodes and is designing to account for this mixed environment. “As chipmakers drive toward smaller geometries in the most advanced nodes like 3nm, they face unprecedented challenges in devices and materials. This will make the process control requirements even more challenging.” ASML is tackling these challenges with its YieldStar metrology platform, e-beam metrology (HMI) and computational lithography solutions that are designed to expand the process window, enhance process control, and improve patterning defect detection. “This ‘Holistic Lithography’ approach will become increasingly important to ensure throughput and yield at the most advanced nodes.”

Levinson said that the issues he projects for 5nm will need to be addressed further at 3nm. “The challenges associated with resists at 3nm dimensions are such that it isn’t clear that chemically amplified resists will be capable of meeting requirements,” said Levinson. “If true, we would be seeing the most significant change in resist platforms in a quarter of a century. Potentially cost-reducing technologies such as directed self-assembly (DSA) are always welcome, but EUVL will be the lithographic workhorse through the 3nm node, and likely beyond.”

At 3nm, mask makers will confront the realities of higher EUV NA tools. “We will need to implement thinner mask absorbers, new films, and perhaps hard masks,” Progler said. “This puts us in a new materials regime for masks, and history has shown us the mask industry takes a long time to refine processes and tools for new mask materials.” He explained that the small scale of the mask ecosystem and the small number of large suppliers available to address the challenges accounts for this lengthy time frame.

Still, looking ahead, Progler noted that Photronics has already done a few studies on the impact of proposed half-field, high NA anamorphic optics on masks. “We uncovered some challenges that need to be addressed, particularly at boundaries and within the overall mask flow,” said Progler. As mask resolution continues to scale down, the industry will need fundamentally higher resolution mask making and inspection processes, requiring next-generation multi-beam mask writing and electron beam inspection, he explained.

At 3nm and below, Progler noted that the metrology needs for masks, while not as severe as that for wafers at these nodes, will test the mask equipment infrastructure in ways that could challenge the relatively small mask industry. “Of course, EUV multi-patterning comes into play as well, and with that, the SRAF sizes will drop below 20nm, requiring an asymmetric compensation over a much wider influence area than the OPC people are used to considering.” With EUV multi-patterning, Progler explained that it will be increasingly important to match or pair EUV masks and to consider how 3D effects and stochastics will drive new technology to enable new requirements for high-speed metrology and simulation components. “All the justifiable hand-wringing over EPE with ArF multi-patterning today gets introduced to the EUV scene when masks are ganged together to make a single device layer,” said Progler.

Originally published on the SEMI blog.

SEMI, the global industry association representing the electronics manufacturing supply chain, today announced that the WT | Wearable Technologies Conference 2018 USA will co-locate July 11-12 with SEMICON West 2018 in San Francisco. The electronics industry’s premier U.S. event, SEMICON West — July 10-12 at Moscone North and South — will highlight engines of industry expansion including smart transportation, smart manufacturing, smart medtech, smart data, big data, artificial intelligence, blockchain and the Internet of Things (IoT). Click here to register.

“We are excited that the WT | Wearables Technologies Conference has joined SEMICON West to co-locate in 2018,” said David Anderson, president of SEMI Americas. “Our strategic partnership brings new content and more value to our extended supply chain. Every day the semiconductor industry makes chips smaller and faster with ever-higher performance. These innovations enable new wearable applications for smart living, smart medtech and healthcare that are continuously improving our lives. The WT | Wearable Technologies Conference speakers at SEMICON West 2018 will demonstrate just how they use semiconductor technology to deliver leading-edge wearables.”

“It is a great pleasure to collaborate with the leading global electronics manufacturing association and its successful SEMICON West event,” said Christian Stammel, CEO of WT | Wearables Technologies. “Since the beginning of our platform in 2006, the semiconductor industry has been a major driver of wearables and IoT innovation. All major developments in the WT application markets like healthcare (smart patches), safety and security (tracking solutions), lifestyle and sport (smartwatches and wristbands) and in the industrial field (AR / VR) were driven by semiconductor and MEMS innovations. Our program of expert speakers at SEMICON West will share the latest insights in the wearables market as the SEMI and WT ecosystems explore collaboration and innovation opportunities.”

With the prospects of large 450mm wafers going nowhere, IC manufacturers are increasing efforts to maximize fabrication plants using 300mm and 200mm diameter silicon substrates. The number of 300mm wafer production-class fabs in operation worldwide is expected to increase each year between now and 2021 to reach 123 compared to 98 in 2016, according to the forecast in IC Insights’ Global Wafer Capacity 2017-2021 report.

As shown in Figure 1, 300mm wafers represented 63.6% of worldwide IC fab capacity at the end of 2016 and are projected to reach 71.2% by the end of 2021, which translates into a compound annual growth rate (CAGR) of 8.1% in terms of silicon area for processing by plant equipment in the five-year period.

capacity install

Figure 1

The report’s count of 98 production-class 300mm fabs in use worldwide at the end of 2016 excludes numerous R&D front-end lines and a few high-volume 300mm plants that make non-IC semiconductors (such as power transistors).  Currently, there are eight 300mm wafer fabs that have opened or are scheduled to open in 2017, which is the highest number in one year since 2014 when seven were added, says the Global Wafer Capacity report.  Another nine are scheduled to open in 2018.   Virtually all these new fabs will be for DRAM, flash memory, or foundry capacity, according to the report.

Even though 300mm wafers are now the majority wafer size in use, both in terms of total surface area and in actual quantity of wafers, there is still much life remaining in 200mm fabs, the capacity report concludes.  IC production capacity on 200mm wafers is expected to increase every year through 2021, growing at a CAGR of 1.1% in terms of total available silicon area. However, the share of the IC industry’s monthly wafer capacity represented by 200mm wafers is forecast to drop from 28.4% in 2016 to 22.8% in 2021.

IC Insights believes there is still much life left in 200mm fabs because not all semiconductor devices are able to take advantage of the cost savings 300mm wafers can provide.  Fabs running 200mm wafers will continue to be profitable for many more years for the fabrication of numerous types of ICs, such as specialty memories, display drivers, microcontrollers, and RF and analog products.  In addition, 200mm fabs are also used for manufacturing MEMS-based “non-IC” products such as accelerometers, pressure sensors, and actuators, including acoustic-wave RF filtering devices and micro-mirror chips for digital projectors and displays, as well as power discrete semiconductors and some high-brightness LEDs.

ASM International introduced the Intrepid® ESTM 300mm epitaxy (epi) tool for advanced-node CMOS logic and memory high-volume production applications. Intrepid ES introduces innovative closed loop reactor control technology that enables optimal within wafer and wafer-to-wafer process performance, critical for today’s advanced transistors and memories. Furthermore, Intrepid ES reduces the cost per wafer significantly for a 7nm epi process compared with prior node processes. The new tool has been qualified for production at a leading-edge foundry customer, and is targeting production applications in other industry segments as well. To date, over 40 reactors have been delivered.

“Over the past several years, multiple customers have been very clear that there is a need to address several technical and cost challenges in the epi market,” said Chuck del Prado, President and Chief Executive Officer of ASM International. “Intrepid ES is the result of a focused development program to address major challenges in this market, including film non-uniformity, process repeatability, tool uptime and high cost per wafer. This early success of the Intrepid ES clearly demonstrates that we are on track in addressing our customers’ emerging epi requirements.”

The new Intrepid ES tool is based on a combination of reactor and platform design improvements. It demonstrates improved film performance and enhanced reactor stability. Fundamental to its technology is an isothermal reactor environment in which the wafer is processed. This provides consistent and repeatable temperature control across the wafer and wafer-to-wafer.

By Ed Korczynski

Veeco Instruments (Veeco) recently announced that Veeco CNT—formerly known as Ultratech/Cambridge Nanotech—shipped its 500th Atomic Layer Deposition (ALD) system to the North Carolina State University. The Veeco CNT Fiji G2 ALD system will enable the University to perform research for next-generation electronic devices including wearables and sensors. Veeco announced the overall acquisition of Ultratech on May 26 of this year. Executive technologists from Veeco discussed the evolution of ALD technology with Solid State Technology in an exclusive interview just prior to SEMICON West 2017.

Professor Roy Gordon from Harvard University been famous for decades as an innovator in the science of thin-film depositions, and people from his group were part of the founding of Cambridge Nanotech in 2003. Continuity from the original team has been maintained throughout the acquisitions, such that Veeco inherited a lot of process know-how along with the hardware technologies. “Cambridge Nanotech has had a broad history of working with ALD technology,” said Ganesh Sandaren, VP of Veeco CNT Applied Technology, “and that’s been a big advantage for us in working with some major researchers who really appreciate what we’re providing.”

The Figure shows that the company’s ALD chambers have evolved over time from simple single-wafer thermal ALD, to single-wafer plasma-enhance ALD (PEALD), to a large chamber targeting batch processing of up to ten 370 mm x 470 mm (Gen2.5) flat-panels for display applications, and a “large area” chamber capable of 1m x 1.2m substrates for photovoltaic and FPD applications. The large area chamber allows customers to do things like put down an encapsulating layer or an active layer such as buffer materials on CIGS-based solar cells.

Evolution of Atomic-Layer Deposition (ALD) technology starts with single-wafer thermal chambers, adds plasma energy, and then goes to batch processing for manufacturing. (Source: Veeco CNT).

Evolution of Atomic-Layer Deposition (ALD) technology starts with single-wafer thermal chambers, adds plasma energy, and then goes to batch processing for manufacturing. (Source: Veeco CNT).

“There a tendency to think that ALD only belongs in the high-k dielectric application for semiconductor devices, but there are many ongoing applications outside of IC fabs,” reminded Gerry Blumenstock, VP and GM of MBE business unit and Veeco CNT. “Customers who want to do heterogeneous materials develop can now have MBE and ALD in a single tool connected by a vacuum cluster configuration. We have customers today that do not want to break vacuum between processes.” Veeco’s MBE tools are mostly used for R&D, but are also reportedly used for HVM of laser chips.

To date, Cambridge Nanotech tools are generally used by R&D labs, but Veeco is open to the possibility of creating tools for High-Volume Manufacturing (HVM) if customers call for them. “Now that this is part of Veeco, we have the service infrastructure to be able to support end-users in high-volume manufacturing like any of the major OEMs,” said Blumenstock. “It’s an interesting future possibility, but in the next six months to a year we’re focusing on improving our offering to the R&D community. Still, we’re staying close to HVM because if a real opportunity arose there’s no reason we couldn’t get into it.”

In IC fab R&D today, some of the most challenging depositions are of Self-Assembled Monolayers (SAM) that are needed as part of the process-flow to enable Direct Self-Assembly (DSA) of patterns to extend optical lithography to the finest possible device features. SAM are typically created using ALD-type processes, and can also be used to enable selective ALD of more than a monolayer. Veeco-CNT is actively working on SAM in R&D with multiple customers now, and claim that major IC device manufacturers have purchased tools.

At the leading edge of materials R&D, researchers are always experimenting with new chemical precursors. “Having a precursor that has good vapor-pressure, and is reactive yet somewhat stable is what is needed,” reminded Sundaram. “People will generally chose a liquid over a solid precursor because of higher vapor pressure. There are many classes of precursors, and many are halogens but they have disadvantages in some reactions. So we see continue to move to metal-organic precursors, which tend to provide good vapor-pressures and not form undesirable byproducts.”

By Pete Singer

Semiconductor manufacturers use a variety of high global warming potential (GWP) gases to process wafers and to rapidly clean chemical vapor deposition (CVD) tool chambers. Processes use high GWP fluorinated compounds including perfluorocarbons (e.g., CF4, C2F6 and C3F8), hydrofluorocarbons (CHF3, CH3F and CH2F2), nitrogen trifluoride (NF3) and sulfur hexafluoride (SF6). Semiconductor manufacturing processes also use fluorinated heat transfer fluids and nitrous oxide (N2O).

Of these, the semiconductor industry naturally tends to focus its attention on CF4 since it is one of the worst offenders, with an atmospheric half-life of 50,000 years. “CF4 the hardest to get rid of and it’s one of the worst global warming gases,” said Kate Wilson, VP Marketing, Subfab Solutions – Semiconductor Division of Edwards. “We tend to use that as an indicator of how much of the other global warming gases, as well, are being emitted by the industry. If we’re dealing with that (CF4) well, we tend to be managing the rest of the gases pretty effectively.”

According to the Environmental Protection Agency (EPA), estimating fluorinated GHG emissions from semiconductor manufacture is complicated and has required a significant and coordinated effort by the industry and governments. It was historically assumed that the majority of these chemicals were consumed or transformed in the manufacturing process. It is now known that under normal operating conditions, anywhere between 10 to 80 percent of the fluorinated GHGs pass through the manufacturing tool chambers unreacted and are released into the air.

In addition, fluorinated GHG emissions vary depending on a number of factors, including gas used, type/brand of equipment used, company-specific process parameters, number of fluorinated GHG-using steps in a production process, generation of fluorinated GHG by-product chemicals, and whether appropriate abatement equipment has been installed. Companies’ product types, manufacturing processes and emissions also vary widely across semiconductor fabs.

The good news is that many companies in the semiconductor manufacturing industry have successfully identified, evaluated and implemented a variety of technologies that protect the climate and improved production efficiencies. Solutions have been investigated and successfully implemented in the following key technological areas:

  • Process improvements/source reduction
  • Alternative chemicals
  • Capture and beneficial reuse
  • Destruction technologies (known as abatement)

In 2011 the industry set new targets for 2020, which it summarizes as:

  • The implementation of best practices for new semiconductor fabs. The industry expects that the implementation of best practices will result in a normalized emission rate (NER) in 2020 of 0.22 kgCO2e/cm2, which is a 30 percent NER reduction from the 2010 aggregated baseline.
  • The addition of “Rest of World” fabs (fabs located outside the World Semiconductor Council (WSC) regions that are operated by a company from a WSC association) in reporting of emissions and the implementation of best practices for new fabs.
  • NER based measurement in kilograms of carbon equivalents per area of silicon wafers processed (kgCO2e/cm2), which will be the single WSC goal at the global level.

“We’re finding as we get down to the lower levels and different things come up as the highest priority in the fab where we’re moving into more and more lower usage processes, which are requiring abatement now in order to get those levels down to meet the targets of 2020 in the industry,” Wilson explained.

The main area for potential improvement now is etch, especially in older 200mm fabs where etch processes may not have been fitted with PFC abatement devices. This is particularly true for etch processes making extensive use of CF4. “The area where we still have the most gaps is clearly etch,” Wilson said. In CVD processes, most of the benefit was done by material shifts rather than actual abatement, although we clearly do need to abate the other gases in those processes. For the etch side, there are still quite a few customers that really only do the toxic emission abatement rather than the global warming gas emission abatement. But we do see, across almost all of our customer base, people have either fairly recently moved to fully abating all the PFC type gases or will be shortly.”

Wilson said some other gases have been coming up more recently in terms of things like N2O, which people are putting more focus on now as it’s becoming a larger part of the fab footprint of global warming materials.

For PFC abatement, Edwards offers the Atlas range of products, which destroys PFCs by burning them. This is followed by a wet scrub of the byproducts. This works quite well, but Wilson cautions that in can be tricky for some processes, such as chamber cleans with NF3. “If the burn is not correct and you get too hot, there’s actually the potential to create PFC’s. And so, it is quite critical to have well-controlled burn technology to make sure that you don’t actually cause issues where we didn’t have them before.”

Wilson said another area where they have seen some issues with PFCs being created is with processing of carbon-doped materials, such as low-k dielectrics. “When they do the chamber clean, they’re cleaning off predominately silicon dioxide but there’s carbon in there so that can create PFCs and CF4 as well so there’s a requirement to look at abatement in those areas,” she said.

Another piece of good news is that no company in the supply chain is waiting for legislation to be enacted before they act themselves. “Right from consumers to the consumer manufacturers, the car manufacturers, consumer electric manufacturers, our direct customers, the equipment manufacturers plus the major players within semiconductor and flat panel display, it seems that at every level there’s a commitment that this is the right thing to do,” Wilson said. “At every level people are pushing to get the requirements more stringent and it’s almost not about legislation anymore, it’s about everybody actually thinks it’s a good idea and they want to do it.”

Across all process areas in the fab effective abatement technologies reduce the GHG emissions significantly. The reductions per process area are shown in the diagram.

Across all process areas in the fab effective abatement technologies reduce the GHG emissions significantly. The reductions per process area are shown in the diagram.

By Lynnette Reese

On Wednesday, Intel Corporation’s Katherine Winter, Vice President of the Automated Driving Group, delivered a keynote that many would think is off-topic from the usual at SemiCon West: ”Big Data in Autonomous Driving.” She revealed that autonomous driving will shift the semiconductor industries’ focus to processing terra flops of data at blinding speeds with low latency. Winter stated, “A lot of the testing that’s going on today is to find what is the right level of MIPS to have the safest possible drive.” Winter addressed the need for computing power by the semiconductor industry to meet the challenges that autonomous driving for the passenger economy will pose. Intel, in working with Strategy Analytics, finds that the Passenger Economy may be worth $7 trillion by 2050. The largest factor holding this new business space back may very well be consumer acceptance.

The burden on semiconductor processors and supporting ICs will be driven part by data. Massive amounts of data will be driven by multiple sensors, “so that you, if you are riding in it, you trust that the vehicle knows what it’s doing…you want to know that it can handle snow and ice.” The sensors complement each other. “As we go through more and more testing, and there’s more of those vehicles out there, we are learning about the combinations, how much redundancy, things like that, that you actually need in the vehicle.” Emerging pedestrians, variable weather conditions, and myriad navigation issues from differing state regulations to undocumented construction and potholes also contribute to the need for data from differing variables aimed at every possibility.

Such enormous amounts of data come not only as technical data from sensors on the car and from infrastructure, but from crowd-sourced data as well as personal data for drivers and passengers. Crowd-sourced data might include reporting new obstacles or construction to be incorporated into the AV’s navigating knowledge. The autonomous learning cycle continues as cars upload data to the cloud, which shares and uses the data to train other vehicles on the new information. Personal data gathered from within the car includes information about the passengers which will be critical to the new passenger economy as AVs become the foundation for new markets for services formed for passengers within the vehicle. New applications like robo-taxis, managing fleets of delivery trucks, and crowd-sourcing data for navigation and finding parking are within reach.

Challenges translate to the semiconductor industry as we try and solve associated problems. How do we store and share the data? What do we do with the data, and what data is saved? Areas of focus in this developing economy will be the speed of critical information and processing workload. Security is also a critical part of the AV vision. Both privacy and overall resistance to cyberattacks are of genuine concern. “How do we keep it secure? How do we make sure that there’s not a way for cyberattacks once those vehicles are out there?” posed Winter. In short, how do we trust autonomous vehicles in every way?

As we get to thousands and millions of autonomous vehicles, we will also need to understand how many we want to manage at one time. At scale, we can share safety data, create standards, and even promote an industry platform. Winter acknowledged that the semiconductor industry is not new to challenges, but indicated that the landscape will change, “We think we know what the sensors are, we think we know that kind of data is generated, but we can’t imagine what we are going to know in two years based on the speed of acceleration that we have seen so far developing in this space.”

The “Passenger Economy,” a term coined by Intel CEO Brian Krzanich, is estimated at $7 trillion by 2050. (Source: Strategy Analytics).

The “Passenger Economy,” a term coined by Intel CEO Brian Krzanich, is estimated at $7 trillion by 2050. (Source: Strategy Analytics).

8:30 am –12:30 pm
Get Smart: SEMI/Gartner, Bulls & Bears Industry Outlook
Yerba Buena Theater

10:30 am – 12:30 pm
SMART Automotive
Meet the Expert Theater, Moscone West

10:30 am – 12:30 pm
The Economics of Choosing a Lithography Strategy
Moscone West, TechXPOT West

10:30 am –12:35 pm
5G Communications and the Next-generation Cloud
Moscone North, TechXPOT North

2:00 pm – 4:00 pm
The Economics of Density Scaling
Moscone West, TechXPOT West

2:00 pm – 4:00 pm
Exploring Electronics Requirements & Solutions for Medical Technology
Moscone North, TechXPOT North