Category Archives: Wafer Level Packaging

BY JOHN HUNT, Senior Director, Engineering, Product Promotion, ASE Group, Tempe, AZ

When most people in packaging hear the term “Fan Out,” they usually think of the eWLB type of “chips first” fan out process/structure. This was the first of the embedded chips first structures to be taken into volume production by Infineon and ASE in Q1 2009. But this was not the end of the story. Today we speak of a chip first process and a chip last process building almost the same fan out structure.

Chips first fan out process describes a process where the singulated die are held in some form of matrix, followed by overmolding and the formation of the redistribution trace structure in situ on the surface of the die/matrix formation.

In contrast, chips last fan out process describes a process where the redistribution trace structure is formed first, sometimes on some type of temporary carrier, and then the singulated die are bonded using a flip chip assembly process onto this trace pattern, followed by overmolding of the package.

To the end user, it is the fan out package structure for the devices – active and passive – and the performance, cost and robustness of that package that really matters. How that fan out package structure is manufactured (i.e. processed) is of less importance. Packaging engineers are nothing but ingenious. Give them a challenge and they will find a way. For Fan Out, the good news is that there are two basic processes, Chip First and Chip Last, providing manufac- turing capacity to serve the end users.

As an example, ASE brought out a high volume chip last panel fan out solution to market in 2014 that provides a verysimilarfanoutstructuretotheeWLBfanoutstructure. And since that time, ASE has been in high volume production for several devices. In fact, one paper at ECTC 2016 describes the comparative similarity and differences of the Fan Out product for the same die built from these two different processes – chip first and chip last.

The Infineon Baseband chip was the first embedded chip first type of fan out to go into mass production and was well suited to the relatively low density, single chip requirements of that package. However, with the evolution of smart phone mobile devices, and the need for greater packaging densities, there is now a need for higher density fan out, often with multiple die, and the inclusion of passive devices within the fan out package structure. And it is this expanded appli- cation space for Fan Out – both for chip first and for chip last – that is getting the industry excited.

In January of this year, using a chip first wafer fan out solution, ASE released a high density fan out hybrid package structure with more than a thousand I/O, and multiple trace layers with very fine lines and spaces into production. It is clear that similar structures will also be built using a chip last process.

We can see that there are advantages and disadvantages in using each of these fan out process technologies, depending on the specific applications. Fan out chip last, however, has the advantage of an existing manufacturing infrastructure, with the promise of faster ramp up to high manufacturing yields. This is because the trace pattern can be inspected, and tested, and nearly known good die can be placed only on known good trace patterns. In contrast, for chip first, the die are committed by the time the trace pattern yield is deter- mined, and any bad trace patterns include the cost of these die in yield losses. Chip Last has also shown the promise of increased versatility in meeting the more complex require- ments of System in Package (SiP) applications.

We are seeing the transition of what had been a niche technology going into mainstream. The ingenuity and creativity of the packaging engineers are being tested as never before. And they have come out on top. As fan out comes of age, we shall find that there are applications and uses for more than one variation of structure and more than one variation of process. In the end, the market will help us to decide the most manufacturable and lowest cost solutions for each of the many different applications.

Driven by a strong semiconductor market outlook and aggressive investment in advanced packaging capability fueled by strong government support, advanced packaging revenue in China is expected to reach US$ 4.6 billion in 2020, against US$ 2.2 billion in 2015, announces Yole Développement (Yole). This market is showing an impressive 16% CAGR during this period. China has the world’s largest population, and its economy will continue to grow at a high pace: the economists predict a 6% growth, reaching around US$16 trillion by 2020. Also, an increase in per capita income (more purchasing power) will ensure China remains a dominant market in the coming years. Today, no business can afford to ignore China.

advpackaging_china_waferforecastyole_june2016_373x280

Under this context, the “More than Moore” market research and strategy consulting company, Yole explores the advanced packaging industry in China and details, in its latest advanced packaging report entitled “Status & Prospects for the Advanced Packaging Industry in China”, the status of this industry, its market drivers and key market data and technology trends. Yole’s analysts propose a clear vision of the Chinese government commitment within the advanced packaging industry in China and point out the huge China’s IC investments fund. Business opportunities, technical challenges and more are also part of Yole’s market & technology analysis.

China commands a significant market for key electronic products. In fact, over half of all key electronic products are consumed in China. In 2014, the Chinese smartphone, LCD, notebook/tablet, and wearable markets were around 81%, 63%, 71%, and 47% of the global market, respectively. The global IC market will grow by a CAGR of 4% from 2014 – 2020, while the Chinese IC market will grow by 7% over the same period. According to Yole, the Chinese IC market is expected to reach about US$149 billion by 2020, around 40% of the total IC market.

“There is a huge gap between China’s IC consumption and its manufacturing,” commented Santosh Kumar, Senior Technology & Market Analyst at Yole. And he details: “In 2015, China produced only 12.5% roughly of the IC it consumes, and the gap between IC consumption and production is about US$91 billion. Currently, IC is China’s #1 import commodity, exceeding oil.”

China considers the IC industry to be a key strategic sector. The Chinese government is making a significant effort through funding and a national IC policy, with an aggressive growth strategy to make China an IC design and manufacturing hub. The goal by 2030 is to become the global leader in all primary IC industrial supply chain segments.

The Chinese government has employed a multi-pronged strategy to support domestic IC industry development in order to achieve the goal of becoming the global leader in all primary IC industrial supply chain segments by 2030. Over the last few decades the Chinese government has supported the domestic IC industry, but with limited success. One key reason for failure was the bureaucratic approach to resource allocation, which was by nature inefficient. This time around, the government is adopting a market-based approach where funding is available for investment in the form of equity investments rather than subsidies in invested companies. The goal is to generate return on investment while simultaneously aligning with government policy.

Out of more than 200 firms, there are 128 companies having significant advanced packaging & assembly (A&P) operations in China. Yole’s analysts identified around 147 plants all over China, mostly based in Jiangsu (43), Guangdong (30) and Shanghai (22) regions. In this part of the globe, more than 50% of A&P plants belongs to IDMs . A number of Taiwan-HQ OSAT plants are concentrated in Jiangsu, especially in the Suzhou Industry Park. Indeed global OSATs such as Amkor Technology and SPIL are investing in advanced packaging capability of their own Chinese operations: China (Shanghai) operation is the Amkor’s second-largest factory by revenue. The advanced packaging market growth is led by JCET/STATSChipPAC, Huatian, NFME & China WLCSP. And the Chinese advanced packaging market is offering a wide range of platforms including:

  •  Flip-chip technology is the largest advanced packaging market segment in China reaching US$ 1,8 billion in 2015. The Flip-chip market is covering bumping and assembly steps. “We see a huge ramping of bumping capacity in China, especially by Chinese players with 12” Cu pillar process,” comments Santosh Kumar from Yole. “This growth is mainly supported by the Flip-chip industry in China showing a 16% CAGR between 2015 and 2020”. Flip-chip platform is followed by WLCSP technology with US$ 343 million in 2015 as well.
•  Fan-out and 2.5/3D platforms are only emerging in China and will have less than 1% market share by 2020.

Under its latest advanced packaging report, Yole’s advanced packaging team points out the key market drivers of this industry. They list:
•  Long-term growth in China IC industry
•  Aggressive mergers & acquisitions
•  Numerous Chinese government initiatives
•  Investments led by global OSATs
This analysis also gives an overview of China’s semiconductor ecosystem and discusses in detail the country’s advanced packaging market.

Today, SEMI announced that the latest packaging solutions will be the topic of an in-depth session at the SEMICON West 2016 Advanced Packaging Forum – and on display on the exhibition floor. Rapidly changing technologies and accelerated product life cycles are driving the need for new assembly and packaging solutions suited for next-generation products such as Internet of Things (IoT) devices and wearables. To meet these packaging needs, semiconductor technologies with smaller form factors, lower power consumption, and flexible designs are increasingly in demand.

Advanced Packaging Forum 

Six complimentary packaging sessions are offered at the Advanced Packaging Forum at SEMICON West’s TechXPOT North stage. Pre-registration is required. Sessions explore what’s ahead in the world of packaging and assembly. The three-day forum will explore the challenges posed by new and emerging devices and offer solutions capable of enabling them. Technical sessions include:

  • SiP Next 1: Processor – Memory/Analog Integration
  • SiP Next 2:  IoT & Smart Things – SiP Integration
  • Sensing the Future: Enabling Applications for a Smarter World
  • Packaging Developments for Flexible, Hybrid Electronics
  • Packaging Power: Enabling a Variety of Applications and Efficiency
  • Packaging Photonics for Speed & Bandwidth

Sessions feature speakers from Cisco, Mentor Graphics, Texas Instruments, and more.  Attendees will learn about the latest in electronic packaging, thermal management, additive manufacturing, simulation, and reliability assessment; system optimization and differentiation through heterogeneous integration and SiP; sensor technologies for monitoring and analyzing complex data streams; and other advanced developments.

Packaging and Assembly Equipment Exhibitors

This year’s SEMICON West exposition also features packaging solutions on the show floor. Attendees can view more than sixty new products from some 200 exhibitors.

The industry is seeing dramatic changes and SEMICON West 2016 has expanded its technical programming by nearly 50 percent to help attendees get a clear view of the road ahead. To learn more about SEMICON West 2016’s eight new forums (Extended Supply Chain, Advanced Manufacturing, Advanced Packaging, Test, Silicon Innovation, Flexible Hybrid Electronics, and World of IoT), visit www.semiconwest.org.

The Semiconductor Industry Association (SIA) this week announced worldwide sales of semiconductors reached $25.8 billion for the month of April 2016, a decrease of 1.0 percent from last month’s total of $26.1 billion and 6.2 percent lower than the April 2015 total of $27.6 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, a new WSTS industry forecast projects decreased annual semiconductor sales in 2016, followed by slight market growth in 2017 and 2018.

“Global semiconductor sales decreased marginally in April, continuing a recent trend of market sluggishness driven by soft demand and a range of macroeconomic headwinds,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Despite a cumulative decrease across all product categories, year-to-year sales of microprocessors and analog products increased modestly, perhaps foreshadowing stronger sales ahead. The latest industry forecast suggests global sales may indeed rebound somewhat in the second half of 2016, but still fall short of last year’s total. The global market is projected to grow slightly in 2017 and 2018.”

Regionally, year-to-year sales increased in Japan (2.2 percent) and China (0.3 percent), but decreased in Asia Pacific/All Other (-8.2 percent), Europe (-8.6 percent), and the Americas (-14.8 percent). Compared with last month, sales were up slightly Japan(0.2 percent) and Asia Pacific/All Other (0.1 percent), but down in Europe (-0.8 percent), China (-1.8 percent), and the Americas (-2.2 percent).

Additionally, SIA today endorsed the WSTS Spring 2016 global semiconductor sales forecast, which projects the industry’s worldwide sales will be $327.2 billion in 2016, a 2.4 percent decrease from the 2015 sales total. WSTS projects year-to-year decreases across all regional markets for 2016: Europe (-0.1 percent), Asia Pacific (-1.2 percent), Japan (-1.7 percent), and the Americas (-7.3 percent). On the positive side, WSTS predicts growth in 2016 for several semiconductor product categories, including discretes, analog, and MCU products.

Beyond 2016, the semiconductor market is expected to grow at a modest pace across all regions. WSTS forecasts 2.0 percent growth globally for 2017 ($333.7 billion in total sales) and 2.2 percent growth for 2018 ($340.9 billion). WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

April 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

4.89

4.78

-2.2%

Europe

2.66

2.64

-0.8%

Japan

2.59

2.60

0.2%

China

7.93

7.79

-1.8%

Asia Pacific/All Other

8.02

8.03

0.1%

Total

26.09

25.84

-1.0%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.61

4.78

-14.8%

Europe

2.89

2.64

-8.6%

Japan

2.54

2.60

2.2%

China

7.77

7.79

0.3%

Asia Pacific/All Other

8.74

8.03

-8.2%

Total

27.56

25.84

-6.2%

Three-Month-Moving Average Sales

Market

Nov/Dec/Jan

Feb/Mar/Apr

% Change

Americas

5.41

4.78

-11.7%

Europe

2.70

2.64

-2.4%

Japan

2.49

2.60

4.3%

China

8.42

7.79

-7.4%

Asia Pacific/All Other

7.87

8.03

2.0%

Total

26.89

25.84

-3.9%

Media Contact 

Today, SEMI announced that 19 new fabs and lines are forecasted to begin construction in 2016 and 2017, according to the latest update of the SEMI World Fab Forecast report. While semiconductor fab equipment spending is off to a slow start in 2016, it is expected to gain momentum through the end of the year. For 2016, 1.5 percent growth over 2015 is expected while 13 percent growth is forecast in 2017.

Fab equipment spending ─ including new, secondary, and in-house ─ was down 2 percent in 2015. However, activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to US$36 billion in 2016, 1.5 percent over 2015, and to $40.7 billion in 2017, up 13 percent. Equipment will be purchased for existing fabs, lines that are being converted to leading-edge technology, as well as equipment going into new fabs and lines that began construction in the prior year.

Table 1 shows the regions where new fabs and lines are expected to be built in 2016 and 2017. These projects have a probability of 60 percent or higher, according to SEMI’s data. While some projects are already underway, others may be subject to delays or pushed into the following year. The SEMI World Fab Forecast report, published May 31, 2016, provides more details about the construction boom.

new fab lines

Breaking down the 19 projects by wafer size, 12 of the fabs and lines are for 300mm (12-inch), four for 200mm, and three LED fabs (150mm, 100mm, and 50mm). Not including LEDs, the potential installed capacity of all these fabs and lines is estimated at almost 210,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2016 and 330,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2017.

In addition to announced and planned new fabs and lines, SEMI’s World Fab Forecast provides information about existing fabs and lines with associated construction spending, e.g. when a cleanroom is converted to a larger wafer size or a different product type.

In addition, the transition to leading-edge technologies (as we can see in planar technologies, but also in 3D technologies) creates a reduction in installed capacity within an existing fab. To compensate for this reduction, more conversions of older fabs may take place, but also additional new fabs and lines may begin construction.

For insight into semiconductor manufacturing in 2016 and 2017 with details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,100 facilities including over 60 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.

By Dr. Phil Garrou, Contributing Editor

Dongkai ShangguanDr. Dongkai Shangguan is currently the Chief Marketing Officer of STATS ChipPAC. Previously, Dongkai served as the founding CEO of the National Center for Advanced Packaging Co., Ltd. (“NCAP China”), worked for 10 years at Ford Motor Company in various technical and management functions, and for 11 years at Flextronics as Corporate Vice President of Global Advanced Technology.

SST: In 2015, STATS ChipPAC was acquired by JCET (Jiangsu Changjiang Electronics Technology Co., Ltd.) and organized as a business unit. Can you describe some of the personnel changes that have taken place?

DS: Following the acquisition, STATS ChipPAC became a business unit under the JCET Group with the same organizational structure as what we had prior to the completion of the deal. Dr. Han Byung Joon (BJ) was appointed to be Co-President and Chief Executive Officer with Tan Lay Koon. Dr. Han had served as our Chief Technology Officer since 1999. He and Lay Koon had worked very closely over the years and together led the company through the first three months following the acquisition. After the initial transition period, Dr. Han became the President and CEO for the company. Reporting directly to JCET Group Chairman Wang XinChao, Dr. Han has full responsibility for the business results of STATS ChipPAC. He also serves as Chairman of the Technology Strategy Council for the JCET Group.

In August of last year, there were two additional executive appointments. Woo Kwek Kiong (KK) was appointed Senior Vice President and Chief Financial Officer for the Company. Prior to joining us, KK was Chief Financial Officer at Advanpack Solutions Pte Ltd and ASTI Holdings Limited. Il Kwon (IK) Shim was promoted to Senior Vice President and Chief Technology Officer. IK has been with STATS ChipPAC since 2000 and prior to his promotion served as Head of Research and Development.

In December, Cindy Palar was appointed as Managing Director of STATS ChipPAC Singapore (SCS), where our FlexLineTM manufacturing is located. Cindy has been with the Company since 1999 and has held a number of senior management positions in Strategic Marketing, Pricing, Product Line Management and Demand/Capacity Planning.

JCET chose a light integration strategy for the acquisition in order to keep the focus on our customers and minimize any disruptions with our service and support. The organizational structure and operating systems for STATS ChipPAC have remained the same as before the acquisition, providing a smooth transition following the deal completion. 

SST: We know that JCET is the largest semiconductor packaging and test provider in China through JCAP (Jiangyin Changdian Advanced Packaging Co., Ltd. ) a subsidiary of JCET which provides wafer bump (solder bump, gold bump, pillar bump), Wafer Level Chip Scale Packaging, assembly and test. Can you differentiate between what JCET SCP and JCET JCAP will offer the customer as divisions of JCET?

DS: JCET has extremely solid credentials in turnkey wirebond packaging, servicing a broad range of applications with very good relationship with a large number of customers, particularly in China. JCET focuses primarily on leaded wirebond and flip chip packaging including assembly of discrete packages.

JCAP provides turnkey services including wafer bump, probe and assembly. JCAP is a leader in advanced wafer bump technology (solder bump, gold bump, copper pillar bump) and Wafer Level Chip Scale Packaging (WLCSP).

STATS ChipPAC, with the strongest IP portfolio in the OSAT industry for many years, clearly brings very strong advanced packaging technologies to the JCET Group, particularly in Fan-out Wafer Level Packaging (FOWLP), laminate-based Flip Chip, package-on-package (PoP), and System-in-Package (SiP) capabilities. STATS ChipPAC will continue to be the FOWLP and SiP center of competency for the JCET Group, and all laminate based flip chip activities are being consolidated into STATS ChipPAC factories.

As a combined Group, the JCET Group is now able to address a much broader total available market (TAM). While each JCET Business Unit has its area of expertise, we are already seeing benefits of cross-selling services to our customers, particularly in China.

SST:. Will the SCP product focus change any in the coming years? Can you share any packaging roadmaps?

DS: No, the merger does not change STATS ChipPAC’s focus or roadmap at all. Our focus for the coming years continues to be on expanding our SiP and FOWLP business, in addition to our core turnkey wirebond, flip chip and PoP packaging business areas. STATS ChipPAC is firmly committed to our industry leading eWLB technology as supported by our eWLB line expansion occurring throughout this year. While we will continue to develop advanced 2.5D and 3D FOWLP package designs, we will be implementing further process optimizations, such as panel manufacturing, which will drive significantly better capital intensity and a lower unit cost for larger body sizes.

SST: Have/will SCP manufacturing facilities in Singapore moved/move to China?

DS: There is currently no plan for any relocation. Our STATS ChipPAC Singapore (SCS) facility remains the hub of the JCET Group’s effort in FOWLP as well as being our largest Test site. SCS is an important location for several Tier 1 customers who prefer having Singapore as part of their supply chain for regional diversity and other commercial reasons.

SST: What is JCET relationship to SMIC? We noticed with interest that SMIC recently increased its ownership position to 14.25% making it the single largest owner of JCET.

DS: JCET has entered into asset purchase transaction whereby it will acquire the remaining shareholding in STATS ChipPAC from the National Integrated Circuit Fund and SMIC. Concurrent to the asset purchase transaction, JCET has entered into a subscription agreement with SMIC whereby SMIC will subscribe for approximately 150 million JCET shares for a consideration of about US$400 million. After the proposed transaction, SMIC will have a 14.25% stake in JCET Group, resulting in JCET owning 100% of STATS ChipPAC. This transaction will strengthen the equity base of JCET with stronger shareholders, and create better operational synergies. These transactions have no significant impact to STATS ChipPAC’s organizational structure or management team, and will not impact our service to our customers.

SST: China’s government policy “National Guidelines for Development and Promotion of the IC Industry,” which was released in June of 2014 calls for expansion and vertical integration of the domestic semiconductor value chain with domestic sales revenue targets of $56B by 2020. How does packaging fit into these overall goals?

DS: The Chinese government correctly identifies packaging and test as critical parts of the overall semiconductor ecosystem and, therefore, packaging is an integral part of these goals. As the largest OSAT in China, the JCET Group is uniquely positioned to participate in and capitalize on the emergence and growth of the Chinese semiconductor ecosystem. With the addition of the advanced packaging technologies from STATS ChipPAC, the JCET Group is well positioned to help enable this growth.

SST: What new products or technologies would you like to share with our readers?

DS: We are very proud to have passed a significant milestone for 1B units shipped for our industry leading eWLB FOWLP product. The eWLB platform has an incredible amount of traction now and the technology roadmap around this platform is resonating with an increasingly diverse range of customers, from its traditional base in mobile communications into areas such as Advanced Driver Assistance Systems (ADAS) in automobiles and bio-processors in the wearables market. Furthermore, as a platform for system integration, enabled by finer L/S and multiple RDL’s, eWLB SiP in various configurations (such as multi-die with passives, PoP, 2.5D, etc) has a tremendous future.

SiP capabilities are incredibly important to those customers driving miniaturization as well as integration and modularization of functionality. This represents a major new source of TAM for the OSAT industry. We feel we are extremely well positioned in this area, as we have developed comprehensive capabilities, including design and simulation, advanced packaging technologies, high density SMT component placement, advanced molding for complex topographies, conformal shielding, and system level test, for a wide variety of SiPs/modules in multiple market segments. Depending on the application requirements and product complexity, we have developed various SiP configurations ranging from conventional 2D modules with multiple active and passive components, interconnected through flip chip, wire bonding, and SMT, to more complex modules such as Package-in-Package (PiP), eWLB Package-on-Package (eWLB PoP), 2.5D and 3D solutions.

We anticipate that our strength in these areas coupled with our unique position in the highest growth region, China, will propel our growth well beyond the industry average going forward.

Soitec (Euronext), a manufacturer of semiconductor materials and a high-volume supplier of silicon-on-insulator (SOI) substrates for the electronics industry, has received the award as the best quality supplier among all vendors from NXP Semiconductors, the world’s largest automotive semiconductor manufacturer. Soitec’s Power SOI substrates use to manufacture smart power IC’s for automotive applications represent a significant and strategic market for Soitec’s business, which is growing at a steady rate.

With continuous innovations in vehicle security, connectivity, infotainment and carbon emissions control as well as the emerging use of autonomous driving, the total semiconductor content per automobile is growing rapidly. According to industry analysis, automotive applications represent the fastest growing end-use IC market segment.Soitec estimates that each new car built today contains an average of 80 square millimeters of SOI and more than six billion automotive ICs have been manufactured on its Power SOI substrates to date.

NXP announced the winners of its annual Supplier Awards in Austin, Texas on May 19 at the company’s first Supplier Day following NXP’s merger with Freescale.

“We are very honored to receive NXP’s best quality award,” said Thomas Piliszczuk, senior vice president of sales and marketing at Soitec. “This award recognizes the everyday focus of Soitec on our product quality and performance in delivering the best SOI substrates to meet the most demanding industry quality standards.”

About Soitec’s Power SOI(TM) substrates: Power SOI substrates provide excellent electrical isolation and are ideal for improving reliability and integrating devices operating at different voltages – from a few volts to several hundred volts – while reducing die area. These wafers are mainly used in the automobile electronics industry in making transceivers, audio amplifiers, powertrain controls and brightness LED drivers.

As the opening day of SEMICON West (July 12-14) approaches, the electronics manufacturing industry is experiencing disruptive changes, making “business as usual” a thing of the past. To help technical and business professionals navigate this fast-changing landscape, SEMICON West programming has been upgraded extensively ─ increased from 170 hours to 250 hours this year. New brand and deep programming provide insights into the latest megatrends and helps attendees identify new opportunities and refine sound strategic plans.

At this year’s expo, several new forums designed to enhance collaboration within shared communities of interest will debut. Lead by technical experts, top analysts, and leaders from some of the biggest names in electronics, the new forums are generating significant advance interest and buzz, key among them:

  • Advanced Manufacturing Forum: Twelve cutting-edge sessions — from What’s Next in MEMS and Sensors to Power Electronics and 3D Printing — will be presented by Samsung, Applied Materials, Texas Instruments, and more. Attendees will learn about new technologies on the horizon and how they impact semiconductor manufacturing.
  • Flexible Hybrid Electronics Forum: Flexible Hybrid Electronics is driving new processes and packages, providing innovative approaches for health-monitoring, wearables, soft robotics, and other next-generation products. Attendees will get details on thinned device processing, system design, reliability testing and modeling from experts at Qualcomm, PARC, and GE Global Research.
  • World of IoT Forum: Forecasters predict that IoT will soon become a $6 trillion market. The World of IoT Forum brings together leading suppliers, integrators, and solution providers at the forefront of innovations in mobility, network-connected devices, and automotive and healthcare applications, among others. Attendees will learn about the trends impacting the market, including big data and analytics, smart things, and MEMS and sensor manufacturing.

With so many disruptive trends driving the market, it is critical for industry professionals to have a clear view of the road ahead. With its vastly expanded technical and business programming, this year’s expo will deliver the strategic insights needed to survive and thrive. To learn more and to register, visit SEMICON West Forums.

North America-based manufacturers of semiconductor equipment posted $1.59 billion in orders worldwide in April 2016 (three-month average basis) and a book-to-bill ratio of 1.10, according to the April Equipment Market Data Subscription (EMDS) Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in April 2016 was $1.59 billion. The bookings figure is 15.6 percent higher than the final March 2016 level of $1.38 billion, and is 1.3 percent higher than the April 2015 order level of $1.57 billion.

The three-month average of worldwide billings in April 2016 was $1.46 billion. The billings figure is 21.5 percent higher than the final March 2016 level of $1.20 billion, and is 4.0 percent lower than the April 2015 billings level of $1.52 billion.

“Bookings reached their highest levels in eight months and billings levels also significantly improved in April,” said Denny McGuirk, president and CEO of SEMI. “The data reflect strong investments in 3D NAND and in China.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

  Billings
(3-mo. avg)		 Bookings
(3-mo. avg)		 Book-to-Bill
November 2015 $1,288.3 $1,236.6 0.96
December 2015 $1,349.9

 

 $1,343.5 1.00
January 2016 $1,221.2 $1,310.9 1.07
February 2016 $1,204.4 $1,262.0 1.05
March 2016 (final) $1,197.6 $1,379.2 1.15
April 2016 (prelim) $1,455.0 $1,594.6 1.10

Source: SEMI (www.semi.org), May 2016