TSV-based 3D power distribution

Researchers from IBM and Rensselaer Polytechnic Institute will report on a partition and assembly approach that combines both the electromagnetic (EM) and analytical simulations to accurately model and analyze several TSV-based 3D power delivery networks, which are composed of stacked-chips, interposer, and package substrate. With this method, they for the first time consider RLC couplings between multiple voltage supply rails in 3D systems. The quantitatively examined power performances, they say, unveil 3D power delivery design implications to fulfill 3D integration benefits. (#30.6: "Hybrid Modeling and Analysis of Different Through-Silicon-Via (TSV)-Based 3D Power Distribution Networks")

Two of the 3D power network architectures (not in scale) used in this work.

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Simulation for integrated MEMS

Scientists from Japan (U. of Tokyo, NTT Advanced Technology, Tokyo Institute) have developed "a handy simulation tool" for integrated microelectromechanical systems (MEMS) on a spice-based circuit simulator (LTspice). As long as one has analytical models for electromechanical components such as electrostatic parallel-plate actuator, viscoelastic spring, and mechanical anchor, "any multiphysics model for MEMS can be interpreted by using behavioral current or voltage sources. Simulation capability was extended to and tested against an electrostatic digital torsion mirror device integrated with CMOS level shifter circuits. (#6.3: A Multi-Physics Simulation Technique for Integrated MEMS" [Invited])

Schematic model of MEMS electrostatic digital torsion mirror array integrated with a high-voltage driver circuit. The mirror deflects downward when the drive voltage is supplied. High-voltage (>20V) level shifter is used to drive the mirror at fast speed and to a relatively large angle.

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Sub-40nm 3D NAND

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at IEDM. They used vertical gates having horizontal channels to create a new architectural layout that dramatically decreases feature sizes in the wordline direction, and improves manufacturability. The new architecture also enables the use of a novel "staircase" bitline contact formation method to minimize fabrication steps and cost. The result is an eight-layer device with a wordline feature size of 37.5nm, bitline feature size of 75nm, 64 cells per string, and a core array efficiency of 63%. The technology not only is lower-cost than conventional sub-20nm 2D NAND, it can provide 1 Tb of memory if further scaled to 25nm feature sizes, according to the researchers. At that size this device would comprise only 32 layers, compared to 3D stackable NANDs with vertical channels that would need almost 100 layers to reach the same memory density. (#2.3: "Highly Scalable 8-Layer Vertical-Gate 3D NAND With Split-Page Bit Line Layout and Efficient Binary-Sum MiLC (Minimal Incremental Layer Cost) Staircase Contacts")

An overview of the proposed architectural layout — twisted even/odd bitline (split-page) VG architecture — that is said to be an improvement on previously proposed 3D vertical gate NAND architecture. The even/odd island gate SSL devices can be laid out in double pitch, providing much larger process window for BL pitch scaling.

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Hybrid-channel ETSOI CMOS

CMOS technology uses the two types of MOSFET transistors (N and P) working together in a complementary fashion: when one is on, the other is off. However, the conflicting materials and design requirements for N- and P-type devices make achieving balanced performance and desired threshold voltage challenging. Meanwhile, extremely thin SOI (ETSOI) technology is a viable device architecture for continued CMOS scaling to 22nm and beyond, offering superior short-channel control and low device variability with undoped channels.

At IEDM, a team led by IBM will report on the world’s first high-performance hybrid-channel ETSOI CMOS device. They integrated a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm geometries. A novel STI-last (isolation-last) process makes the hybrid architecture possible. The researchers built a ring oscillator circuit to benchmark performance, and the hybrid planar devices enabled the fastest ring oscillator ever reported, with a delay of only 11.2ps/stage at 0.7V, even better than FinFETs. (#18.1: "High-Performance Extremely Thin SOI (ETSOI) Hybrid CMOS with Si Channel NFET and Strained SiGe Channel PFET")

A wrap FG cell (left) and a planar FG cell (right).

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Goodbye graphene, hello MoS2

Graphene, a one-atom-thick sheet of carbon atoms, is seen as a potential replacement for silicon in future transistors thanks to its exceptional set of properties (high current density, mobility, and saturation velocity). However, transistors made of graphene cannot be turned off because graphene has almost no bandgap. So investigations have begun for a new 2D material, molybdenum sulfide (MoS), which has similar characteristics but offers something graphene doesn’t: a wide energy bandgap, enabling transistors and circuits to be built from it directly. At IEDM, an MIT-led team will describe the use of CVD processing to grow uniform, flexible, single-molecular layers of MoS, comprising a layer of Mo atoms sandwiched between two layers of S atoms. They exploited the material’s 1.8 eV bandgap to build MoS transistors and simple digital and analog circuits (a NAND logic gate and a 1-bit ADC converter). The transistors demonstrated record MoS mobility (>190 cm²/Vs), an ultra-high on/off current ratio of 108, record current density (~20μA/μm) and saturation, and the first GHz RF performance from MoS. The results show MoS may be suitable for mixed-signal applications and for those which require high performance and mechanical flexibility. (#4.6: "Large-Scale 2D Electronics Based on Single-layer MoS2 Grown by Chemical Vapor Deposition")

A schematic of the CVD process for growing single-layer MoS.

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Hybrid floating gate nonvolatile memory

imec will describe — for the first time — a demonstration of ultra-thin hybrid floating gate (HFG) planar NVM cell performance and reliability. Results not only confirm the high potential of the HFG thickness scaling down to 4nm with improved performance, but also show excellent post cycling data retention and P/E cycling endurance. The optimized ultra-thin HFG planar cells show potential for manufacture and scalability for high density memory application. The stack consists of an ISSG tunnel oxide, a dual layer FG (PVD polysilicon + PVD TiN), a high-k IPD (ALD Al₂O₃) and an n-type polysilicon CG. (#2.2: "Ultra Thin Hybrid Floating Gate and high-k Dielectric as IGD Enabler of Highly Scaled Planar NAND Flash Technology")

XTEM of a Ge-channel FET with SiGe source/drain.

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Flexible CMOS with SOI

Flexible circuitry promises a host of innovative biomedical, security, wearable, and other products. To date, flexible circuits have offered only limited performance because plastic substrates aren’t compatible with the high temperatures/harsh processes needed to make high-performance CMOS devices. Fabricating high-performance CMOS on silicon substrates, and then transferring the devices to plastic, has shown to be complex and expensive.

At IEDM, for the first time, a way around this will be unveiled: IBM researchers will demonstrate high-performance state-of-the-art CMOS circuits, including SRAM memory and ring oscillators, on a flexible plastic substrate. The extremely thin silicon on insulator (ETSOI) devices had a body thickness of just 60Å. IBM built them on silicon and then used a simple, low-cost room-temperature process called "controlled spalling," which essentially flakes off the Si substrate. Then they transferred them to flexible plastic tape. (#5.1: "Advanced Flexible CMOS Integrated Circuits on Plastic Enabled by Controlled Spalling Technology")

XTEM of a Ge-channel FET with SiGe source/drain.

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Stressed-out 14nm FinFETs with SiGe channels

In a jointly authored paper, researchers from imec, GlobalFoundries and Samsung provide calculations of stress enhanced mobilities for n- and p-FinFETs with both Si and Ge channels for the 14nm node and beyond. Results indicate that both for nFETs and pFETs, Ge is "very interesting," provided the correct stressors are used to boost mobility. They conclude that strained channels grown on a strain relaxed buffer is effective for 14nm nodes and scalable to future nodes. TCAD simulation trends are experimentally confirmed by nano-beam diffraction (NBD). (#6.5: "Stress Simulations for Optimal Mobility Group IV p- and nmOS FinFETs for the 14nm Node and Beyond")

XTEM of a Ge-channel FET with SiGe source/drain.

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