Category Archives: Wafer Level Packaging

July 10, 2012 — Imec Technology Forum (ITF) took place just before SEMICON West 2012 opened in San Francisco, CA. ITF, held at the Marriott Marquis, focused on advanced semiconductor architectures and process technologies, with an additional impetus placed on the healthcare/medical industry.

Luc Van den hove, president and CEO, imec, spoke with Solid State Technology’s digital media editor, Meredith Courtemanche, covering imec’s major announcements and research presentations to take place during SEMICON West 2012. Summaries of imec’s presentations follow the video.

 

 

Logic

To enhance the advanced metal-high-k gate stack for next-generation logic devices, imec successfully demonstrated higher-k dielectric with Replacement Metal Gate (Metal-Gate-Last) transistors that achieved 200-1000x reduction in gate leakage relative to leading-edge logic devices in the industry with HfO2 high-k gate dielectric. To address the process control and scalability of the replacement metal gate for nano-scale devices, imec achieved tight electrical distribution down to 20nm gate length through detailed process optimizations. By providing fundamental insights into work-function influences due to metal intermixing in aggressively-scaled metal gates, imec’s research addresses an important source of variability in advanced transistors.

Imec has also invested significant effort in the development of 3D FinFET devices and high-k metal gate over the last 10 years.  In the 14nm platform, these features will be combined with the next generation of stress engineering. For the next node — 10nm — we will replace the silicon channel in the FinFET devices with high-mobility materials. And for the nodes beyond 10nm, we are evaluating two possible device routes: tunnelFETs and junction-less nanowires.

 

Memory

In NAND Flash memory, imec further develops hybrid floating gate architecture, scaling this architecture to 15nm and beyond. Beyond 10nm, the main emerging technology is resistive RAM (RRAM). We’ve made significant progress on RRAM: imec recently announced 10nm functional RRAM, made significant improvements in performance and reliability of RRAM cells by process improvements and clever stack-engineering, and increased fundamental understanding of RRAM process technology. 

In DRAM memory, imec is helping to scale MIMcap technology with a focus on materials. Beyond MIMcap, SST-MRAM is the leading candidate on the industry’s emerging DRAM roadmaps. Therefore, in November 2011, imec launched a program on SST-MRAM, for stand-alone DRAM as well as replacement of embedded SRAM.

 

Advanced lithography

To enable further scaling, imec is focusing on the extreme ultraviolet (EUV) lithography pre-production readiness and on extending immersion lithography using advanced patterning integration schemes. To further push the limits of 193nm immersion lithography and overcome some of the critical concerns for EUV lithography, imec implemented 300mm fab-compatible Directed Self-Assembly (DSA) process line all-under-one-roof in imec’s 300mm cleanroom fab. Imec’s DSA collaboration aims to address the critical hurdles to take DSA from the academic lab-scale environment into high-volume manufacturing.

 

Interconnects

The focus of imec’s nano-interconnect program is technology scaling including materials, process, integration, reliability and system aspects.

Imec is investigating half pitch (hp) multiple patterning techniques in combination with immersion lithography, and EUV lithography with single or double patterning techniques.

To improve the mechanical stability and low-damage patterning and integration schemes to reduce the k value, imec studies post-deposition techniques and the impact on performance and reliability.

To avoid wire resistance increase, imec explores metallization using new barrier and seed materials as well as novel deposition and filling techniques such as manganese and ruthenium based metallization, atomic layer deposition and chemical vapor deposition techniques.

 

3D integration

3D integration enables system scaling through 3D chip stacking with through-silicon-vias. Imec’s 3D integration processes are completely executed on 300mm. All processes and flows are tested on functional circuit demonstration vehicles. As part of the INSITE program, imec proposes flows for modeling, simulation, design and testing of 3D systems.

 

14nm, FinFETs

Imec’s early-version PDK (process development kit) for 14nm logic chips is the industry’s first to address the 14nm technology node. It targets the introduction of a number of new key technologies, such as FinFET technology and EUV lithography. With this PDK release, imec leads the way to an industry-standard 14nm PDK. In addition, the PDK anticipates the introduction of a number of new technologies at the 14nm node. The main example is the use of FinFET transistors, which have a larger drive per unit footprint and higher performance at low supply voltages compared to the traditional planar technologies. Evolutions of this PDK will gradually also introduce the use of high-mobility channel materials. The PDK includes elements of both immersion- and EUV lithography, opening the way for a gradual transition from 193nm immersion to EUV lithography.

 

Optical I/O

Future systems will become increasingly dependent on a high input/output bandwidth. Not only between systems, but also between the chips in a system, or even between the cores on a chip.

With optical components, it is possible to build interconnects that have the required bandwidth without consuming more power. Silicon photonics allows fabricating optical components with state-of-the-art semiconductor equipment, using the same processes and tools as for the fabrication of state-of-the-art chips.

At Semicon West, imec will announce the first important results of its industrial affiliation program (IIAP) on high-bandwidth optical input/output. This program is working towards a manufacturable solution for achieving high-bandwidth communication by modeling and engineering optical solutions for high-bandwidth communication between CMOS chips.

Check out Solid State Technology’s coverage of SEMICON West 2012!

July 10, 2012 — ULIS, a manufacturer of high-quality infrared (IR) imaging sensors, marked its 10-year anniversary with a EUR20 million investment in a new state-of-the-art facility to meet increasing market demands for IR technology.

The IR sensor facility will boost ULIS

July 9, 2012 – PRNewswire — Ultratech Inc. (Nasdaq:UTEK), a leading supplier of lithography and laser-processing systems used to manufacture semiconductor devices and LEDs, formed ‘exclusive supplier’ and ‘preferred tool vendor’ agreements with several top-tier advanced packaging companies around the world.  Combined, these companies account for almost 60% of the electroplated flip chip market that Ultratech addresses.

Also read: Challenges in Flip Chip Assembly

These agreements, along with the recent acquisition of over 200 U.S. and foreign advanced packaging patents, strategically position Ultratech to meet the lithography packaging requirements for the future device nodes of its global customer base.  They additionally underscore Ultratech’s ongoing commitment to provide its customers with leading-edge technology solutions and low cost-of-ownership advantages.

Ultratech Vice President, Advanced Packaging Technology/Nanotechnology Markets Manish Ranjan explained, "Ultratech has maintained its leading position in AP for almost 10 years.  Several of our customers have signed multi-year agreements that range from ‘exclusive supplier’ to ‘preferred tool vendor’ because they understand the technical and economic advantages our tools deliver for advanced volume manufacturing.  These agreements highlight the close working relationship that Ultratech has with its strategic customers.  These long-term relationships provide valuable insight for the development of market-specific features that enable our customers’ next-generation devices.  Building on the recent acquisition of AP patents and the multi-year vendor agreements, Ultratech will continue to work to develop lithography systems that meet its customers’ leading-edge, advanced packaging needs."

The AP300 300-mm lithography system is built on Ultratech’s customizable Unity Platform

July 9, 2012 — STATS ChipPAC Ltd. (SGX-ST:STATSChP), a leading semiconductor test and advanced packaging service provider, brought its fcCuBE advanced flip chip semiconductor packaging technology with copper column bumps, bond-on-lead (BOL) interconnection, and enhanced assembly processes into high-volume manufacturing (HVM) for multiple customers. STATS ChipPAC expanded its assembly processing capabilities to address a wider spectrum of bump pitch ranges from >200

July 2, 2012 – BUSINESS WIRE — Tessera Technologies Inc. (NASDAQ:TSRA) has received notice from Powertech Technology Inc. (PTI) that it will terminate its license agreement with the semiconductor packaging and optics technology company. Tessera also completed phase 1 of its acquisition of camera module technologies from Flextronics.

Tessera Inc., a wholly-owned subsidiary of Tessera Technologies Inc., received a letter from Powertech Technology Inc. (PTI) that purports to terminate its license agreement with Tessera Inc. PTI stated that on July 30, 2012, it will make a payment to Tessera Inc. in protest under the license agreement for the quarter ended June 30, 2012.

PTI filed a complaint against Tessera, Inc. in December of 2011, seeking a declaratory judgment that PTI had the right to terminate its license agreement due to a breach of contract by Tessera, Inc.

June 29, 2012 – BUSINESS WIRE — Semiconductor fab tool supplier Ultratech Inc. (Nasdaq:UTEK) acquired the rights to a collection of patents from semiconductor leader IBM. Ultratech gained semiconductor packaging technologies including C4 bumping, ball grid array (BGA) methods, lead-free solders, and 3D packaging IP.

Representing both U.S. and foreign patents, the portfolio includes claims directed at methods of making, at compositions and at structures of semiconductor devices. This acquisition strengthens and broadens Ultratech’s offerings to facilitate advanced packaging at the lower device nodes.

Ultratech, Inc. (Nasdaq: UTEK) designs, manufactures and markets photolithography and laser processing equipment. Visit Ultratech online at: www.ultratech.com.

IBM makes semiconductors and other microelectronics. For more information on IBM, please visit:www.ibm.com

June 18, 2012 – PRWEB — Daewon Innost achieved what it says is the light-emitting diode (LED) industry’s best thermal dissipation performance on its Glaxum LED Array family of chip on board (COB) modules. The proprietary Nano-Pore Silicon Substrate (NPSS) technology developed by Daewon Innost led to thermal impedance of 0.41°C/W.

Daewon Innost’s NPSS is created by applying semiconductor lithography to silicon wafers, allowing for 50µm-pitch interconnection between gallium nitride (GaN) LED chips; conventional metal-core printed circuit boards (MCPCBs) cannot drop below 300µm pitches. The COB modules are fabricated with high-efficacy, commercially available 1W LED chips. An LED chip supplier independently tested the modules.

“Our Glaxum module runs over 12°C cooler than the previous top performing COB module,” said Sungyuk ‘Stephen’ Won, CEO of Daewon Innost, noting that generally 1°C lower operating temperature = an extra 1000 hours of lifetime.

The Glaxum NPSS modules are available in models ranging from 3.5 to 100W. The models with lowest thermal impedance are Glaxum-MCL-GL-WC-020-002 (warm white) and the Glaxum-MCL-GL-CC-020-002 (cool white). Tested voltage and current value of Glaxum module is 16.6 V, 1.2 A, respectively.

Daewon Innost was founded in 2011 as a spin-off from Daewon SPIC, a leading company in the global semiconductor packaging industry, to focus on LED lighting. Learn more at http://www.dwinnost.com.

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ECTC


June 15, 2012

June 15, 2012 — San Diego, CA, hosts the annual ECTC (Electronic Component Technology Conference) every three years. Attendance at this year