Category Archives: Wafer Level Packaging

March 23, 2012 — SEMI is seeking papers for technical sessions and presentations at the upcoming SEMICON Europa 2012, October 9-11 in Dresden, Germany. Technical presentation abstracts are due April 30.

SEMICON Europa serves the global microelectronics industry in Europe, with new products and technologies from across the microelectronics supply chain: electronic design automation, device fabrication (wafer processing), and final manufacturing (assembly, packaging, and test). SEMICON Europa also features emerging markets and technologies, including micro electro mechanical systems (MEMS), flexible electronics and displays, nano-electronics, solid state lighting (LEDs), and related technologies.

SEMICON Europa 2012 plans to host more than 100 hours of technical sessions and presentations on the design and manufacturing of semiconductors, MEMS, printed and flexible electronics, and related technologies:

• International MEMS/MST Industry Forum, 8-9 October; theme: “New Dynamics in the MEMS Industry”

• Advanced Packaging Conference (APC), 9-10 October; theme “Packaging Solutions for the New Technologies”

• 14th  European Manufacturing Test Conference (EMTC), 10-11 October; theme: “Overcoming New Test Challenges through Cooperation and Innovation”
 
Submit a 200-400 word abstract of original, non-commercial and non-published material to [email protected], indicating in the subject line of the e-mail: “TEST Call for Papers,”  “MEMS Call for Papers” or “Advances Packaging Call for Papers.” The deadline for submitting abstracts is April 30, 2012. Abstracts must clearly detail the nature, scope, content, organization, key points and significance of the proposed presentation.  The abstract should also contain the main author contact details like job title, company, address, telephone and e-mail, with a short biography.

For more information about the conference or submitting abstracts, including guidelines and requirements, visit http://www.semiconeuropa.org/ProgramsandEvents/CallforPapers, or contact Carlos Lee, SEMI Europe, Tel. +32 2 6095334. SEMI is a global industry association serving the nano- and microelectronic manufacturing supply chains.

March 21, 2012 – Reuters — Taiwan raised investment ceilings for Chinese investors in liquid crystal displays (LCDs), semiconductors, IC assembly and test, microelectronics production equipment, and metal tool manufacturing.

Mainland China companies still cannot hold controlling stakes in these companies in Taiwan, or appointing managers, the government said. But they can hold more than 10% stakes in local companies. All investments must be approved by Taiwan regulators.

This revision also covers makers of light-emitting diodes (LEDs) and solar cells, opened to Chinese investment for the first time. Also read: 2011 results for Taiwan’s LED makers and packagers

Read the full report on Taiwan’s investment regulation changes from Argin Chang, Faith Hung, Chris Lewis at Reuters at http://www.reuters.com/article/2012/03/20/taiwan-china-investment-idUSL3E8EK0RM20120320

In 2011, Taiwan took over as the world leader for installed capacity of semiconductor manufacturing, with 21% of total capacity.

Taiwan also recently re-elected its leader Ma Ying-jeou of the Kuomintang (KMT) for a second term. Ma is not expected to make any major economic and regulatory reforms, according to the US-Taiwan Business Council.

Last month, Taiwan’s Ministry of the Interior (MOI) relaxed its conditions for granting multiple-entry visas to mainland Chinese, to make it more convenient for mainland Chinese business people to visit Taiwan and promote business opportunities. Once the new measures are implemented, the number of mainland Chinese business people obtaining multiple-entry visas is expected to double from the current 4,191 to more than 8,000 a year.

March 15, 2012 — Semiconductor assembly and test services (SATS) provider Amkor Technology Inc. (Nasdaq:AMKR) added Mike Liang as president of Amkor Technology Taiwan. Liang’s background includes stints with Phoenix Semiconductor, Ti-Acer, UMC, and others.

Liang and his team will serve packaging and test customers and execute Amkor’s strategies in Taiwan. Taiwan recently took the global lead in wafer fabrication capacity, beating out its Asian neighbors and the Americas. Taiwan also leads in 300mm wafer capacity installed.

Liang brings "a proven track record in operations, sales and marketing for semiconductor packaging, wafer processing and testing services," said JooHo Kim, Amkor EVP, worldwide manufacturing operations. Liang was most recently president and CEO of King Yuan Electronics Corporation in Hsin-Chu, Taiwan, and has held executive and operational roles at Phoenix Semiconductor International, AbelLink Technology, Mosel-Vitelix, Ti-Acer, and United Microelectronics Corporation (UMC). Liang holds a Bachelor of Science in physics from National Cheng Kung University and an MBA from National Taiwan University.

Amkor provides semiconductor packaging and test services to semiconductor companies and electronics OEMs. More information on Amkor

March 9, 2012 — IBM (NYSE:IBM) scientists developed a prototype optical chipset, Holey Optochip, that can transfer 1 trillion bits (1Tbit) per second as a parallel optical transceiver, or 8X faster than today’s parallel optical components. IBM expects to commercialize the concept within a decade, with the help of its chip manufacturing partners.

The chip-scale transceiver relies on higher levels of integration, power efficiency and performance through packaging and circuit innovations, said IBM Researcher Clint Schow, part of the team that built the prototype. Optical chips transfer data using light pulses instead of electron transmission on wires. The aim is to use optical signals on chips made via standard low-cost/high-volume manufacturing methods.

Photo 1. IBM’s Holey Optochip. Original chip dimensions are 5.2 x 5.8mm.

To make the Holey Optochip, IBM fabricated 48 through-silicon holes (optical vias) through a standard 90nm silicon CMOS IC. The holes allow optical access through the back of the chip to 24 receiver and 24 transmitter channels, creating an ultra-compact, high-performing and power-efficient optical module. The transceiver consumes <5W power. The Holey Optochip module is constructed with components that are commercially available today, with an eye on future commercial scaleability.

Simple post-processing on completed CMOS wafers with all devices and standard wiring levels results in an entire wafer populated with Holey Optochips. The transceiver chip measures 5.2 x 5.8mm. Twenty-four channel, industry-standard 850-nm VCSEL (vertical cavity surface emitting laser) and photodiode arrays are directly flip-chip soldered to the Optochip. This direct packaging produces high-performance, chip-scale optical engines.

The Holey Optochips are designed for direct coupling to a standard 48-channel multimode fiber array through an efficient microlens optical system that can be assembled with conventional high-volume packaging tools.

Photo 2. The back of the IBM Holey Optochip with lasers and photodectors visible through substrate holes. 

Parallel optics is a fiber optic technology primarily targeted for high-data, short-reach multimode fiber systems that are typically less than 150m. Parallel optics differs from traditional duplex fiber optic serial communication in that data is simultaneously transmitted and received over multiple optical fibers.

The research will be presented at the Optical Fiber Communication Conference taking place in Los Angeles. Learn more at www.ibm.com.

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March 7, 2012 — Semiconductor fab equipment supplier Applied Materials Inc. (AMAT) opened the new Centre of Excellence in Advanced Packaging at Singapore’s Science Park II with its partner in the endeavor, the Institute of Microelectronics (IME), a research institute under Singapore’s Agency for Science, Technology and Research (A*STAR). Singapore’s Minister for Trade and Industry, Lim Hng Kiang, presided at the official opening ceremony.

Plans for the Centre were first announced in April 2011.

The Centre of Excellence in Advanced Packaging will focus on wafer-level and 3D packaging technologies, with a 14,000 square foot Class-10 cleanroom housing 300mm wafer processing equipment. It was created with combined investment of over USD100 million from Applied Materials and IME.

Applied Materials will provide the leading-edge equipment and process technology to be used by IME

March 6, 2012 — Semiconductor test and advanced packaging service provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) uncrated its next-generation 3D embedded wafer-level ball grid array (eWLB) package-on-package (PoP) technology, with a package profile height below 1.0mm.

The PoP format aims for higher thermal and electrical performance, increased bandwidth and speed in an ultra thin package profile, with design flexibility in integrating memory and logic semiconductors. Industry standard is 1.4mm total stacked package height, 30% more than STATS ChipPAC’s new 3D eWLB. STATS uses fan-out wafer level packaging (FOWLP) to reduce the bottom PoP package height below 0.5mm. The technology also offers tighter substrate line/space capability. eWLB PoP is available in single or double-sided configurations.

STATS ChipPAC also offers a co-design process with packaging customers to optimize the functional performance of the ultra thin 3D package. The 3D PoP form factor targets advanced mobile applications: smartphones, media tablets, cloud computing, etc. Microprocessors are adopting the technology. Computing-sector customers are also using eWLB to reduce substrate complexity and cost.

Over 200 million eWLB units are in the market, with package architectures including small die, large die, multi-die and multi-layer designs.

STATS ChipPAC will present on innovative 3D packaging, covering eWLB, low-cost copper (Cu) column flip chip PoP technology, and stacked die integration of RF packages at the IMAPS International Conference and Exhibition on Device Packaging this week in Scottsdale, AZ.

STATS ChipPAC Ltd. provides semiconductor packaging design, assembly, test and distribution services. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com.

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March 6, 2012 – PRNewswire — Flip chip bumping and wafer-level packaging (WLP) supplier FlipChip International (FCI) signed a set of license, sales, and marketing agreements with NANIUM S.A., semiconductor manufacturing, test and engineering services provider, for 300mm flip chip bumping and WLP.

The partnership revolves around NANIUM’s 300mm WLP services and FCI turnkey bump services for 150mm and 200mm wafers. NANIUM will license the FCI Spheron plated copper (Cu) redistribution technology, adding fan-in wafer-level packaging (FIWLP) and wafer-level chipscale packaging (WLCSP) technologies to its portfolio of fan-out WLP (FOWLP). "Together, FCI and NANIUM offer a complete WLP service portfolio covering 150, 200 and 300mm wafer sizes," summarized Armando Tavares, NANIUM president of Executive Board.

NANIUM signed a similar technology agreement with Tessera Inc. in 2010.

The companies have an eye on next-generation packaging needs for high-performance/small form factor semiconductors in smartphones, medical devices, tablets, automotive ICs, graphics processors, microprocessors, and wireless 3G/4G integrated products. WLP and flip chips are gaining "global strategic importance," said Bob Forcier, FCI president and CEO.

NANIUM provides package and system design, development, manufacturing, testing and engineering services in the semiconductor business, operating mainly in WLP. NANIUM also offers packaging based on laminated organic substrates and metal leadframes. Website: www.nanium.com.

FCI provides products and services for the wafer bumping and wafer level packaging market. FCI is a subsidiary of RoseStreet Labs LLC, a supplier of products and services for the semiconductor, renewable energy and life science markets. Website: www.flipchip.com.

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March 5, 2012 — Plessey Semiconductors developed the Electric Potential Integrated Circuit (EPIC) sensor, optimized for use as an ECG sensor, at a reportedly lower cost and better resolution than conventional electrodes. It enables ECG monitoring in mobile phone applications.

"EPIC is a completely new kind of sensor that detects changes in electric field potential," explained Barry Dennington, Plessey’s COO.

The product was developed as part of the Precision Passive Component Design and Manufacture in Micro Module Electronics project (PPM2), co-funded by the Technology Strategy Board. The Precision Passive Component Design and Manufacture in Micro Module Electronics project encouraged the integration of precision passive components into advanced packaging schemes, improving performance.

The Nanotechnology Knowledge Transfer Network (NanoKTN), a UK knowledge-based network for Micro and Nanotechnologies, announced details of the product, developed by UK-based semiconductor manufacturer Plessey, and supports promotion to potential end-users and partners, along with JEMI UK.

Plessey Semiconductors and JEMI UK organized a technical visit to its facilities in Plymouth to disseminate outcomes from the PPM2 project and to launch the EPIC sensor. Delegates discussed opportunities for the UK supply chain and IC manufactures to utilize these techniques in their own devices.

The NanoKTN played a key role in disseminating results from the PPM2 project and encouraged a number of potential end-users for Plessey’s products developed through the program, to attend the event and hear more about the potential benefits. By disseminating the outcomes to key audiences via the NanoKTN’s website and the NanoKTN’s extensive database of contacts, key target audiences were brought together in a personal setting to network and develop business relationships.

"Building relationships and contacts within relevant industries is vital to companies in the early stages of commercial development, enabling them to build connections and to raise their profile nationally and overseas. We hope that by helping to disseminate outcomes from this project, that UK businesses will come together and look at ways of using the intelligence gathered throughout the programme," explained Dr Alec Reader, Director at the NanoKTN.

The NanoKTN’s primary aim is to encourage collaboration and knowledge transfer between key players in industry, as well as start-ups and small/medium enterprises (SMEs). The NanoKTN is dedicated to helping its members understand how to write a successful proposal and identify suitable partnerships for collaborative work. The NanoKTN facilitates the transfer of knowledge and experience between industry and research, offering companies dealing in small-scale technology access to information on new processes, patents and funding as well as keeping up-to-date with industry regulation. The four broad areas that the NanoKTN focuses on are: Promoting and facilitating knowledge exchange, supporting the growth of UK capabilities, raising awareness of Nanotechnology, and providing thought leadership and input to UK policy and strategy. Established by the Technology Strategy Board, the NanoKTN is managed by Centre for Process Innovation Ltd, a leading technology development and consulting company. Further information about the NanoKTN can be found at www.nanoktn.com.

JEMI UK is the Joint Equipment and Materials Initiative; a non-profit organization, representing more than 55 companies and part of a network of organizations throughout Europe. JEMI UK was founded to promote the development of a strong infrastructure to support the growth of companies in the Semiconductor supplier industry, while ensuring that the interests of manufacturers and suppliers within the industry are properly represented.

Plessey Semiconductors develops and manufactures semiconductor products used in sensing, measurement and controls applications.

The Technology Strategy Board is a business-led government body that works to create economic growth by ensuring that the UK is a global leader in innovation. Sponsored by the Department for Business, Innovation and Skills (BIS), the Technology Strategy Board brings together business, research and the public sector. For more information, please visit www.innovateuk.org.

KTNs have been set up by government, industry and academia to facilitate the transfer of knowledge and experience between industry and the science base. The first KTNs were set up in 2005; they are active in sectors, technologies and market-based areas and they interact strongly with the government’s Technology Programme and overall technology strategy.

The Centre for Process Innovation (CPI) is a UK based technology innovation centre and part of the government’s High Value Manufacturing Catapult. CPI offers market and technology expertise along with cutting-edge development assets to help its public and private sector clients build and prototype the next generation of products, processes and services quickly and efficiently, and with minimal risk.