Category Archives: Wafer Level Packaging

Update February 1, 2012 – BUSINESS WIRE — Tessera Technologies, Inc. (NASDAQ:TSRA) announced that, after a series of discussions with Starboard Value LP, together with its affiliates, Starboard has agreed in writing to rescind its nomination notice for the election of directors at the upcoming 2012 Annual Meeting of Stockholders.

"After constructive discussions with Tessera Technologies, Inc., we have decided not to move forward with the nomination of directors at the 2012 annual meeting. Based on the Company

January 3, 2012 – BUSINESS WIRE — Enpirion, Inc. entered into a strategic partnership agreement with JiangyinChangdian Advanced Packaging Co., Ltd. (JCAP) for the manufacturing of silicon-based magnetics utilizing Enpirion’s proprietary micro electronic magnetic silicon (MEMS) technology. Earlier in 2011, Enpirion demonstrated that its MEMS technology achieved all necessary application performance figures-of-merit at record frequencies of 18 MHz in its DC-DC power system-on-chip (PowerSoC). This announcement marks another key milestone in Enpirion’s leadership and commercialization efforts using low-cost silicon-based magnetics partnering with JCAP with its specialized, high volume wafer level packaging manufacturing capabilities. JCAP is implementing and fully qualifying Enpirion’s innovative magnetic material processes.

"I am happy to announce our collaboration with JCAP on the integration of Enpirion’s advanced MEMS technology into JCAP’s innovative wafer level manufacturing operations," said Denis Regimbal, CEO of Enpirion. "Since the company’s inception, we have invested heavily in developing silicon-based magnetic technologies that complement our high frequency CMOS power technology. This will permit Enpirion to continue to extend its leadership in integrated DC-DC power solutions by penetrating into new applications such as cost-effective LDO replacements."

Lai Chih-Ming, President of JCAP said: "We are excited to have been selected by Enpirion, the leader in integrated power management, to bring to market this advanced technology for magnetic materials on silicon wafers for the first time in power applications using our world renowned, innovative, high volume wafer level bump and chip scale manufacturing processes. Clearly this next generation technology will deliver the first low cost, fully integrated DC-DC converter on silicon. We look forward to growing this business with Enpirion."

Enpirion, the leading provider of integrated power management solutions, simplifies design complexity while addressing the space constraint and efficiency needs faced by designers of enterprise, telecom,storage, industrial and embedded applications. For more information about Enpirion, please visit www.enpirion.com .

JiangyinChangdian Advanced Packaging Co., Ltd. (JCAP) is a subsidiary of Jiangsu Changjiang Electronics Technology Co., Ltd. (JCET) a leading manufacturer of discrete semiconductor devices, the largest indigenous packaging subcontractor for discrete and IC packaging assembly and test in mainland China. For more information about JCAP, please visit www.jcap.cn

December 29, 2011 – At the recent 7th annual RTI 3-D Architectures for Semiconductor Integration and Packaging (3D ASIP) Conference in Burlingame CA, the "buzz" centered around the presentation by TSMC‘s Doug Yu, senior director of integrated interconnect, who repeated the case he had made at the November Georgia Tech Interposer Conference [see "2.5D announcements at the Global Interposer Tech conference"] for the pure foundry model for 2.5 and 3DIC — claiming that TSMC was readying to take on full beginning to end interposer manufacturing.

Yu told the audience of more than 200 that sharing the fabrication process with OSATs is not the preferred option for TSMC, because "the risk for the customer is too high […] therefore we [TSMC] will take full responsibility and accept full risk." TSMC is proposing that such one stop shopping will be simpler, cheaper and more reliable than using multiple sources (i.e. foundries, assembly houses and potentially other partners). Yu remained steadfast in his assessment that the required investments and the technology needed to handle thinned wafers would require that the foundries take control of such processing: "This is a new ballgame; the old ways of doing business are out of date for this new technology." On rumors that TSMC is currently working with only a handful of 2.5D/3D customers (including Xilinx); he indicated that "new customers will have only the integrated solution proposal […] some, but not all of them [customers] want us to work with other partners, but many like our new approach very much."

Certainly with customer Xilinx being first to enter the 2.5D market space, TSMC appears ahead of the rest of the foundries in this regard. Ivo Bolsens, VP and CTO of Xilinx detailed the company’s Virtex 2000T FPGA product which he claims delivers 4

December 29, 2011 — Diodes Incorporated (Nasdaq:DIOD) began packaging MOSFETs in the miniature DFN1212-3 package for cooler operation than the equivalent-footprint SOT723 package.

The MOSFET pair initially released by Diodes are 20V rated and comprise the DMN2300UFD N-channel and the DMP21D0UFD P-channel parts. 30V and 60V rated parts will follow in the DFN1212-3 package, along with a comprehensive range of bipolar devices.

With a junction to ambient thermal resistance (Rthj-a) of 130

December 27, 2011 — Small, mobile, Internet-connected devices are bucking the slow economy and use advanced packaging technologies to pack an enormous amount of functionality into a very small form factor, notes New Venture Research. The chip packaging method also determines the speed and performance of that chip, as well as its battery consumption.  

Advanced IC packaging technologies include system in package (SiP), stacked packages, fan-in quad flat pack no leads (QFN), fan-out wafer-level packages (WLP), and interconnection styles of 3D and 2.5D through-silicon vias (TSV) and flip chip. The use of these packaging technologies for mobile electronic devices is covered in New Venture Research’s Advanced IC Packaging Technologies, Materials, and Markets, 2011 Edition.

Stacked packages are essentially a vertical multichip package. They come in many forms, including die stacks, package on package (PoP), package in package (PiP), TSOP stacks, QFNs, MCMs, and WLPs. Now found in all cell phones, stacked packages are in a high-demand market. Stacked package revenue will experience a 10% compound annual growth rate (CAGR) through 2015.

TSVs/3D interconnect creates a die stack with short interconnection distance for high speed, low power consumption, reduced parasitics, and small form factor. Vias go through the silicon, electrically connecting the die vertically. It replaces wire bonds and other second-level interconnects. The identified potential markets for TSVs will grow from 35 billion units in 2010 to over 54 billion in 2015.

System in package (SiP) devices are a functional block, a system of electronics that combines functional units together onto a single substrate to enable the shortest electrical distance between parts for superior performance. This reduces the amount of traces going into and out of the package, enabling a more simplistic PCB for the final product and potentially reducing system costs.  Revenue for SiPs will expand at a 5.4% CAGR through 2015.

To increase the reach of the QFN package, fan-in QFN involves extending the number of rows of leads from the usual one to two or three rows. This allows hundreds of package leads, up from the 50 or fewer in a traditional package design. Although the number of fan-in QFNs assembled currently is quite small, the potential is huge, with a projected CAGR of 63.1% for revenue through 2015.

Reconfigured or fan-out wafer-level packages (FOWLP) were introduced in 2006. After devices are manufactured on a wafer, the devices are sawn and transferred on a carrier to another larger wafer that has gaps between die, which are filled with overmold material that also coats the back side of the devices for protection. This allows for a larger surface on which to extend a redistribution layer, thus allowing for far more I/Os than would be possible on the original smaller WLP surface. Solder balls or bumps can be added to this surface for interconnection to a printed circuit board (PCB). Fan-out WLPs are expected to have a CAGR of 15.9% for revenue through 2015.

Cellular handsets are the primary handheld electronic gadget globally, especially in areas too vast to support wired communication lines. Cellular handsets are growing at an 8.5% CAGR between 2011 and 2015, and smart phones, a subset of total cellular handsets, are growing at a 15.2% CAGR.

More information can be found on these topics and others in the new report, Advanced IC Packaging Technologies, Materials, and Markets, 2011 Edition, from New Venture Research at newventureresearch.com.

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December 26, 2011 — Yole Développement studies the evolution of inertial micro electro mechanical systems (MEMS) and magnetometers and provides reverse costing analysis of the MEMS devices in "Technology Trends for Inertial MEMS," volumes 1 & 2. The report considers 23 MEMS devices.

Four identifiable trends are revealed: future generation of sensors will deliver functions; sensor fusion, combining data from different sensors, is on the rise; new architectures are emerging; and price pressure is still very strong (5% drop per quarter for consumer applications), said Laurent Robin, activity leader, inertial MEMS devices and technologies at Yole Développement.

Yole’s report shares market drivers for inertial MEMS, including consumer, automotive, and high-end applications. Packaging and test trends for the devices are discussed. Over the last 3 years, inertial MEMS & magnetometers have been subject to dramatic market & technological evolutions. This has been driven by a large increase of the consumer market: mobile phones and tablets for accelerometers; gaming for gyros; mobile phones for magnetometers.

Along with “stand-alone” MEMS devices, inertial combo sensors, a combination of several inertial sensors into a single package, are also coming. Main applications are consumer (e.g. accelerometer with magnetometer or accelerometer with gyro) and automotive for ESC and rollover functions first.

On the technical side, form factor is ever decreasing with reduced footprint and thickness. And power consumption has been reduced to a few microA while performances are still increasing. The most successful type for inertial MEMS is based on capacitive transduction. Reasons are simplicity of the sensor element, no requirement for exotic materials, low power consumption and good stability over temperature. But will comb-drive architecture for accelerometers continue to be the main detection principle as MEMS die size keeps shrinking?

Regarding gyroscopes, most are falling into the categories of tuning vibrating fork/plate (STM, Bosch) or vibrating shells (Silicon Sensing Systems). This very common design gives ease of fabrication and possible integration in standard IC manufacturing industry.

For magnetometers, Hall Effect has been the dominant technology for a long time, but today it is changing as Magneto Impedance, Giant Magneto Resistance and Anisotropic Magneto Resistance are used. A new approach, Lorentz effect based on MEMS technology, is currently in R&D (VTT and others). This could bring easier integration in MEMS combo sensors.

"Testing has been also subject to strong evolution over the last years," said Dr. Eric Mounier, senior analyst, MEMS Devices & Technologies at Yole Développement. For example, combo sensors will require new test solutions compared to “stand-alone” sensors. Beyond the usual wafer-level electrical test and package-level electrical and mechanical or functional testing, these sensor combos will need module level testing and calibration of the combined sensors. If they include an MCU in the package, the communication between the sensors and the MCU will also need to be tested. Solutions need to be cost effective with high throughput to test multiple axes of multiple devices, either in parallel or in separate modules, rather like separate chambers in IC equipment.

The world of MEMS testing has moved in the last several years from internal development at MEMS makers to co-development with test suppliers to commercial off the-shelf equipment. So combo solutions that can test all axes of the module in a single tool for higher throughput will also likely be co-developed with the test equipment suppliers and available commercially. Assembly and test houses may also start to offer these test services on an outsource basis for fabless or fab-light MEMS makers. The Yole Développement report will analyze the latest trends in MEMS testing.

In order to understand the key evolutionary changes, a total of 23 different MEMS devices (9 accelerometers, 10 gyros, 3 combos and 1 magnetometer) — mostly consumer MEMS — have been disassembled, analyzed and cost simulations have been constructed for MEMS, ASIC and Packaging/Test. One of the key features of the reports is that ASICs have been analyzed as well. The MEMS have been analyzed and production costs have been simulated by System Plus Consulting, the reverse costing specialist company. The teardown analysis results have been compared in terms of performance, total cost, MEMS size, ASIC lithography node, ASIC size, package size, year for market introduction.

From its analysis, Yole Développement found there is a clear MEMS die size decrease over 2007-2011. For example, in 2008, the average size for an accelerometer (3-axis) was 4-5mm². 3 years later, size is about 2mm². ASIC size has been following the same trend with a lithography node in the range 0.18-0.35μ today. "With latest ST announcement about the use of through silicon vias for inertial, we can expect even lower cost and size in the future," said Robin. The same analysis has been performed for gyros comps, combos and magnetometers.

Companies cited in the report:
Accutronic, Advanced Microsensors, Advantest, Afore, Aichi, AIS/SSS, AKM, Analog Devices, ASE, Baolab, Bosch Sensortec, CascadeMicrotech, CEA Leti, Colibrys, Epson Toyocom, Freescale, Gladiator Technologies, Honeywell, Invensense, Jyve, Kionix, KYEC, Litef, Memsic, Multitest, Murata, Panasonic, Polytec, Qualtre, Rohm, Sensonor, Sensordynamics, Sony, SPEA, SSS, STM, Systron Donner,TEL, Teradyne, Thales, Tronics, VTI, VTT, Yamaha

Dr. Eric Mounier has a PhD in microelectronics from the INPG in Grenoble. He previously worked atCEA LETI R&D lab in Grenoble, France in Marketing dept. Since 1998 he is a co-founder of Yole Developpement, a market research company based in France. At Yole Developpement, Dr. Eric Mounier is in charge of market analysis for MEMS, equipment & material. He is Chief Editor of Micronews, and MEMS’Trends magazines (Magazine on MEMS Technologies & Markets).

Laurent Robin is in charge of the Inertial MEMS & Sensors market research at Yole Developpement. He previously worked at image sensor company e2v Technologies (Grenoble, France) and at EM Microelectronics (Switzerland). He holds a Physics Engineering degree from the National Institute of Applied Sciences in Toulouse. He was also granted a Master Degree in Technology & Innovation Management from EM Lyon Business School, France.

Yole Développement provides market research, technology analysis, strategy consulting, media in addition to finance services. Access the report catalog at www.yole.fr.

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December 19, 2011 — Powertech Technology Inc. (trading number:6239) has approved a tender offer of NT$25.28 per share for the common shares of Greatek Electronic Inc. (trading number:2441), with a minimum acquisition target of 166,061,377 shares, or 30% of the outstanding shares for Greatek. The maximum acquisition is set at 282,304,340 (51%).

Powertech can expect to spend up to NT$7.137 billion in the tender offer. The tender offer period runs through February 3, 2012 and must be approved by relevant competent authorities.

Greatek specializes in semiconductor packaging and test services, covering P-DIP, SOP, SOJ, SSOP, TSSOP, MSOP, QFP, LQFP, TQFP, PLCC, TO and QFN form factors. It boasts circuit probing and final test offerings, and owns 2 factories at Zhunan in Miaoli County, Taiwan (R.O.C.). Greatek employs 2500 people.

The deal would boost PTI’s logic-chip packaging portfolio. DRAM packaging is Powertech’s main business, Ken Liu of Taiwan-based China Economic News Service (CENS), notes, and the DRAM industry has suffered declines in recent quarters. Liu quotes PTI general manger Zhongji Liao as saying that the company will shift its logic packaging business to Greatek, which will operate as a independent manufacturer.

With the tender offer, Powertech plans to create a system of cross support of production between Powertech and Greatek, increasing market competitiveness and technological efficiency for various products and reducing costs for a total packaging process. The new alliance also is expected to increase consolidated revenue. Positive changes on enterprise value and return on equity of both companies is foreseeable, reports management.

Also read: Elpida, PTI, UMC finalize 3D IC partnership

Grand Cathay Securities is commissioned to serve as the financial adviser and PWC Legal is commissioned to serve as the legal consultant of offeror in the tender offer.

Powertech provides IC packaging, testing, and distribution. Powertech has more than 6,000 employees worldwide, with facilities at Hsinchu Industrial Park, Hsinchu Science-Based Park and Suzhou Industrial Park. Please refer to http://www.pti.com.tw for more information.

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