December 15, 2011 — Grid-array packages — ball grid arrays (BGA), land grid arrays (LGA), column grid arrays (CGA) — are getting larger, and as such as susceptible to mechanical stresses from handling, assembly onto PCBs, and test procedures. IPC and JEDEC created
Category Archives: Wafer Level Packaging
December 7, 2011 — Arteris Inc., network-on-chip (NoC) interconnect IP company, will incorporate its FlexNoC NoC interconnect IP into an SoC die on silicon interposer test chip with Taiwan Semiconductor Manufacturing Company (TSMC). TSMC recently approved additional spending on advanced packaging tech.
"TSMC chose to work with Arteris on the interposer based test chip program because its interconnect technology is ideally suited to addressing the SoC wire routing congestion and timing closure challenges," said Suk Lee, director of design infrastructure marketing at TSMC.
Arteris’s FlexNoC NOC interconnect IP is physically implemented as a distributed network of small design elements within a SoC floorplan. FlexNoC addresses bandwidth, latency, and quality of service (QoS) requirements introduced with wide data paths.
Arteris is a TSMC Open Innovation Platform Partner and a participant in TSMC’s Reference Flows 11.0 and 12.0.
Arteris Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. More information can be found at www.arteris.com.
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November 30, 2011 — The Institute of Microelectronics (IME), a research institute of the Agency for Science, Technology and Research (A*STAR), plans to commercialize key innovations in silicon photonic chips designed to support high-speed, high-bandwidth optical communications. Developed as part of IME
November 29, 2011 — OSRAM Opto Semiconductors introduced the Oslon Square LED for lighting applications, packaged enclosed in a reflective layer to boost light output.
The reflective package technology increases system efficiency, redirecting light from the side and back of the LED chip to the front. Light that is reflected back to the LED within a system, for example from a diffuser, can also be recycled in this way. At an operating current of 700mA, it achieves an efficiency of above 90lm/W and a luminous flux of 200lm and more. At 350mA, its efficiency exceeds the 100lm/W mark.
Also read: Thin-film chip boosts LED optical output without changing footprint
The Oslon Square is available in various versions and color temperatures, and can be operated with different currents. The Square measures 3 x 3mm, has thermal resistance of 3.8
November 28, 2011 – Marketwire — STATS ChipPAC Ltd. (SGX-ST:STATSChP), a semiconductor test and advanced packaging service provider, was named "Supplier of the Year" by Cirrus Logic Inc. (NASDAQ:CRUS), analog and mixed-signal processing components maker.
STATS ChipPAC provides full turnkey semiconductor assembly and test services (SATS) for Cirrus Logic’s portable audio solutions, which are used in diverse consumer electronics products. STATS ChipPAC was recognized from among Cirrus Logic’s back-end service providers.
Cirrus Logic aims for "very small and very economical" audio products, notes Randy Carlson, VP of supply chain management, Cirrus Logic, who credited STATS ChipPAC’s "responsiveness and exceptional performance during this past year" for advancing the company.
Hal Lasky, EVP and chief sales officer, STATS ChipPAC, added that his company’s high-performance wafer-level packaging (WLP) abilities were instrumental in supporting Cirrus Logic.
STATS ChipPAC recently named its own top suppliers.
STATS ChipPAC Ltd. provides semiconductor packaging design, assembly, test and distribution for communications, digital consumer and computing. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com.
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November 24, 2011 — Hynix Semiconductor Inc. exercised the renewal option in its March 31, 2005 license agreement with Tessera Technologies Inc. (NASDAQ:TSRA) to extend the term of that license to May 22, 2017.
November 23, 2011 – BUSINESS WIRE — The Design Automation Conference (DAC) is soliciting semiconductor industry experts for participation in invited sessions, panels, and other events at the 49th DAC, June 3-7, 2012 in San Francisco, CA.
Nominees should be experts in:
- Analog/Mixed-Signal and RF
- Beyond Die-Integration and Package/Hybrid/Board Design
- Circuit Simulation and Interconnect Analysis
- Embedded HW Design and Applications
- Embedded SW Tools and Design
- FPGA Design Tools and Applications
- High-Level Synthesis
- Logic Synthesis and Circuit Optimization
- New or Emerging or Specialized Design Technologies
- Power Analysis and Low-Power Design
- System-Level Communication and Networks on Chip
- Timing Analysis and Design for Manufacturability
- Physical Design and Manufacturability
- Signal Integrity and Design Reliability
- System-Level Design and Co-Design
- Testing
- Verification
The experts will be entered in the DAC Speakers’ Bureau, which acts as the resource center from which the DAC Executive Committee can contact interesting and experienced speakers from all areas of EDA for participation at the 49th DAC. Third-party nominations, highlighting prior presentations by the nominated speaker that generated substantial audience interest, are especially appreciated. Self-nominations are also accepted. Nominations can be made at http://www.dac.com/speakers+bureau.aspx.
The Design Automation Conference (DAC) covers the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. Learn more at www.dac.com.
November 22, 2011 – PRNewswire-Asia-FirstCall — ChipMOS TECHNOLOGIES (Bermuda) LTD. (Nasdaq:IMOS) subsidiary ThaiLin Semiconductor Corp. will take on dedicated semiconductor testing capacity for a new long-term service agreement with its client Asahi Kasei Microdevices Corporation (AKM).
Under the new agreement, AKM will consign to ThaiLin certain sets of mixed-signal tester equipment, which ThaiLin will use as dedicated capacity to test AKM devices. This will allow ThaiLin to provide a critical testing facility without capex investment, noted S.J. Cheng, Chairman and CEO of ChipMOS.
The companies have worked together since 1999.
Hideki Kobori, president of Asahi Kasei Microdevices Corporation, commented that the new agreement follows AKM’s geographic diversification strategy following Japan’s March 11 earthquake and tsunami off Sendai. AKM is fortifying its supply chain with a long-term partner, ensuring quality control, Kobori said.
The new business will give ChipMOS access to wafer level chip scale packaging (WLCSP) technology, which helps it penetrate the smartphone/tablet device manufacturing market, said Cheng. ChipMOS also is building its LCD driver business for this end-use sector.
Asahi Kasei Microdevices Corporation (AKM) is the core operating company for all electronics devices operations of the Asahi Kasei Group. AKM provides mixed-signal ICs for consumer, automotive, and communication applications as well as magnetic sensors. Learn more at www.asahi-kasei.co.jp/akm/en/.
ChipMOS is an independent provider of semiconductor testing and assembly services to customers in Taiwan, Japan, and the U.S. Learn more at www.chipmos.com.
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November 17, 2011 – Marketwire — STATS ChipPAC Ltd. (SGX-ST:STATSChP), semiconductor test and advanced packaging service provider, completed the expansion of its 300mm wafer bump and wafer-level chipscale packaging (WLCSP) operation in Taiwan.
STATS ChipPAC invested more than $150 million in Taiwan, building up a full turnkey wafer bump and WLCSP offering. The expansion increased production capacity at STATS ChipPAC Taiwan Co. Ltd. to 420,000 bumped wafers/year and 60,000 WLCSP devices/year. STATS ChipPAC Taiwan’s advanced WLP technologies include low-temp cure polymers, copper for under bump metallization (UBM) and redistribution layers (RDL), and more.
In January 2011, STATS ChipPAC grew its 300mm wafer-level packaging ops at the site.
Wafer-level, flip chip, and wafer bump packaging processes "cater to the most demanding needs of mobile and consumer devices," said Wan Choong Hoe, EVP and COO, STATS ChipPAC. STATS ChipPAC is growing this business to support advanced technology nodes and form factors. Benefits of WLCSP include virtually die-sized packages, better thermal performance, finer pitch board-level interconnects, and improved functionality.
"We have tripled our Class 100 cleanroom space to 3,478 square meters or 37,437 square feet and significantly increased both our 300mm bump and WLCSP capacity. We have been working to expand our technology processes to support bump pitches down to 40um," said Richard Weng, managing director, STATS ChipPAC Taiwan.
An official inauguration was held at STATS ChipPAC Taiwan with more than 80 honoured guests and company management participating.
STATS ChipPAC Ltd. performs semiconductor packaging design, assembly, test and distribution. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com.
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November 16, 2011 – A host of companies are offering, or are in development with, fan-out wafer-level packaging (FO-WLP) for devices with large numbers of I/Os as an alternative to going finer-pitch (0.3-0.35mm) to keep using conventional fan-in technology, says TechSearch International, in an updated report.
Fan-out WLP offers the same low-profile advantage as conventional WLP: singulated die are placed into a "reconstituted wafer" with enough space around each chip to accommodate second-level connections. Among those offering or prepping FO-WLP options is the newly launched Deca Technologies; TechSearch cites Deca president/Tim Olson praising the "tremendous" promise of the technology to improve cost, inflexibility, and cycle times for tooling substrates, assuming the industry can overcome some "capital disadvantages and a few engineering challenges. "We are close to a tipping point," he says. Others offering FO-WLP include the usual SATS firms (Amkor, ASE, SPIL, STATS ChipPAC) plus a host of others including ADL, Freescale, Fujikura, Intel (via Infineon’s wireless division), King Dragon, Nanium, Nepes (via Freescale’s 300mm RCP line), Renesas, and Teramikros (n