Category Archives: Wafer Processing

ACM Research (Shanghai), Inc. has announced that it has solved the problem of patterned wafer cleaning. This is another breakthrough at ACM after it developed Space Alternating Phase Shift (SAPS) megasonic cleaning in 2011.

Compared to flat wafer cleaning, patterned wafer cleaning is much more complicated and challenging. With the decreasing line width and increasing aspect ratio, cleaning a patterned wafer without damage is much more difficult than ever. Meanwhile, as the feature size continues to shrink, the impact of fine particles (less than 30 nm) and contaminates to final device yields are much more significant.

“Finding the solution for patterned wafer cleaning has been an urgent challenge for the semiconductor equipment industry in recent years,” Dr. David Wang, President and CEO of ACM, mentioned. “When it comes to 1X nm and below manufacturing nodes, you must be capable of cleaning particle sizes smaller than tens of nm, and one cleaning step is used on average after every two non-clean processing steps in order to achieve high yield. This is where ACM’s proprietary megasonic cleaning technologies areuniquely effective.”

ACM’s newly-developed, proprietary Timely Energized Bubble Oscillation (TEBO) technology solved the problem of pattern damages caused by transit cavitation in the conventional megsonic clean process. By using TEBO, the cavitation becomes stable without bubble implosion or collapse during megasonic cleaning processing. The damage-free physical cleaning capability of TEBO with high Particle Removal Efficiency (PRE) has been demonstrated on 1X nm patterned wafers. The TEBO cleaning technology can be applied not only in FinFet manufacturing processes, but also in the high aspect ratio of DRAM and 3D NAND manufacture processes. (Aspect ratio of 30:1 or even 60:1.)

TSMC today announced that the Company and the municipal government of Nanjing, China have signed an investment agreement. This agreement affirms that TSMC will make an investment in Nanjing valued at US$3 billion to establish TSMC (Nanjing) Co. Ltd., a wholly-owned subsidiary managing a 12-inch wafer fab and a design service center.

TSMC’s 12-inch fab site in Nanjing will be located in the Pukou Economic Development Zone. Planned capacity is 20,000 12-inch wafers per month, and the facility is scheduled to commence production of 16nm process technology in the second half of 2018.

As a technology leader, TSMC began volume production of 16nm process technology for customers in 2015, and accounted for more than half of the global foundry market for production of 14/16nm technology wafers in that year. Further significant increases in global foundry market share of the 14/16nm technology production is forecast for 2016. TSMC also holds the largest foundry market segment share in China with more than 100 Chinese customers.

“With our 12-inch fab and our design service center in Nanjing, we aim to provide closer support to customers as well as expand our business opportunities in China in step with the rapid growth of the Chinese semiconductor market over the last several years,” said TSMC Chairman Dr. Morris Chang. “We look forward to stronger collaboration with our customers to further expand our market share in China.”

A look into how the silicide process has evolved over the years, trying to cope with the progress in scaling technology and why it could no longer be of service to finFET devices.

BY ARABINDA DAS, TechInsights. Ottawa, Canada

Samsung and TSMC introduced their finFET devices in 2015 and joined Intel as the semiconductor industry’s three major manufacturers possessing the most advanced technology. Intel’s 14nm finFET 5Y70 processor was commercialized in 2014 and within six months Samsung mass produced their 14nm finFET Exynos 7 7420 SoC. Later that same year, TSMC started supplying their 16nm finFET based devices to Apple. Today Samsung and TSMC both supply their finFET based processors to Apple, which are being used for the iPhone6’s A9 processor.

Since the release of the iPhone6 several blogs and articles have been written about the cost of fabrication, the perfor- mance of tri-gates, the type of work-function materials used by the manufacturers, the dominant supplier for Apple and speculation about the future of finFET devices. TechInsights has performed detailed structural analyses of these three devices and has also tried to understand some of these questions. While comparing these structural reports on finFET devices, one small detail stands out is that a major pillar of semiconductor processing is missing. The silicide process is not being used. Intel stopped using the silicide process in their 22nm finFET “Ivy Bridge” Processor. Samsung and TSMC at 20nm used the existing planar structure and employed NiSi on top of their source and drain regions. But as soon as these two device makers adopted finFET structure in 14 and 16nm nodes they abandoned the thirty year old silicide process. It is interesting to look into how the silicide process has evolved over the years, trying to cope with the progress in scaling technology and finally also why it could not anymore be of service to finFET devices.

The silicide process has been an integral part of semicon- ductor manufacturing since the early 1980s. The first patents were filed by Motorola, Fairchild and IBM. This process is used as an interface between semiconductor material and metals to reduce the contact resistance between tungsten contacts and the source-drain regions or the gate electrode. This parasitic resistance should be minimized to enable higher drive currents in transistors. Silicides have metal-like properties and are made by reacting Si to refractory or near-noble metals. A large number of metals in the periodic table can form silicides. The most common silicides in the semiconductor industry are titanium silicide, tungsten silicide, cobalt silicide, nickel silicide and nickel-platinum silicide. Platinium was used to stabilize the NiSi phase at a specific temperature.

These compositions can exist in various phases and have unique phase diagrams. One particular integration process of silicides, known as self-aligned silicides (also termed ‘salicide’), has played a significant role in bipolar devices, passives and in CMOS devices. In this scheme, no additional mask is needed; the silicide is grown on exposed silicon or polysilicon surfaces and not at all on neighboring dielectric surfaces.

The main steps of growing the silicide are depositing a refractory metal or a near-noble metal on the exposed Si and then annealing in a non-oxidizing atmosphere at a suitable temperature to react the metal with Si. The duration of the thermal cycle should be long enough to convert the majority of the metal to a silicide composition. Several stages of annealing may be completed to stabilize the phase. Thereafter the unreacted metal is removed by wet-etching. For a detailed understanding of silicide process please refer to the book “Silicide technology for integrated circuits” by L.J. Chen or to the lecture notes from Professor Sarsawat from Stanford University [1].

The earliest image of the silicide process in TechInsights’ database is from Intel’s 166 Mhz Pentium microprocessor A80502166 based on a 0.35 μm CMOS process. The die markings of this device suggest that it was made in 1992-93. FIGURE 1 shows a TEM cross-section of a gate employing titanium silicide. The transistors in this device have 0.40 μm thick titanium silicide on top of the gates and silicided diffusions formed using a salicide process.

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The industry realized very quickly that TiSi2 was not easily scalable. It has two phases C49-TiSi2 and C54-TiSi2. The first is formed at temperatures between 350 to 700o C and has a resistivity of 60-80 μΩcm; while the other is formed around 750 ̊ C and has a resistivity lower than C49-TiSi2 (~20 μΩcm). As devices scaled down it became necessary to reduce the thermal budget which had the consequence of forming C49-TiSi2 instead of C54-TiSi2, which resulted in higher contact resistance. Since this was counter-productive, it was time to switch to a new silicide. Intel’s Pentium III “Tualatin” used Co-silicide in a 0.13 μm CMOS process (FIGURE 2).

The next major milestone for silicide processes came at the 90nm node when Intel introduced the concept of raised source and drain for the PMOS transistor in their “Prescott” processor. The raised source and drain regions were formed by etching out portions of the Si substrate at the source and drain regions and then depositing epitaxial layers of Si1-xGex, where x is between 0 and 1. The etching out used both dry and wet chemistry. This concept was an innovative use of the growth rate variability on the bottom surface and on the side walls of the cavity due to the different crystal plane orientations of the silicon substrate. SiGe has a lattice constant that is slightly larger than that of silicon so this epitaxial film induces a large uniaxial compressive strain in the PMOS channel region, resulting in significant hole mobility improvement. But SiGe surfaces were not very suitable for Co-Silicide. Most silicides have much lower free energy than germanides so when the silicide is formed on a Si-Ge alloy the Ge is expelled. This expelled Ge undergoes agglom- eration and increases the contact resistance thus negating the effect of the enhanced mobility. The use of Ni instead of Co was especially beneficial for salici- dation of both Si and SiGe source drain regions because Ni provides a more uniform contact resistance. Moreover, NiSi has the same resistivity as CoSi2 but has smaller Si consumption. FIGURE 3 shows Intel’s 90nm “Prescott” transistor along with NiSi on top of SiGe regions.

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NiSi was the mainstream process for two process nodes (90nm and 65nm) and was employed on top of polysilicon gate as well as on top of the source-drain regions. Around the year 2000, there were even discussions about a fully silicided (FuSi) gate. Then in 2008 Intel introduced the high-k dielectric and metal gate-last (HKMG) process at the 45nm node in their “Penryn” processor. This device did not require any more silicide on top of the gate but only at the source-drain regions. FIGURE 4 shows a TEM cross-section of Intel’s 45nm “Penryn” processor. In these devices, silicide is formed only on top of source and drain regions. The silicide is self-aligned to the sidewall spacer. The surface of the SiGe source-drain regions that is in contact with the silicide has enriched Si concentration to facilitate the silicide process. The nickel silicide depth from the silicon surface is about 65nm.

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Finally, in 2012 Intel commercialized the first finFET device at 22nm in their “Ivy Bridge” (Intel core i5-3550) processor, in this device the silicide process was abandoned. To understand why the silicide process was not employed, it is important to grasp the differences between a tri-gate device and a planar device. Tri-gate brought in several advantages. For example, the effective gate width is proportional to the fin height and can be increased without increasing the device footprint. Additionally, because the gate wraps around the fin, there is better control of the channel. Another benefit is that the walls of the fin offer a different crystallographic plane than the top of the fin. Here, in this integration schemethe PMOS transistors benefit from higher mobility along the fin sidewalls.

The tri-gate integration scheme also brought in several process challenges. Epitaxial SiGe for PMOS and epitaxial Si islands for NMOS must be grown in a recess in a narrow Si fin rather than in the Si substrate. One constraint is due to double patterning, which requires that all the fins be of the same width and pitch; so if a larger gate width is required then multiple fins have to be employed. That means that the gate width is dependent on integer units of fins. This concept of integer units of fins is well illustrated in FIGURE 5, where the I/O transistor of TSMC finFET is shown having several fins connected in parallel.

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Multiple fins connected in parallel imply that the contact to the source-drain regions must have exactly the same contact resistance on multiple fins and this was indeed difficult to guarantee with the silicide process due to the vagaries of the diffusion process. In the Ni silicide process, it is believed that Ni atoms are the dominant diffusing species in Ni monosilicide formation; this property can lead to excessive silicidation on narrow lines. Ni-silicide is sensitive to temperature and often at low temperature a NiSi2 is formed. This phase is usually seen on strained PMOS structures and can create an increase of contact resistance. Non uniform distribution of silicide process was the biggest show-stopper for this old process.

In addition to the silicide process there was also the problem of dopants in the source and drain regions. The thermal process causes undesirable dopant diffusion and leads to the loss of the junction abruptness. Also, thermal processes create thermal budget issues in the integration’s process flow. There could be also other reasons for avoiding the silicide process in finFET devices, like leakage and stress because it is well known that the silicide process has an impact on device properties. Luckily, the technology of in-situ doping was already mature and used for DRAM devices as these volatile memories do not require a silicide process due to leakage concerns. Intel in its 22 nm process flow, most likely used in-situ doping of epitaxial regions along with trench contacts to eliminate the silicide process. This does not mean that other doping techniques like implants and thin film doping were not employed; they were probably used during different parts of the process flow. Intel did mention at IEDM 2014 that thin film doping method was used for 14nm finFET devices.

The introduction of trench contact, which ensure equal and low contact resistance to multiple fins was the ultimate reason not to use the silicide process in FinFETs. The integration flow is described in FIGURE 6. First, multiple parallel fins are formed. Each fin is separated from its neighbors by the STI-oxide. On these fins a sacrificial poly-silicon gate structure is made that runs perpendicular to the fins. On portions of the fin not covered by the gate, cavities are etched by using a line mask or a self-aligned process. Recesses in the fins are made by selectively etching the silicon. In-situ doped epitaxial layers are then grown to form source-drain regions. These epitaxial layers extend beyond the fin width and may even merge to form a continuous layer. The epitaxial layers do not extend above the surface of the fin. Subsequently, the poly-silicon gate is removed and the high-k-metal-gate (HKMG) formed in its place. A dielectric layer is deposited on top of the gates and the fins. The dielectric layer is patterned to form trenches running parallel to the gate. The integration scheme further includes etching a trench in the epitaxial layers and then filling the trench with tungsten to form trench contacts.

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FIGURE 7 shows the cross-sectional schematic diagram of how the trench contacts are embedded or well anchored in the epitaxial layers.

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Cross-sectional images parallel to the fins of the three 1x node finFETs from Intel, Samsung and TSMC are collected in FIGURES 8a, 8b and 8c, respectively. The cross-section is made along one of the fins. The important point to note is that the trench contact at the surface of the source and drain regions is surrounded on three sides. It is more pronounced in the case of Samsung’s device. The tungsten metal lines that run parallel to the gate, form the contacts for source-drain regions and are well anchored in the epitaxial layers. This increases the surface area of the contact and reduces the contact resistance.

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FIGURE 9 shows the cross-section of the 16nm finFETs from TSMC in the direction perpendicular to the fins. In this direction the epitaxial regions could be designed to merge or extend beyond the fin width and thus increase the contact region with the metal contact. This increased contact region reduces the contact resistance.

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The silicide process has a long history in the semicon- ductor industry; it has evolved through many phases from tungsten silicide to titanium silicide to cobalt-silicide to nickel silicide. But it could not be used for finFET devices. As for these devices, multiple fins may be used to form a single transistor, which implies that the contacts to all these fins have the exact same contact resistance. This is difficult to control in a process that is purely based on diffusion like the silicide process. So after 30 or more years of service it is time that the silicide process takes retirement and leaves the future to trench contacts and in-situ doping; however, there is always a possibility its use may be prolonged especially if the silicidation can be localized only inside the trench contact and not over the entire surface of the source-drain regions. Trench contacts will most likely be used in the next 10nm node but sub 10nm node, if new concepts like nanowire or new materials are introduced, the semiconductor industry is likely to innovate some other designs.

ARABINDA DAS is a Senior Process Analyst in the Technical Services division of TechInsights, Ottawa, Canada, [email protected]

An exploration of where trace metals come from, the impact they have on the industry and what can be done to reduce the risks.

KNUT BEEKMANN, Precision Polymer Engineering (PPE), part of the IDEX Sealing Solutions Group, Blackburn, England

Triboelectricity is defined as a charge of (static) electricity generated by friction. The concept was first applied in the 1940s for electrostatic painting and is now widely used in photocopy machines. This phenomenon becomes a concern in wafer manufacturing processes since water is a polar molecule and deionized water (~18MOhm) is a good insulator [1, 2].

When working at the nanoscale of microchip production, even low levels of contamination have the capacity to alter the electrical characteristics of the device and affect the reliability of the end product. Operational hygiene has always been an issue due to the sensitivity of semiconductors to contaminants, but the threat of trace metal contamination specifically is significant. This is mainly true for front end processing but, due to the high mobility of many of these contaminants, it remains a threat at all stages of the manufacturing process flow.

Trace metal constituents of elastomer seals can be released as byproducts during erosion of the seal in aggressive plasma or chemical environments that are part of routine process tool operation. Contamination of semiconductor devices by trace metals adversely affects device performance and as linewidths decrease, the allowable levels of metal contamination reduce. This article explores where trace metals come from, the impact they have on the industry and what can be done to reduce the risks.

Background

Semiconductor microchips, which provide inexpensive, fast computing power for electronic devices, are made from millions or even billions of transistors. The transistor is fundamentally an electronic switch that contains no moving parts but uses an applied low voltage to the gate which in turn allows electrons to move from the source to the drain.

The overall chip making process involves many repeating steps to form the transistor at the front end, and subse- quent formation of the back end interconnect including multiple metal and dielectric levels and several etch steps in between. In the process of building these layers, many transistors are created and interconnected. When completed, a single wafer will contain hundreds of identical chips that must pass rigorous testing. The chip is then mounted onto a metal or plastic package that undergoes final testing, ready to be assembled into final products [1,2].

During routine operation, many components within the process tools and ancillary equipment will be subject to wear and abrasion, particularly those components within the process module that are directly exposed to harsh physical and chemical environments. The most critical locations are those where components are exposed to such environments and in proximity to the substrate being processed.

Equipment consumable items that can sometimes be overlooked are elastomer seals or O-rings. These materials have a certain lifetime proportional to the mechanical and chemical properties of the operating environment and the physical constraints of the groove and location. While an elastomer in a critical location may not actually determine the maintenance cycle of the process tool, byproducts and elastomer constituents will be released into the process environment during active operation. Therefore, whatever constitutes the elastomer can contaminate the wafer and this applies equally to the trace metals.

Trace metal contaminants fall broadly into two categories. Alkali metals which include elements such as sodium (Na), potassium (K) and lithium (Li) and heavy metals which include elements such as copper (Cu), iron (Fe), zinc (Zn), titanium (Ti) and chromium (Cr). The effects on the device of such contaminants vary depending on the type of the element. Sodium for example, can readily lose its outer electron to form an ion with charge +1. It can then readily diffuse through the oxide under the influence of an electric field even at room temperature, however; it cannot penetrate the silicon crystal lattice which means that a charge can accumulate at the silicon/silicon dioxide interface. This in turn leads to unpre- dictable voltage threshold shifts and correspondingly random digital outputs from logic circuits.

Additional failure mechanisms include current leakage through the dielectric and reduced dielectric breakdown voltage, degradation of time dependent dielectric breakdown (TDDB), or complete breakdown of the gate [3]. Gettering layers are also no guarantee of eliminating the issue. Phopho- silicate glass (PSG) and borophophosilicate glass (BPSG) layers are often used to getter sodium ions, however, the presence of moisture either through integral process steps or atmospheric absorption can facil- itate the release of trapped mobile ions in the getter [4]. Rather than accumulate at the semiconductor interface, heavy metals tend to diffuse through the semiconductor, where they effectively create energy states in the bandgap of the semiconductor causing changes in carrier lifetime or the diffusion length [5].

Consumer demands for faster, more powerful and portable technology with greater functionality is a key factor driving the semiconductor manufacturing industry.

Although the part of Moore’s law that refers to shrinking technology remains largely intact, the pressure on cost reduction is rising throughout the whole value chain [6]. Reduced device dimensions and gate thickness leads to devices that become more sensitive to a number of factors including trace metal contamination.

It is clear that such contamination leads to unstable device performance, yield loss, device degradation with increased risk of reliability failures, potentially costing the fab in lost time, loss of revenue and wafer production capacity.

Purity in elastomers

When choosing elastomer materials or seals for critical applications, device manufacturers must ensure that they select appropriate materials with ultra-low levels of trace metals, in order to avoid contamination and device degradation. Manufacturers must also decide on the material in accordance with the location in the tool and the chemistry involved. Critical locations where the elastomer is in contact with the chemistry or process media, where degradation takes place, and where the byproducts of this degradation can be transported to the wafer, require the highest quality seal material in order to avoid contaminating the device. The sealing product must precisely fit the characteristics of the operating equipment.

There is often a large choice of products for any one particular application and ‘semiconductor compatibility’ is often taken for granted especially in critical applications. However, not all elastomer materials are equal when it comes to the level of undesirable contaminants. For many device applications, it is no longer adequate to measure contamination at the parts per million (PPM) level. When analyzing trace metal levels in elastomer materials, vapor phase decomposition (VPD) combined with inductively coupled plasma mass spectrometry (ICPMS) yields data down to parts per billion [7]. A number of different elastomer materials have been analyzed by an independent test laboratory in order to quantitatively determine the amount of trace metal within each sample. The materials analyzed include the leading elastomer brands and the results are graphically represented in FIGURE 1. It should be particularly noted that In order to accommodate all the samples tested, a log scale was used.

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The results show that the elastomers that achieved the lowest trace metal content of all materials tested were entirely organic perfluoroelastomers, or FFKMs. The cleanest fluoroelastomer or FKM material was found to be Nanofluor Y75N, again a fully organic highly fluori-nated elastomer. FIGURES 2, 3 and 4 below illustrate the individual levels for several of the key contaminants that should be avoided for three of the cleanest materials tested.

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Conclusion

It is clear that the seal lifetime is not the only factor that should be considered when making elastomer choices for specific applications. Elastomer or seal wear in key tool locations during normal operation exposes the wafer to the degradation byproducts of the elastomer material, and therefore also the impurities contained within the elastomer, such as trace metals. FFKM elastomers are particularly suited to the most critical applications, and the harsh environments presented by higher temper- atures, aggressive wet chemical and plasma processes. The more aggressive the environment and the more sensitive the device, the greater is the need to consider the contaminating degradation byproducts of the system components.

Contamination ultimately results in loss of yield, increased cost, or loss of reputation. The use of high purity components becomes a preventative measure, guarding against costly transistor damage or increased risk of poor reliability. Elastomer materials that contain only ultra-low levels of metallic contaminants are ideal for manufacturers of devices at advanced technology nodes and all fabs wishing to minimize the risk of random changes to electrical characteristics and reliability failures.

For further information about how to integrate high performance elastomer seals into your production equipment, and to understand the benefits of customized sealing solutions please contact the author at [email protected].

IRT Nanoelec, an R&D consortium focused on information and communication technologies (ICT) using micro- and nanoelectronics, today announced the first co-integration of a III-V/silicon laser and silicon Mach Zehnder modulator demonstrating 25 Gbps transmission on a single channel. This transmission rate usually is achieved using an external source, over a 10 km single-mode fiber.

Current interconnect technologies, which use micro-optics integration to assemble a discrete laser and a silicon photonic circuit, will soon reach their limits and new, different solutions will have to be found to handle increasing traffic.

Integrating photonics capabilities on silicon chips is replacing currently established technologies, vastly increasing bandwidth, density and reliability, while dramatically reducing energy consumption. In the age of photonics-on-silicon, data transmission will be measured in terabits per second.

“Jointly obtained by STMicroelectronics and Leti in the frame of the IRT Nanoelec cooperation, these results, especially fabricating the laser directly on silicon, demonstrate IRT Nanoelec’s worldwide leadership in III/V-on-silicon integration to achieve high-data-rate fiber-optic modules,” said Stéphane Bernabé, project manager. “IRT Nanoelec and its partners on this project, Leti, STMicroelectronics, Samtec and Mentor Graphics, are paving the way to integrating this technology in next-generation transceivers for optical data links.”

To achieve these recent results, silicon photonics circuits integrating the modulator were processed first on a 200mm SOI wafer, although 300mm wafers also could be used in the near future. Then, a two-inch wafer of III-V material was directly bonded on the wafer. In the third step, the hybrid wafer was processed using conventional semiconductor and/or MEMS process steps to produce an integrated modulator-and-laser transmitter.

IRT Nanoelec launched its silicon photonics program in 2012, with core members Mentor Graphics, STMicroelectronics and CNRS. The program brings together, under one roof, the expertise and equipment needed to address the entire photonics-on-silicon value chain.

Leti, which will attend the Optical Fiber Communication Conference in Anaheim, Calif., March 20-24, and have a booth at the Exhibition Hall (3759), is a major innovation player in III-V/silicon integration for high-data-rate fiber optics modules.

By Douglas G. Sutherland and David W. Price

Author’s Note: This is the last in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications. Within this article we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

In the eighth installment1 in this series, “The Tyranny of Numbers,” we discussed the trend of increasing process steps—the number of steps is expected to double between the 20nm and 10nm nodes—and the impact that those additional steps will have on final yield. In addition to impacting yield, the increased complexity of the process flow will also increase production costs and cycle time. As these trends unfold, managing costs and cycle time will become increasingly important to fab operations.

The tenth fundamental truth of process control for the semiconductor IC industry is:

Adding Process Control Reduces Production Costs and Cycle Time

Instrumental to having an efficient, low-cost fab is the ability to collect meaningful information about the process in a timely fashion. Process control tools (metrology and inspection) are the eyes and ears of the fab in that they provide insight into what’s working and what’s not: they are an investment in “process information.” In a 2007 paper2 the National Institute of Standards and Technology (NIST) estimated that the average return on investment for metrology alone was 300 percent.

Previous articles in this series have illustrated how process control can reduce costs by reducing the scrap and raw material costs associated with lost yield and reliability3 failures. Similarly, improving yield reduces the environmental footprint of fab operations per good die out.4 In this article, we will examine two other elements of cost reduction and factory efficiency enabled by process control:

  1. Process equipment re-use from node-to-node
  2. Improved net cycle time

Equipment Re-Use

The single biggest component of cost in a modern fab is capital depreciation. It can vary from company to company, but typically wafer fab capital equipment is depreciated at 20 percent per year over the course of five years. If you can extend the life of a piece of equipment beyond the point where it is fully depreciated you are essentially getting that tool for free. If you can find a way to re-use an entire group of process tools (scanners, etchers, etc.) the savings could easily be measured in tens or even hundreds of millions of dollars.

Ultimately, a process tool must meet the technical specifications that are demanded by the manufacturing process in which it is used. However, in cases where the tool’s capability is marginal, its lifetime can be extended by closer monitoring—using existing metrology or inspection tools to keep the tool operating within the required process specifications. Performing more frequent process tool qualifications can help improve matching and ensure that a tool does not drift out of spec. For stable feed-back and feed-forward schemes, having more in-line inspections provides better averaging and allows for better control of the actual process. In these situations, process control is helping to extend the life of existing process tools—adding process control in this context can actually save money.

The Process Capability Index (Cpk) is a metric that measures how well the natural variation of a process fits within the spec limits. For a centered process with a symmetric distribution the Cpk is given by equation 1,

Cpk = (USL – LSL) / 6σ                             Eq. 1

where USL and LSL are the upper and lower spec limits respectively and s is the standard deviation of the process. If the Cpk value is greater than one, the process is considered capable. Cpk values less than one indicate that the process is not capable.

Consider an etch process step where the Cpk of the CD measurement is exactly equal to one (i.e., the step is marginally capable in that the upper and lower spec limits are both three standard deviations from the mean). The marginal capability could be the fault of the previous photo step, the etch step or both. Either way it is an expensive proposition to upgrade either tool set to improve the Cpk—the capability —of the process.

Often the capability of the process can be improved by implementing a data feed-forward scheme—using additional metrology to fully characterize the process at one step (e.g., photo) and then feeding that information forward to adjust parameters at etch to effectively customize the process conditions for each lot or wafer. Figure 1 below shows an example Statistical Process Control (SPC) chart of the after-etch CD with and without feed-forward.

Figure 1. Left: SPC Chart of etch CD without feed forward (Cpk=1.0). Right: SPC Chart of etch CD with feed forward (Cpk=1.3)

Figure 1. Left: SPC Chart of etch CD without feed forward (Cpk=1.0). Right: SPC Chart of etch CD with feed forward (Cpk=1.3)

Feed-back and feed-forward schemes can be used to extend the useful lifetime of process tools by effectively increasing the process window in which they operate. CD measurements that are slightly off target at photo can be brought back on target by using that information to adjust the etch bias at the etch process step. 

Cycle Time

Cycle time is another very important production metric. We will give a more detailed account of cycle time in an upcoming paper but would like to touch briefly on the counter-intuitive relationship between cycle time and process control.

Any source of variability that prevents lots from moving through the fab in lock-step fashion will increase the cycle time. Adding inspection steps will add cycle time to those lots that get inspected but due to sampling (not every lot gets inspected) it will have a much smaller impact on the average. When an excursion does occur, comparatively few process tools will have to be put down (because the inspection points are closer together) and the module owner will be able to isolate the problem much sooner. The total disruption to the fab (the variability) will be reduced and the cycle time of all lots will be improved. This counter-intuitive concept has been demonstrated by several fabs that have both added inspection steps and reduced cycle time simultaneously.

To summarize, adding process control steps contribute to fab efficiency on several levels (figure 2): increasing baseline yield, extending the useful life of existing process tools, limiting the duration of excursions, and reducing cycle time.

Figure 2. The cascading benefits of process control.

Figure 2. The cascading benefits of process control.

As we conclude this series on the 10 fundamental truths of process control1,3,5-11, we thank you for reading. We hope that these articles have provided deeper insight into the value of process control and the base knowledge for successful implementation of process control in IC fabrication. We look forward to exploring additional aspects of process control in future Process Watch articles throughout the coming months.

References:

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Cadence Design Systems, Inc. today announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10nm FinFET process. Cadence and TSMC are also continuing to collaborate on the advancement of 7nm technologies and have completed tools certification and the delivery of the latest Process Design Kit (PDK) for mutual customers to initiate early design starts based on the most current version of the DRM and SPICE model.

The Cadence custom/analog, digital and signoff tools have been validated by TSMC on high-performance reference designs, providing customers with innovative methodologies to achieve TSMC’s 7nm and 10nm process benefits of higher performance, lower power consumption, and smaller area. The certified Cadence tools include:

  • Innovus Implementation System: Enables increased capacity and reduced turnaround time while supporting TSMC’s 10nm design requirements, such as floorplanning, placement and routing with integrated color-/pin-access/variability-aware timing closure, and clock tree and power optimization
  • Quantus QRC Extraction Solution: Delivers on TSMC accuracy requirements for all 10nm modeling features and offers multi-patterning, multi-coloring and built-in 3D extraction capability
  • Tempus Timing Signoff Solution: Provides integrated, advanced process calculation of delay and signal integrity effects, with static timing analysis (STA) while achieving TSMC’s rigorous accuracy standards, including those at low- and ultra-low voltage operating conditions
  • Voltus IC Power Integrity Solution: Cell-level power integrity tool that supports comprehensive electromigration and IR-drop (EM/IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy
  • Voltus-Fi Custom Power Integrity Solution: SPICE-level accurate tool that supports comprehensive EM/IR design rules and requirements to analyze and signoff analog, memory and custom digital IP blocks down to the transistor device level
  • Virtuoso custom IC advanced-node platform: Provides the innovative in-design to signoff flows, integrating signoff-quality electrical and physical design checking that is highly correlated to the Cadence TSMC-certified signoff platforms
  • Spectre simulation platform: Spectre Circuit Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre eXtensive Partitioning Simulator (XPS) deliver fast and accurate circuit simulation with full support for advanced-node device models with self-heating and reliability effects
  • Physical Verification System: Includes advanced technologies and rule decks to support design rule checks (DRC), layout versus schematic (LVS), advanced metal fill, yield-scoring, voltage-dependent checks, pattern-matching, and in-design signoff
  • Litho Electrical Analyzer: Allows layout-dependent effect- (LDE-) aware re-simulation, layout analysis, matching constraint checking, reporting on LDE contributions, and the generation of fixing guidelines from partial layout to accelerate 10nm analog design convergence

In addition to the tools certified for TSMC’s 10nm process, the Virtuoso Liberate Characterization Solution and the Virtuoso Variety Statistical Characterization Solution have been validated to deliver accurate Liberty libraries including advanced timing, noise and power models utilizing innovative new methods needed for Liberty Variation Format (LVF) models to enable process variation signoff and electromigration models for ultra-low-power applications. Libraries characterized by these two solutions were used in the 10nm v1.0 STA tool certification.

Cadence and TSMC also validated a custom/mixed-signal design reference flow for the 10nm process. The flow includes the following key capabilities for improving design productivity:

  • Advanced simulation capabilities including variation analysis, EM/IR analysis and self-heating impact: Helps designers create robust, reliable and high-yield designs
  • Color-aware custom layout including rapid prototyping, automated routing and electrically and LDE-aware design: Provides a high level of automation in exploring the impact of physical effects on circuit performance
  • Virtuoso Layout Suite for Electrically Aware Design: Provides innovative in-design electromigration routing and parasitic resistor/capacitor (RC) checks that understand colored design, allowing design teams to achieve faster time to market with better circuit performance

“The certification of our tools enables systems and semiconductor companies to deliver advanced-node designs to market faster for mobile phones, tablets, application processors and high performance computing applications,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Through our deep collaboration with TSMC, we are actively working with customers on 10nm designs while also advancing the 7nm design process to enable customers to maximize the benefits of these leading-edge process nodes.”

“We worked closely with Cadence to certify its set of tools and deliver digital and custom/mixed-signal reference flows that can enable customers to reduce iterations and improve predictability when creating 7nm designs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “This marks the production release of our 10nm technology design support.”

Semico’s Inflection Point Indicator is a model developed by Semico Research, which has a history of accurately predicting semiconductor revenue inflection points four quarters in advance. After analyzing current trends, Semico announced this model indicates the semiconductor industry is repeating the pattern from 2011-2012, albeit at a muted level. Just in the past 4-5 years, the major end markets served by the semiconductor industry–tablets, notebooks, smartphones–have matured, causing growth rates to slow. On top of that, compared to 2012, most of the world’s economies are forecast to be weaker in 2016, with the exception of India. Finally, DRAM prices are expected to be weaker this year, compared to 2012. The positive growth in 2013-2014 was primarily due to the memory shortage and the subsequent rising prices.

Average selling prices (ASPs) in January recovered on lower revenues, which were down 6% year over year. Although ASPs rose 4.0% in January, they are still historically low.

Semico president Jim Feldhan commented, “In the past 8 months, the industry has seen ASPs in the $0.41 range 5 times. One has to go back to May 2009 to find a lower price, and 2009 was not a good year!”

semi ipi

 

The IPI Report is Semico’s most popular report series that accurately predicts semiconductor revenue inflection points four quarters in advance.

SEMI, the global industry association for companies that supply manufacturing technology and materials to the world’s chip makers, today reported that worldwide sales of semiconductor manufacturing equipment totaled $36.53 billion in 2015, representing a year-over-year decrease of 3 percent. 2015 total equipment bookings were 5 percent lower than in 2014. The data are available in the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) Report, now available from SEMI.

Compiled from data submitted by members of SEMI and the Semiconductor Equipment Association of Japan (SEAJ), the Worldwide SEMS Report is a summary of the monthly billings and bookings figures for the global semiconductor equipment industry. The report, which includes data for seven major semiconductor producing regions and 24 product categories, shows worldwide billings totaled $36.53 billion in 2015, compared to $37.50 billion in sales posted in 2015. Categories cover wafer processing, assembly and packaging, test, and other front-end equipment. Other front-end includes mask/reticle manufacturing, wafer manufacturing, and fab facilities equipment.

Spending rates increased for Taiwan, Korea, Japan, and China, while the new equipment markets in North America, Rest of World, and Europe contracted. Taiwan remained the largest market for new semiconductor equipment for the fourth year in a row with $9.64 billion in equipment sales. The expanding markets in South Korea and Japan surpassed the North American market, to claim the second and third largest markets, respectively, while North America fell to fourth place at $5.12 billion. The China market remained larger than the Rest of World and European markets.

The global other front end segment increased 16 percent; the wafer processing equipment market segment decreased 2 percent; total test equipment sales decreased 6 percent; and the assembly and packaging segment decreased 18 percent.

Semiconductor Capital Equipment Market by World Region (2014-2015)

2015

2014

% Change
Taiwan

9.64

9.41

2%
South Korea

7.47

6.84

9%
Japan

5.49

4.18

31%
North America

5.12

8.16

-37%
China

4.90

4.37

12%
Rest of World

1.97

2.15

-9%
Europe

1.94

2.38

-19%
Total

36.53

37.50

-3%

Source: SEMI/SEAJ March 2016; Note: Figures may not add due to rounding.

Intel Corporation this week recognized 26 companies with its 2015 Preferred Quality Supplier (PQS) award, which celebrates exceptional performance and continuous pursuit of excellence. The 2015 recipients exhibited extraordinary achievements across key focus areas of quality, cost, availability, technology, customer service, labor and ethics systems, and environmental sustainability.

Along with the distinguished PQS award, Intel recognized one supplier with the Supplier Achievement Award, which is a specific recognition for outstanding accomplishments in one or more key performance areas. The company also presented eight companies with its highest honor, the Supplier Continuous Quality Improvement (SCQI) award.

Award winners will be honored in a ceremony last night in Santa Clara, California. The theme of the ceremony is “Delivering the Future Together” as this dedicated group of suppliers has helped Intel push the boundaries of smart and connected technology and brings innovative products to market quickly.

“Intel is honored to recognize our Preferred Quality Suppliers for their sustained excellence in 2015 to deliver leading-edge technology with world-class cost, velocity and sustainability,” said Robert Bruck, corporate vice president and general manager of Global Supply Management at Intel. “Close collaboration and superb execution by these suppliers remains one of the crucial factors in enabling Intel to extend our industry-leading silicon, packaging and test technologies, and is a clear demonstration of leadership in their respective markets.”

“The winners of the Preferred Quality Supplier and Achievement Award are an integral part of Intel’s success,” added Jacklyn Sturm, vice president, Technology and Manufacturing Group and general manager of Global Supply Management at Intel. “The absolute focus and rigorous attention to continuous improvement and time-to-market innovation are a testament to their world-class support, providing Intel with a critical part of the foundation to be a leader in computing innovations.”

The PQS award is part of Intel’s Supplier Continuous Quality Improvement (SCQI) program, which encourages suppliers to innovate and continually improve. To qualify for PQS status, suppliers must exceed high expectations and uncompromising performance goals while scoring at least 80 percent on an integrated report card that assesses performance throughout the year. Suppliers must also achieve 80 percent or greater on a challenging continuous improvement plan and demonstrate solid quality and business systems.

Additional information about the SCQI program is available at www.intel.com/go/quality.

The PQS winners provide Intel with the following products or services:

  • Amkor Technology Inc.: semiconductor advanced packaging design, assembly and test services
  • ASM International: front-end equipment supplier for atomic layer deposit (ALD), plasma-enhanced ALD, metal gate and diffusion
  • Daewon Semiconductor Packaging Industrial Co. Ltd.: plastic injection molded tray (PIMT) media for bare die automation, substrate transport, device assembly and test, final shipping and storage, bare die tape and reel (BDTR) media for bare die transport
  • Daifuku: automated material handling systems
  • DISCO Corporation: precision cutting, grinding and polishing machines
  • EBARA Corporation: chemical mechanical polishers, plating systems, and dry vacuum pumps and abatement systems
  • Edwards Vacuum LLC: vacuum system products and abatement solutions
  • Fujimi Corporation: chemical mechanical planarization and silicon polishing slurries
  • Hitachi High-Technologies Corporation: dry etching, ashing, metrology and advanced packaging systems
  • Hitachi Kokusai Electric Inc.: batch processing and single wafer processing systems
  • JLL: facilities management
  • KLA-Tencor Corporation: process control and yield management solutions
  • Lam Research Corporation: fab capital equipment
  • Mitsubishi Gas Chemical Company Inc.: high-purity peroxide and custom back-end cleans
  • ModusLink Global Solutions Inc.: channel box CPU for Penang, Shanghai and Miami, and finished goods warehouse distribution for Miami
  • Murata Machinery Ltd.: automated material handling systems, hoist vehicles and stockers
  • The PEER Group Inc.: automation software and services
  • SCREEN Semiconductor Solutions Co. Ltd.: wafer cleaning and anneal equipment and services for semiconductor manufacturing
  • Shin Etsu Chemical Co., Ltd: silicon wafers, advanced photoresists, photomask blanks, and thermal conductive materials.
  • Shinko Electric Industries Co. Ltd.: plastic laminated packages and heat spreaders
  • Siltronic AG: polished and epitaxial silicon wafers
  • Tokyo Ohka Kogyo Co. Ltd: high-purity photo resists, developers, cleaning solutions and supporting chemistries
  • Tosoh SMD, Inc.: sputtering targets
  • Tosoh Quartz Inc.: quartzware for semiconductor wafer processing equipment
  • VWR: products, services and solutions to laboratory and production facilities
  • Veolia North America: waste management services

The Supplier Achievement Award winner is:

  • Nanium: outsourced semiconductor packaging, assembly and test provider (recognizing extraordinary results in product availability)