Category Archives: Wafer Processing

Perovskite solar cells (PSCs) can offer high light-conversion efficiency with low manufacturing costs. But to be commercially viable, perovskite films must also be durable and not degrade under solar light over time. EPFL scientists have now greatly improved the operational stability of PSCs, retaining more than 95% of their initial efficiencies of over 20% under full sunlight illumination at 60oC for more than 1000 hours. The breakthrough, which marks the highest stability for perovskite solar cells, is published in Science.

Challenges of stability

Conventional silicon solar cells have reached a point of maturation, with efficiencies plateauing around 25% and problems of high-cost manufacturing, heavyweight, and rigidity has remained largely unresolved. On the contrary, a relatively new photovoltaic technology based on perovskite solar cells has already achieved more than 22% efficiency.

Given the vast chemical versatility, and the low-cost processability of perovskite materials, the PSCs hold the promise to lead the future of photovoltaic technology by offering cheap, light weight and highly efficient solar cells. But until now, only highly expensive, prototype organic hole-transporting materials (HTMs,selectively transporting positive charges in a solar cell) have been able to achieve power-conversion efficiencies over 20%. And by virtue of their ingredients, these hole-transporting materials adversely affect the long-term operational stability of the PSC.

Therefore, investigating cheap and stable hole transporters that produce equally high efficiencies is in great demand to enable large-scale deployment of perovskite solar cells. Among various inorganic HTMs, cuprous thiocyanate (CuSCN) stands out as a stable, efficient and cheap candidate ($0.5/gr versus $500 /gr for the commonly used spiro-OMeTAD). But previous attempts to use CuSCN as a hole transporter in perovskite solar cells have yielded only moderately stabilized efficiencies and poor device stability, due to problems associated with depositing a high-quality CuSCN layer atop of the perovskite film, as wells as the chemical instability of the CuSCN layer when integrated into a perovskite solar cell.

A stable solution

Now, researchers at Michael Grätzel’s lab at EPFL, in a project led by postdocs Neha Arora and M. Ibrahim Dar, have introduced two new concepts that overcome the major shortcomings of CuSCN-based perovskite solar cells. First, they developed a simple dynamic solution-based method for depositing highly conformal, 60-nm thick CuSCN layers that allows the fabrication of perovskite solar cells with stabilized power-conversion efficiencies exceeding 20%. This is comparable to the efficiencies of the best performing, state-of-the-art spiro-OMeTAD-based perovskite solar cells.

Second, the scientists introduced a thin spacer layer of reduced graphene oxide between the CuSCN and a gold layer. This innovation allowed the perovskite solar cells to achieve excellent operational stability, retaining over 95% of their initial efficiency while operating at a maximum power point for 1000 hours under full-sun illumination at 60 °C. This surpasses even the stability of organic HTM-based perovskite solar cells that are heavily researched and have recently dominated the field.

The researchers also discovered that the instability of the perovskite devices originates from the degradation of CuSCN/gold contact during the solar cell’s operation.

“This is a major breakthrough in perovskite solar-cell research and will pave the way for large-scale commercial deployment of this very promising new photovoltaic technology,” says Michael Grätzel. “It will benefit the numerous scientists in the field that have been intensively searching for a material that could replace the currently used, prohibitively expensive organic hole-transporters,” adds M. Ibrahim Dar.

OEM Group announced today a Post-Dice Clean solution on the proven Cintillio™ Batch Spray platform following plasma and laser dicing methods. Designed specifically to remove residue and particles left behind from these dicing methods, OEM Group’s Cintillio™ SST (Spray Solvent Tool) and Cintillio™ Eco-Clean systems utilize their patented Enhanced Spray Technology (EST) to deliver process improvement through uniform media flow with a nozzle-per-wafer concept ensuring uniform flow and increased rinse efficiency.

After wafers are singulated prior to “pick and place,” the conventional method of cleaning is by water rinsing; however, some singulation methods, particularly plasma and laser, may leave behind residues that water cannot clean. Slag, polymers, and other residues impede device performance and may cause corrosion or affect downstream processes. The Cintillio™ post-dice clean process successfully removes these residues to maintain final device performance. Chris Forgey, CTO for OEM Group says, “We’re pleased to leverage our patented Ozone process specifically for post dice clean applications, delivering value and superior process capability for this specific application.”

Along with the patented Enhanced Spray Technology (EST), both platforms adapt wafer carriers and rotors to hold multiple “diced wafer-on-tape-on-frame” substrates, delivering greater throughput, reduced chemical utilization, space efficient footprint, and excellent overall performance. According to OEM Group Applications Lab Manager, Joshua Levinson, Ph.D., “Any device manufacturer who performs back-end processing of wafers and who employs wafer singulation to create diced substrates will benefit from our solutions. Batch processing also reduces the number of cleaning tools required in a fab and lowers overall cost of ownership, waste generation, and DI water usage.”

With global headquarters in metro Phoenix, Arizona and additional sites throughout the North America, Europe, Japan and Asia, OEM Group, LLC is a semiconductor capital equipment manufacturer and innovator in new and remanufactured 75mm–200mm tools and services.

Solar-Tectic LLC (“ST”) announced today that a patent application for a method of making III-V thin-film tandem solar cells with high performance has been allowed by the US Patent and Trademark Office. The patent, the first ever for a thin III-V layer on crystalline silicon thin-film, covers group III-V elements such as Gallium Arsenide (GaAs), and Indium Gallium Phosphide (InGaP), for the top layer, as well as all inorganic materials, including, silicon, germanium, etc., for the bottom layer.  Group III-V compounds such as Gallium Arsenide (GaAs) are proven photovoltaic materials with high efficiencies but until now have been cost prohibitive because high quality III-V material such as GaAs is expensive. Moreover, the cost of substrates on which to grow III-V materials, such as germanium, which is known to be an ideal material, has kept the technology from market entry. In the breakthrough technology here, ultra-thin films of III-V materials and silicon (or germanium) replace expensive, thicker wafers thereby lowering the costs dramatically. The inventor is Ashok Chaudhari, CEO of Solar-Tectic LLC.

III-V tandem (or multi-junction) cells built on wafers such as silicon are currently being developed in labs, with high efficiencies of around ~30%.  The highest dual-junction cell efficiency (32.8%) came from a tandem cell that stacked a layer of gallium arsenide (GaAs) atop crystalline silicon. Manufacturing costs are expensive especially if a germanium wafer is used as the bottom material in the two layer tandem structure.  In order to compete with low cost silicon wafer technology which is 90% of the global solar panel market, efficiencies must not only be as high as silicon wafers or greater (21.7% and 26.7% are lab records for poly- and monocrystalline silicon wafer cells, respectively), but manufacturing costs must also be lower. This is achievable in the Solar-Tectic LLC patented technology, which uses common industrial manufacturing processes and at low temperature. There is no wafer involved which saves material and energy; instead a thin film allows for precise control of growth parameters. A glass substrate instead of wafer also allows for a bifacial cell design for increased efficiency. A cost effective ~30% efficient III-V tandem solar cell in today’s market would revolutionize the solar energy industry by dramatically reducing the balance of system (BoS) costs, and thereby reduce the need for fossil fuel generated electricity. Silicon wafer technology based on polycrystalline or monocrystalline silicon could become obsolete.

Importantly, the entire patented process for the Solar-Tectic LLC III-V tandem cell can be environmentally friendly since non-toxic metals can be used to deposit the crystalline thin-film materials for both the bottom layer in the tandem configuration as well as in the top, III-V, layer.

The technology also has great promise for LED manufacturing using for example Gallium Nitride.

A “Tandem Series” of solar cell technologies has been launched by Solar-Tectic LLC, which includes a variety of different proven semiconductor photovoltaic materials for the top layer on silicon and/or germanium bottom layers. Recently patents for a tin perovskite and germanium perovskite thin-film tandem solar cell were also granted.

The ITC ruling on September 22 means that it is likely that tariffs will be imposed on crystalline silicon wafers sold in the US. These tariffs will not apply to thin-film solar cell technology, such as ST’s.

Band gaps, made to order


September 28, 2017

Control is a constant challenge for materials scientists, who are always seeking the perfect material — and the perfect way of treating it — to induce exactly the right electronic or optical activity required for a given application.

One key challenge to modulating activity in a semiconductor is controlling its band gap. When a material is excited with energy, say, a light pulse, the wider its band gap, the shorter the wavelength of the light it emits. The narrower the band gap, the longer the wavelength.

As electronics and the devices that incorporate them — smartphones, laptops and the like — have become smaller and smaller, the semiconductor transistors that power them have shrunk to the point of being not much larger than an atom. They can’t get much smaller. To overcome this limitation, researchers are seeking ways to harness the unique characteristics of nanoscale atomic cluster arrays — known as quantum dot superlattices — for building next generation electronics such as large-scale quantum information systems. In the quantum realm, precision is even more important.

New research conducted by UC Santa Barbara’s Department of Electrical and Computer Engineering reveals a major advance in precision superlattices materials. The findings by Professor Kaustav Banerjee, his Ph.D. students Xuejun Xie, Jiahao Kang and Wei Cao, postdoctoral fellow Jae Hwan Chu and collaborators at Rice University appear in the journal Nature Scientific Reports.

Their team’s research uses a focused electron beam to fabricate a large-scale quantum dot superlattice on which each quantum dot has a specific pre-determined size positioned at a precise location on an atomically thin sheet of two-dimensional (2-D) semiconductor molybdenum disulphide (MoS2). When the focused electron beam interacts with the MoS2 monolayer, it turns that area — which is on the order of a nanometer in diameter — from semiconducting to metallic. The quantum dots can be placed less than four nanometers apart, so that they become an artificial crystal — essentially a new 2-D material where the band gap can be specified to order, from 1.8 to 1.4 electron volts (eV).

This is the first time that scientists have created a large-area 2-D superlattice — nanoscale atomic clusters in an ordered grid — on an atomically thin material on which both the size and location of quantum dots are precisely controlled. The process not only creates several quantum dots, but can also be applied directly to large-scale fabrication of 2-D quantum dot superlattices. “We can, therefore, change the overall properties of the 2-D crystal,” Banerjee said.

Each quantum dot acts as a quantum well, where electron-hole activity occurs, and all of the dots in the grid are close enough to each other to ensure interactions. The researchers can vary the spacing and size of the dots to vary the band gap, which determines the wavelength of light it emits.

“Using this technique, we can engineer the band gap to match the application,” Banerjee said. Quantum dot superlattices have been widely investigated for creating materials with tunable band gaps but all were made using “bottom-up” methods in which atoms naturally and spontaneously combine to form a macro-object. But those methods make it inherently difficult to design the lattice structure as desired and, thus, to achieve optimal performance.

As an example, depending on conditions, combining carbon atoms yields only two results in the bulk (or 3-D) form: graphite or diamond. These cannot be ‘tuned’ and so cannot make anything in between. But when atoms can be precisely positioned, the material can be designed with desired characteristics.

“Our approach overcomes the problems of randomness and proximity, enabling control of the band gap and all the other characteristics you might want the material to have — with a high level of precision,” Xie said. “This is a new way to make materials, and it will have many uses, particularly in quantum computing and communication applications. The dots on the superlattice are so close to each other that the electrons are coupled, an important requirement for quantum computing.”

The quantum dot is theoretically an artificial “atom.” The developed technique makes such design and “tuning” possible by enabling top-down control of the size and the position of the artificial atoms at large scale.

To demonstrate the level of control achieved, the authors produced an image of “UCSB” spelled out in a grid of quantum dots. By using different doses from the electron beam, they were able to cause different areas of the university’s initials to light up at different wavelengths.

“When you change the dose of the electron beam, you can change the size of the quantum dot in the local region, and once you do that, you can control the band gap of the 2-D material,” Banerjee explained. “If you say you want a band gap of 1.6 eV, I can give it to you. If you want 1.5 eV, I can do that, too, starting with the same material.”

This demonstration of tunable direct band gap could usher a new generation of light-emitting devices for photonics applications.

Reno Sub-Systems (Reno), a developer of high-performance radio frequency (RF) matching networks, RF power generators and gas flow management systems for semiconductor manufacturing, today announced it has closed its Series C funding. Samsung Venture Investment Corporation led the round. New investors Samsung Venture Investment Corp., Hitachi High-Technologies Corporation and SK hynix all join Reno’s premier list of strategic investors. Existing investors Intel Capital, Lam Research and MKS Instruments also participated in this funding round.

“Our list of strategic investors now includes the venture arms of three of the top five largest semiconductor manufacturers, two out of four of the largest etch tool providers, and a key subsystems supplier,” said Bob MacKnight, CEO of Reno Sub-Systems. “Our holistic approach to precision subsystem process control across RF as well as flow technologies offers clear differentiation from competitive approaches. Our new investors are motivated to participate to secure access to our innovative technologies, to enhance their manufacturing operations or product offerings.”

“We saw high value in Reno’s technology, so it only made sense for us to pursue an investment,” said Dr. Dong-Su Kim, vice president of Samsung Venture Investment Corp.

“The new capabilities that Reno’s subsystems provide will add to our competitive strengths,” said Craig Kerkove, president & CEO of Hitachi High-Technologies America.

“Greater precision and repeatability of processing are key to future device geometries,” said Heejin Chung, head of SK hynix’s Venture Investment. “Reno’s subsystems can help us achieve that.”

The additional funding will support continued development of the technology to enable leading-edge silicon manufacturing technology nodes in high-volume production. “The C-round will allow us to support our rapidly growing number of deployments and enable high-volume manufacturing of our systems to support our recent platform wins,” said MacKnight.

The company also announced that it has secured several additional platform design wins for its Electronically Variable Capacitor (EVC™) impedance matching networks and has been qualified by a leading OEM.

Understanding the impact of valve flow coefficient (Cv) in fluid systems for microelectronics manufacturing

BY STEPHANE DOMY, Saint-Gobain Performance Plastics,

When scaling up, or down, a high-purity liquid installation – many complex factors need to be considered from ensuring the integrity of the transported product to the cleanliness of the environment for both the safety of the process and the operator [1]. In my 15 years working in the semiconductor fluid handling component industry, I’ve learned that the Cv is a bit misunderstood. Given the Cv formula can be used for any flow component in a fluid line, most are familiar with it, yet few consider how it relates to their specific installation. Therefore, this article will focus on factors that pertain to achieving a specific flow performance and specifically the flow coefficient (Cv) as it relates to valves.

Cv empirical explanation and more

As we know, when working on a turbulent flow the Cv formula is: Cv= Q√(SG / ∆P) where Q is the flow going through the valve in gallons per minute (GPM), SG is the specific gravity of the fluid and ∆P is the pressure drop in PSI through the component. In the semiconductor industry, due to the low velocity of the transported fluid the high purity chemistry and slurries are mostly in a semi–turbulent state or a laminar state. Yet you’ll notice there is not a single link to the viscosity of the transported product in the Cv formula. This is significant given the viscosity directly impacts the Cv value when the flow is in a semi-turbulent or laminar mode. Consider that if you calculate the pressure drop in your system with the formula above you could end up with a result that is 4 to 5 times lower. No doubt this inaccuracy can cause significant issues in your installation.

To take this further, let’s analyze how pressure drop based on flow evolves through a valve by comparing a Saint-Gobain Furon® Q-Valve (1⁄2” inner flow path and 1⁄2” pipe connection) to a standard semiconductor industry valve of the same size. The Saint-Gobain valve, which meets the requirements of the semiconductor industry (metal free, 100% fluoropolymer flow path and so on), has a Cv of 3.5 – one of the best for its dimensions. To ease the calculation, we will use deionized (DI) water, which will free us of the specific gravity or impact of the viscosity if we are not in the right state.

As we can see on the graph in FIGURE 1, at a normal flow rate used in micro-e for 1⁄2” 5 to 10 lpm; the pressure drop difference between a standard valve and a Saint-Gobain valve is in the range of 0.1 to 0.3 PSI. At first glance, this does not appear to be much. However, let’s factor in a viscous product and that you have a number of these lines in your flow line — now the numbers start to accumulate. And by moving from a standard valve to a Saint-Gobain valve, as described above, you start to see a significant difference in pressure drop, which could occur across your installation. That being said, up to a certain limit (defined by another component in your installation, such as your pump pressure capability or some more delicate device) an “easy” counter is to increase the pressure through put of your pump but it is at the expense of wasting energy and adding the potential for additional shearing or particle generation in your critical fluid. Now that we have reviewed, the impact of the Cv on our flow and how this could impact our installation, let’s see what can potentially impact the Cv.

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Design impact on Cv and resulting trade-off

The first impact that may come to mind is a larger orifice – and it’s correct. The size of the orifice can benefit flow through and directly relates to the volume of your valve. However there are trade-offs for this improved Cv. The first is cost increase. A higher volume requires a larger valve, which can cost up to 50% more than the initial valve due to specific material and process requirements. Additionally, as highlighted in “Design Impact for Fluid Components” by increasing the size of the component (due to the specific micro-e material requirements), you could lose pressure rating performance [1]. Also when increasing the inner volume of your valve, you potentially increase volume retention as well as particle generation, given that using larger actuation systems results in more points of contact and creates a hub for generating particles. Another possible drawback is significant velocity loss, but that will have to be addressed in another article. The critical point to be taken here is the importance of choosing the right size orifice – too small and flow can be restricted too much and too big and you may end up paying for other problems.

Another potential impact to Cv is the difference in valve technology. Though there more, I’ll specifically cover stopcock/ball valves, weir style valves; and diaphragm valves. Other valve technologies, such as the butterfly valve, will not be discussed because their construction materials are generally not used for fluid handling components for the semiconductor industry.

Starting with the simplest design, the stopcock/ball valve provides by far the best Cv of the three technologies mentioned. Considering the premium Cv achieved, you would assume they are expensive. Instead they are generally the cheapest of the three values mentioned. One drawback in using stopcock valves is the need for a liquid oring on the fluid path which may create compatibility issues. The exception is the Furon® SCM Valve, a stopcock valve that employs a PFA on PTFE technology and allows for oring-free sealing. Additionally, stopcock valves can lower pressure/ temperature ratings and have a tendency to generate a great deal of particles when actuated. This occurs when the key or ball is rotating inside the valve body. Both drawbacks are related to the PTFE/PFA construction materials required for the flow path by the micro-e industry.

The weir style valve, if done properly, should provide a very good Cv – perhaps not as good as a stopcock/ball valve, but still very good. And although liquid orings are not an issue, these valves have other drawbacks. In a weir style valve the diaphragm is generally a sandwich structure consisting of a thin layer of PTFE that is backed by an elastomeric component in which a metal pin is embedded to connect the membrane to the valve actuating system. It is the sandwich materials that generate a number of potential issues when used on critical, high purity chemistry. Specifically, the delamination of the sandwich creates the possi- bility of multiple points of contamination to the liquid (metal & elastomer). In addition, the significant surface contact between the membrane and the valve seat, which is necessary to secure a full seal, generates a lot of particles – though significantly less than a stopcock/ball valve.

The diaphragm valve is the most commonly used valve in the semiconductor industry as it offers a great balance in terms of the issues previously identified: potential contami- nation, materials and particle generation. The trade-off is that the construction of these valves is more complex and as a result they are priced higher than the average cost of the other valves. Additionally, the Cv performance is well below a stopcock/ball valve and slightly below a weir style valve. However, by using Saint-Gobain’s patented rolling diaphragm technology this does not have to be an issue. In fact, with this technology, we can offer the equivalent Cv of a weir style valve in combination with premium pressure and temperature capabilities as well as the cleanest valve technology – all of which allows for a system design with the lowest impact possible on the transported fluid.

As demonstrated in this document, understanding the Cv rating and the impacts that could affect that rating as it relates to valves is critical when optimizing an installation for fluid and energy efficiency. Cost aside, there are a number of issues that are unique to the semiconductor industry that ultimately guide and often restrict installation choices, such as: dead volume, particle generation, cleanliness as well as the physical and mechanical properties of appropriate polymers. Additionally, choosing the appropriate valve for your installation goes far beyond the simple notion that if “I need more flow, I will get a larger valve.” Most likely the residual effect of that choice will affect the performance of the system, particularly regarding cleanliness. Instead critical adjustments to your valve actuation mechanism and valve flow path designs as well as to your valve technology may allow you to achieve the required results – even if the installation still uses the same 1⁄2” valve…but more on this point in another article.

References

1. www.processsystems.saint-gobain.com/sites/imdf.processsystems. com/files/2015-12-03-part-one-design-impact-for-fluid-components.pdf

BY ARABINDA DAS and JUN LU, TechInsights, Ottawa, ON

Last year was a great year for photovoltaic (PV) technology. According to Renewable Energy World magazine, since April 2016, 21 MW of solar PV mini-grids were announced in emerging markets [1]. The exact numbers of installed solar grids for 2016 has not been published yet but looking at the data for 2015, the PV industry is growing, helped by the $/watt for solar panels continuing to drop. The $/watt is obtained by taking the ratio of total cost of manufacturing and the number of watts generated. According to the Photovoltaic Magazine, the PV market continued to grow worldwide in 2015. The magazine also makes reference to the newly published report by the International Energy Agency Photovoltaic Power System (IEA PVPS) programme’s “Snapshot of Global Photovoltaic Markets 2015,” which also states that the total capacity around the globe has crossed the 200 GW benchmark and is continuing to grow [2]. This milestone of 200 GW in installed systems is a remarkable achievement and makes us think of the amazing journey of PV technology. The technology was born in Bell Labs, around 1954, with a solar cell efficiency of just 4% [3]. By the end of the 20th century, the overall solar cell efficiency was close to 11% and the worldwide installed capacity of PV was only 1 GW [3]. Today, seventeen years later, it has soared to 200 GW, with single junction cells having efficiencies around 20% [2].

Si-based solar cells

To celebrate this important milestone, we put TechInsights’ analysis and technical databases to work to investigate the structure of solar cells of two leading manufacturers and compare them to earlier technologies. We chose to analyze Si-based solar cells only, as they represent over 85% of the global market. According to the 2016 IHS Markit report, the top three PV module suppliers in the world are Trina Solar, SunPower, and First Solar [4]. We procured panels from Trina Solar, a Chinese based company, and SunPower, an American company, and carried out a structural analysis of these panels. These analyses helped us take a snapshot of current PV technology. We compared these two types of panels with an older panel from our database. This panel is about eight years old and was made by Kaneka (Japan). We will provide an overview of each panel and their underlying structure.

Table 1 consolidates some of the important param- eters of the three panels. The SunPower panel is based on monocrystalline silicon and the Trina solar panels are based on polycrystalline silicon. The older Kaneka panel is based on amorphous Si thin film technology. The panel from Kaneka is an earlier product; their recent products are made using hybrid technology, a combination of amorphous films and polycrystalline substrates, The Kaneka panel complements very well the other two products which are based on Si crystalline wafers. The technology to fabricate the solar cells (thin film, multi-crystalline or mono-crystalline) has a direct impact on the efficiency of the cells and on their electrical parameters like the open circuit voltage (Voc) and the short circuit current (Isc), as can be seen in Table 1. This table also shows that the Kaneka thin-film based panel has the lowest nominal power among the three. The ratio of nominal power to the light power that is received by the PV panel is indicative of its efficiency. It can be seen also that Kaneka’s thin film panel has the highest open circuit voltage which is the maximum voltage available from the solar cell without any load connected to it.

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Table 1 indicates that SunPower is the only one among the three that uses an n-type substrate and has the highest solar efficiency. SunPower has the lowest weight per meter-square of all the panels assessed (9.3kg).

Unlike SunPower panels, most installed Si solar panels employ a p-type substrate, even though the first silicon-based solar cells developed at Bell Labs were based on n-type Si substrates [3]. Researchers J. Libal and R. Kopecek posit that the industry transitioned to p-type substrates because the initial usage of solar cells was in space applications and p-type wafers demonstrated less degradation in the presence of cosmic rays. They suggest that for terrestrial applications there is growing evidence that n-type based solar panels are preferred over p-type based panels [5]. The reasons for choosing n-type Si substrates rather than p-type substrates are because the former are less sensitive to metallic impurities and thus are less expensive to fabricate. In general, the minority carrier diffusion lengths in n-type substrates are higher than p-type Si substrates. Also, n-type Si substrates can withstand higher processing temperatures than p-type substrates, which are prone to boron diffusion. According to the International Technology Roadmap for Photovoltaic (ITRPV), n-type based substrates will increase in prevalence and may eventually replace the p-type monocrystalline Si cells [6].

Thin film based solar panels are very different from monocrystalline Si cells. Thin film cells have the lowest efficiency and yet they too have a role to play in the PV industry. They are the most versatile; they can be coated on different substrates such as glass, plastic or even flexible substrates. The other big advantage of amorphous solar films is that they can be manufac- tured in a range of shapes, even non-polygonal shapes, thus they can be used in various applications. Also, thin film solar panels are not affected by high temper- atures, unlike crystalline solar panels. Thin film based panels made from amorphous Si are more effective for wavelengths between 400 nm to 700 nm, which is also the sensitive spectrum of the human eye; thus they can be used as light sensors [7]. Usually, thin film panels are almost half the price of monocrystalline panels. Amorphous silicon solar cells only require 1% of the silicon used in crystalline silicon solar cells [7].

Multi-crystalline (MC) solar panels are also cheaper than monocrystalline solar panels. MC panels are made by melting raw silicon and confining them into square molds, where they are cooled. This MC-Si process does not require the expensive Czochralski process. In the early days, the cost of fabrication of MC-Si panels was higher than thin film based panels. Now, due to the major advances in fabrication technologies, these panels often have the best $/ watt, which represent the ratio of cost to manufacture to energy output [8]. It is difficult to compare $/watt directly from different manufacturers and different types of solar panels as the technology is manufacturing is changing rapidly and often the most recent products of a manufacturer are not compared. A more sensible factor of comparison would be the ratio of total kilowatt-hours the system generates in its lifetime divided by the cost per square unit of the panel. To make a detailed estimation even the installation cost and tolerance to shade, overall reliability must be included in the calculations, which is beyond the scope of this article.

Solar panel overview

FIGURE 1 shows the panel from Kaneka. It indicates that the Kaneka solar panel cells are long strips that run across the whole length of the panel. The color of the panels is a shade of purple. The Kaneka Solar which is amorphous Si-based, has a very uniform color. The inherent structure of amorphous Si-films has many structural defects because they are not crystalline and thus are tolerant to other defects like impurities during manufacturing, unlike crystalline based panels [7]. The color of the thin film panels is strongly thickness dependent because thickness affects the light absorption. A solar cell’s outward appearance can range from blue to black and is dependent on the absorption and reflectivity of their surface. Ideally, if the cell absorbs all the light impinging on the surface it should be black. FIGURE 2 shows the panels from Trina solar and Sunpower. The Trina Solar panel has a blueish color and each cell is perfectly square. The SunPower SPR-X20- 250-BLK solar cell has a uniform blackish color. The spacing between the cells, the interconnect resis- tance, the top contacts and the materials used for the connections affect the overall performance of the panel. All three manufacturers connect their cells within a PV module and PV modules within an array in a series configuration.

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Table 2 summarizes the cell dimensions for the three manufacturers. Kaneka panels have the narrowest space (0.55mm) between the cells. The Trina solar panel has a 3 mm wide gap and a 5 mm gap, between two adjacent solar cells, in the horizontal and vertical direction respectively. These gaps are used for bus electrodes. In the SunPower solar panel, the metal grid is placed on the back surface eliminating metal finger width as a layout constraint. This design significantly reduces the finger resistance and improves the series resistance.

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For all panels, interconnects are made between the cells. The metallization and interconnects between the cells is a field of technology on its own. There are various techniques like lithography, laser grooving and printed contacts and these details are discussed more in detail elsewhere [9, 10, 11].

Solar panel cross-sections

In this section, we look into the layers deposited on the substrates. Cross-sectioning these big panels is not a trivial feat. These panels are covered with tempered glass and shatter during sawing and cross-sectioning. To extract a small rectangular piece requires patience and involves sawing and grinding processes. In most cases, the glass was removed before doing the cross-section. FIGURE 3 illustrates two SEM cross-sectional images and one schematic drawing. The SEM cross-sectional images show the top and bottom part of the Kaneka solar cell. In figure 3(a), the active layers comprise indium- tin- oxide, an amorphous silicon layer capped with zinc oxide, silver and a very thin layer of Ni-Al. On top of the Ni-Al film, solder is deposited. Ni-Al provides better adhesion to solder. Two electrical contacts are made between the cells, one to the indium-tin-oxide for the back contact and the other to the Ni-Al layer. Figure 3(b) exposes the layers under the glass substrate. The rear surface of the glass substrate is covered by a soft material such as EVA (ethyl-vinyl-acetate), which in turn is covered by a rear Polyvinyl Fluoride (PVF) layer called the backsheet (Tedlar or similar). EVA is also used on the top surface (figure 3(a)). The usage of these layers is standard practice in the PV industry. The main function of these layers is that they are impervious to moisture and are stable under prolonged exposure to sunlight. On the front side, EVA also helps to reduce reflection and provides good adhesion between the top glass and the solar panels. Figure 3(c) shows the complete stack in the Kaneka solar cell.

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FIGURE 4 presents the stack of materials on the multi- crystalline substrate of the Trina Solar panel. The substrate is p-type and has a very thin phosphorous doped region near the top surface. This n-doped region forms the PN junction. A silicon nitride anti-reflective coating layer is deposited on top of the substrate and in designated areas the passivation is opened and silver is deposited to make electrical contact to the n-doped regions. At the bottom of the multi-crystalline substrate, there is also a thin region of high p-doping concentration and this forms the back surface field layer. This solar cell module is fabricated using passivated emitter and full metal back-surface-field (BSF) technology. BSF technology is implemented to mitigate rear surface recombination and this is done by doping heavily at the rear surface of the substrate. This high doping concentration keeps minority carriers (electrons) away from the rear contact because the interface between the high and low doped areas of same conductivity acts like a diode and restricts the flow of the minority carriers to the rear surface. Passivated emitters in the front side and BSF layer on the rear side improve the efficiency of the cells. Figure 3(b) is the schematic repre- sentation of the cell without the EVA and PVF layers.

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FIGURE 5 shows an optical cross-section of the SunPower cell. Figure 5(a) shows that SunPower employs a backside junction technology with interdigitated backside p-emitter and n-base metal. This means that both the contact’s n and p-electrodes are at the bottom of the substrate and are placed in in an alternating manner. Having all the metal contacts on the rear side has two big advantages:

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1. Metallic contacts are reflective and occupy space that can be used to collect more sunlight; transferring these contacts to the rear side improves the cell efficiency and also leaves the front surface with a uniformly black color, which is more aesthetic for the home users.

2. It reduces bulk recombination. The mono-crystalline substrate is only 120 μm thick. It is designed so that the carrier is generated close to the junction. The substrate is n-type and p-electrodes are formed by localized doping on the bottom part of the substrate.

Figure 5(b) illustrates the general structure of the cell.

FIGURE 6 depicts a SEM cross-section of the metal fingers that connect to the interdigitated electrodes. The pitch between the metal fingers is 920 um and repeats over the entire back surface of the panel.

All three manufacturers employ some sort of surface texturing along with anti-reflective coatings to reduce reflection but SunPower uses the most advanced technology for surface texturing. FIGURE 7 illustrates a SEM topographical image of the front surface texture of the monocrystalline substrate having pyramids, which are etched into the silicon surface. These faceted surfaces increase the probability of reflected light entering back to the surface of the substrate. A similar concept is also applied to the back surface.

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The future is sunny and bright

Of the three panels we analyzed, SunPower solar panels employ the most advanced technologies and they illustrate how the solar cell has evolved over the ages. It started from a simple PN junction, then passivated emitters were intro- duced along with local back-surface-field (BSF) technology, which came to be known as Passivated-Emitter with Rear Locally (PERL) diffused technology. In contrast, today the most advanced technology is interdigitated back contacts along with passivated contacts.

In addition to these advances, there is great progress in tandem cells and multi-junctions to capture the different wavelength regions of the sun’s rays. A recent article in IEEE spectrum magazine presented the state of art of record-breaking PV cells made with different techniques such as thin film, crystalline Si, single junction, multi-junction cells. PV cells especially the multi-junction cells, have now crossed the 50% efficiency barrier [12]. Similarly, a publication from the alterenergy.org has collected all the major advances made in PV technology and discusses concepts like colloidal quantum dots and GaAs for cell technology, along with new applications [13]. Today, we regularly read about new materials (like perovskites) and come across new techniques that improve solar panel efficiencies, including new manufacturing methods to reduce the overall cost of fabrication. Moreover, PV cells are used in an innovative manner. The installation of PV panels is no more restricted to isolated rooftops or solar farm. An article in the Guardian made a reference to a solar panel road in Normandy, France [14]. At TechInsights, we will continue to keep an eye on emerging solar cell technologies.

The efforts emerging from various organizations all over the world are very encouraging. There are indeed many challenges for renewable energy to overcome before fiscal parity with fossil fuels is achieved; particularly for PV energy. Nevertheless, there is an increased focus on climate change issues. This has resulted in a significant amount of resources being allotted to PV technology in many countries, especially in developing countries such as China, India, and Brazil [1, 2]. This optimistic scenario reminds us of the song “I Can See Clearly Now” by the 1970s American singer Johnny Nash, where the refrain runs optimistically, “It’s gonna be a bright, bright sun-shiny day.”

References

1. http://www.renewableenergyworld.com/articles/2017/01/21-mw- of-solar-pv-for-emerging-market-community-mini-grids-announced- since-april.html;
2. http://www.pv-magazine.com/news/details/beitrag/iea-pvps— installed-pv-capacity-at-227-gw-worldwide_100024068/#ixzz4MB1 a44hq
3. The history of solar: https://www1.eere.energy.gov/solar/pdfs/solar_ timeline.pdf
4. http://news.ihsmarkit.com/press-release/technology/ihs-markit- names-trina-solar-sunpower-first-solar-hanwha-q-cells-and-jinko-
5. www.pv-tech.org/guest…/n_type_silicon_solar_cell_technology_ ready_for_take_off
6. http://www.itrpv.net/; http://www.itrpv.net/Reports/Downloads/2016/ 7. http://www.solar-facts-and-advice.com/amorphous-silicon.html
8. http://energyinformative.org/solar-cell-comparison-chart-mono-
polycrystalline-thin-film/
9. RP_0706-14839-O-4CS-11Kaneka
10. RP_0616-41931-O-5SA-100_Trina
11. RP_0716-42662-O-5SA-100_SunPower
12. http://spectrum.ieee.org/green-tech/solar/what-makes-a-good-pv-
technology
13. http://www.altenergy.org/renewables/solar/latest-solar-technology.
html
14. https://www.theguardian.com/environment/2016/dec/22/solar-panel-
road-tourouvre-au-perche-normandy

A new system combines acoustic, optical and reflectometric techniques to enable measurement of metals, dielectrics, resists and critical dimensions on a single platform.

BY CHEOLKYU KIM, Director of Metrology Product Management, Rudolph Technologies, Inc.

Rapid growth in the mobile device market is generating demand for advanced packaging solutions with higher levels of system integration and increased I/Os and functionality. This demand is driving 2.5D/3D integration of IC devices, which in turn requires sophisticated packaging technologies. Among various approaches, fan-out is gaining traction as outsourced semiconductor assembly and test (OSAT) houses and wafer foundries roll out their own technologies. As illustrated in FIGURE 1, the adoption of fan-out technology accelerated significantly in 2016, and is projected to reach $2.5 billion by 2021, a more than 10X increase from 2015.

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First generation “core” fan-out was geared toward mobile applications and had RDL lines that were typically 10/10μm (line/space) and larger. Second generation HDFO processes, which were developed to integrate multiple chips in a single package, use more RDL lines at smaller width and tighter pitch, down to 2/2μm and smaller. Growth in HDFO accelerated with the entry of Apple and TSMC in 2016 and accounts for the bulk of the fan-out growth projected through 2021 [2-4].

As design rules for HDFO approach those of front-end processes, so too will requirements for process control and, in consequence, the need for more accurate and repeatable metrology. Until now, manufacturers have characterized metal films, such as RDL and under bump metallization (UBM), using semi-automated measurement tools, such as contact profilometers, which are easy to use and relatively inexpensive. However, these tools are not the best solution for measuring a variety of products with varying topographies in high volume production.

High Density Fan-Out process control

HDFO processes include one or more RDL, the number depending on the application. Like front-end processes, HDFO processes use additive and subtractive technol- ogies to create patterns of conductive metal lines isolated by dielectric materials. As RDL lines become smaller, controlling line resistance with appropriate dimensional control has become essential. For an RDL process, the most important parameters to monitor are dielectric thickness, Cu seed layer thickness, Cu thickness and line width (CD). In general, the process must operate inside a window that varies within 10% of the target value. This, in turn, requires measurement tools with a gauge capability (3σ repeatability + reproducibility) of 10% of the variability, or 1% of the target value. In addition to delivering accuracy and repeatability, the metrology system must be able to operate on product wafers and, therefore, 1) be able to measure test structures smaller than 50μm, 2) be non contact/non-destructive/ non-contaminating, 3) be fast enough to support high volume production and 4) be able to handle the significant surface topography and substrate/wafer warpage that are induced by the HDFO process.

As shown schematically in FIGURE 2, the metrology system described here (MetaPULSE® AP, Rudolph Technologies), combines picosecond ultrasonic laser sonar (PULSETM), automated optical microscopy and reflectometry to meet all the requirements for RDL process control in a single system. The acoustic technique, well proven and widely accepted for metal film metrology in front-end applications, is a first principle technology that provides accurate measurements of metal film thickness for UBM and RDL.

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Measurements of RDL thickness with this technique on dense line arrays, pads and bumps have shown excellent correlation to cross sectional scanning electron microscope (X-SEM) results. The precision and gage capability of the technology have been validated down to 2μm and meet OSAT and foundry RDL roadmap requirements.

The integration of a high-resolution reflectometer provides accurate measurements of dielectric and resist thickness, ranging from a few 1000Å to 60μm, on product wafers. The incorporation of an automated optical microscope/high-resolution camera provides gage-capable CD measurements. CD measurements can be made simultaneously with thickness measurements. The addition of optical CD measurements and reflectometer-based transparent film thickness measurements to the acoustic platform provides an efficient and comprehensive in-line RDL metrology solution that eliminates the need to route wafers to multiple measurement tools.

PULSE acoustic thickness measurements on opaque films

FIGURE 3 illustrates the principles of the PULSE acoustic measurement technology. An extremely short laser pulse is focused onto a small spot on the sample surface where the energy of the laser pulse is absorbed by the film surface. This causes a sudden increase of surface temperature, and rapid thermal expansion launches a sound wave on the surface that travels into the film. When the sound wave reaches an interface with an underlying film, it is partially reflected back to the surface as an echo. Upon arrival at the surface, the echo causes a change in optical reflectivity, which is detected to measure the round-trip travel time of the sound wave. Film thickness can be calculated from the travel time of the sound wave and the speed of sound in the material. Some of the energy from the original sound wave is transmitted through the interface. In a multi-layered stack, the progressing sound wave returns a distinct echo from each interface. An analysis of the round-trip travel time for each successive echo permits the calculation of the thickness of each layer. Typical data acquisition times vary from 1s to 4s per site. Repeatability is < 0.1% of target thickness, meeting the 10% GR&R requirement. FIGURE 4 shows the correlation between X-SEM and PULSE measurements for RDL in the 1.25μm-1.5μm thickness range. The excellent correlation clearly demonstrates the accuracy of PULSE thickness measurements.

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Reflectometer thickness measurements on transparent films

FIGURE 5 (left) demonstrates the strong correspondence between a measured reflectometer signal and a model fitted curve for 5μm polyimide on Si. The figure also shows the correlation between reflectometer measurements and a fab reference metrology tool. The excellent correlation with the reference tool confirms the accuracy of reflectometer measurements. Data collection time for reflectometer measurements is typically less than 1s. The reflectometer has excellent sensitivity with Å level resolution and gage-capable R&R.

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Automated optical CD measurements

Using the optical microscope/ high resolution camera system, users can define multiple regions of interest (ROI) for CD measurements, including single line and multi-line arrays. The built-in measurement algorithms can report individual or average values. Extension of the CD technique to also measure overlay has shown promising results and additional work is in progress to fully characterize the capability. FIGURE 6 shows images and signals from CD measurements on lines and arrays. The strong correlation between optical CD and X-SEM measurements (FIGURE 7) validates the accuracy of the technique. CD measurement with the optical microscope is limited by the micro- scope’s resolution, typically 1μm or larger. Since SEM resolution is typically on the scale of nanometers, the correlation requires proper calibration. The results shown in Fig. 7 are after calibration.

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Multi-layered stacks

Most of RDL plating requires prior deposition of a Cu seed layer, the thickness of which must also be tightly controlled. FIGURE 8 (left) shows examples of the acoustic signals acquired from three Cu/ Ti stacks of varying thickness. The first positive peak of each signal gives the round-trip travel time of the sound wave in the Cu film, while the spacing between first and second positive peaks gives the round-trip travel time through the Ti layer. The echo positions are used to calculate the thickness of Cu and Ti layers simultaneously. Figure 8 (right) shows the signal of an Au/Ni/Cu/Al stack measured on UBM. The echo from each layer is distinct. Knowing the arrival times of the echoes and the speed of sound in the materials, the system calculates the thickness of all four layers simultaneously, with 3σ repeatability less than 1% for each of the layers.

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Warped wafer handling

The thin wafers/substrates used in HDFO processes can be warped significantly at several different steps in the process, most significantly by the mismatch between thermal expansion coefficients of the molding compound and the die. Warpage of 2mm or more poses a major challenge to handling and measurement systems. A specially designed vacuum chuck has three concentric vacuum zones. Applying vacuum to the zones sequentially, starting with the innermost zone and working out, the chuck pulls and holds warped wafers flat against itself to allow accurate measurements.

Conclusions

High density fan-out packaging is essential for advancing growth in mobile and networking applica- tions. The integration of multi-chip modules in fan-out processes requires complex processing using tools and materials that are significantly more expensive than traditional packaging lines. We have described an automated metrology solution that combines acoustic measurements with high resolution reflectometry and optical microscopy to provide comprehensive, gage- capable measurements for characterizing critical process steps in high volume production applications. Simultaneous measurement of multiple parameters on a single platform eliminates the need to route product through several different tools, improving the speed and efficiency, and reducing the overall cost-of-ownership, of the metrology process.

References

1. “Fan-out technnologies and MarketTrends 2016 Report”,Yole Devel- oppement, July 2016
2. “What is driving advanced packaging platforms development?”, T. Buisson and S. Kumar, Chip Scale Review, pp. 32-36,May-June 2016 3. “Recent advances and trends in advanced packaging”, J. Lau, Chip
Scale Review, pp. 46-54, May-June 2017.
4. “Status of Advanced Packaging Report,” Yole Developpement, June 2017.

Synopsys, Inc. (NASDAQ: SNPS) today announced that the Synopsys Design Platform has been fully certified for use on Samsung Foundry’s 28FDS (FD-SOI) process technology. A Process Design Kit (PDK) and a comprehensive reference flow, compatible with Synopsys’ Lynx Design System, containing scripts, design methodologies and best practices is now available. For Samsung Foundry’s latest differentiated process offering, support for bias throughout the Design Platform flow has been thoroughly verified and certified to achieve optimal power and performance tradeoffs.

“FD-SOI technology offers one of the best power, performance, and cost tradeoffs,” said Jaehong Park, senior vice president of the Foundry Solutions Team at Samsung Electronics. “Samsung Foundry’s 28FD-SOI technology allows designs to operate both at high and low voltage making it ideal for IoT and mobile applications. Moreover, the FD-SOI technology exhibits the best soft error immunity, and, therefore, is well suited for applications that require high reliability such as automotive. Availability of certified Synopsys Design Platform, PDK and reference flow will allow our mutual customers to accelerate adoption of our 28FDS technology.”

“Our long standing, close collaboration with Samsung Foundry starts very early, allowing Synopsys to refine tools and flows enabling customers to achieve desired performance and power targets,” said Michael Jackson, corporate vice president of marketing and business development for the Design Group at Synopsys. “Certification of the Synopsys Design Platform, complete with PDK and reference flow helps our mutual customers to rapidly design with confidence for Samsung Foundry’s 28-nm FD-SOI process.”

DSA and EUV should be envisioned as complementary, not competing, techniques that will eventually become mainstream for fine-pitch lithography.

BY DOUGLAS J. GUERRERO, Ph.D., Brewer Science, Rolla, MO

Advances in lithography have always been critical in the drive toward each subsequent semiconductor node. Anticipating limitations in the scaling ability of immersion lithography, the industry has been pursuing next-generation lithography techniques. Several techniques have been proposed, including extreme ultraviolet (EUV) lithography, multibeam electron-beam lithography, nanoimprint lithography and directed self-assembly (DSA) of block copolymers.

DSA attracted a great deal of interest from major semiconductor manufacturers for several years, following its initial development in the early 2000s. However, it has since fallen out of favor to some extent, in part because of advances in EUV lithography as a result of focused investment in that technology. Recent developments in DSA materials and processing promise to overcome concerns that have delayed its implementation.

Choosing an appropriate lithography technique does not need to be an either-or proposition. The greatest opportunity may lie in leveraging both EUV lithography and DSA. Although these two technologies are sometimes seen as competing, it makes more sense to envision them as complementary. This article explains how lithography may benefit by taking advantage of both EUV and DSA, and why previously existing roadblocks may no longer pose obstacles.

The material defines the pattern

Unlike most lithography techniques, where the mask defines the pattern, in DSA the pattern exists in the material itself. The original block copolymers (BCPs) for DSA combine polystyrene (PS) and poly(methyl methacrylate) (PMMA), two polymers that naturally segregate themselves into separate phases. Adjusting the relative proportions of PS and PMMA in the PS-b-PMMA material changes the morphology from spherical to cylindrical to lamellar (FIGURE 1). The product of the Flory interaction parameter, χ, and the segment length determine the spacing of the ordered structure. The higher the value of χ, the finer the pitch of the resulting structure.

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Standard PS-b-PMMA materials have relatively low χ, which limits the pitch to 20nm or larger. Some materials manufacturers are considering chemistries other than PS-b-PMMA to produce high-χ BCPs, replacing the PMMA component with polydimethylsiloxane or polyhydroxystyrene. Modifying PS-b-PMMA is another approach to increase χ. In this manner, it is possible to tune χ, the molecular weight and the glass transition temperature to achieve lamellar spacing between 14nm and 40nm under various annealing conditions.

The process flow for BCP deposition is straightforward. A neutral layer spin-coated onto the substrate allows for the BCP to separate into its individual domains during the thermal annealing process. The neutral layer allows for domain separation because it does not have affinity for either of the polymer chains in the BCP. Polymer domain separation is responsible for pattern formation.

Processing considerations

The DSA deposition process uses one of two basic approaches (FIGURES 2 and 3). Graphoepitaxy leverages topography to align the BCPs, depositing them into relatively deep trenches. Guide patterns define the trenches, confining the BCPs into configurations in which they align in a preferred direction. Chemical epitaxy, or chemoepitaxy, is based on a chemical pattern on a flat substrate, on top of which the BCPs self-align.

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Click to enlarge.

The semiconductor industry is pursuing both graphoepitaxy and chemoepitaxy approaches, favoring the former for producing fine-pitch vias and the latter for creating arrays of parallel lines.

Annealing temperatures are in the range of 250°C to 275°C, making them compatible with standard semiconductor processing. The annealing step can be lengthy—up to two hours to create structures with sufficiently low defect rates—adding cost to the process.

PS-b-PMMA BCPs are being manufactured in high- volume quantities. Worldwide, 1.1 million tons of the material are currently in use for a variety of applica- tions. This quantity is greater than the needs of the entire semiconductor industry. Therefore, although no commercially produced DSA materials are currently targeted for semiconductor applications, the infra- structure is in place to scale up production of suitable materials when the industry is ready.

Why DSA is attractive now

DSA was added to the ITRS roadmap in 2007. Major semiconductor industry players originally believed DSA would enter commercial production anywhere between the 14nm and 7nm logic nodes, and even sooner for DRAM; but so far that has not come to pass. A survey at the 2016 DSA Symposium suggested that the technology is still not ready for the mainstream and won’t be for several years. But some IDMs would like to accelerate the process, and there are reasons to believe this is not only possible, but desirable.

Decreasing the wavelength to 193nm immersion lithography has enabled line width and spacing down to 80nm. Techniques such as self-aligned quadruple patterning (SAQP) can create even smaller features through multiple lithography/etch iterations, but at the expense of adding lithography steps, each requiring a custom mask.

Immersion lithography is reaching its limits, providing an opportunity for next-generation lithographic techniques. Designs with critical dimensions (CD) in the range of 10nm to 30nm create a sweet spot for these state-of-the-art techniques.

Advances in EUV lithography are one factor that has led the industry to favor it over DSA. Today’s EUV materials have greater sensitivity compared with older- generation products, therefore requiring lower UV doses; and line roughness has improved as well. EUV lithography can create vias with 30nm or 40nm spacing that are not feasible with immersion lithography.

DSA enables even finer resolution than the semicon- ductor industry currently demands. Feature sizes are just now approaching a level where DSA can be especially effective. If these trends continue, the technique is poised to be widely adopted before the end of this decade.

DSA and EUV: Better together?

The most effective solution may lie in leveraging EUV and DSA technologies to take advantage of the strengths of each. Both methods can achieve resolution levels that are compatible with the N7 and N5 logic nodes. EUV lithography is well-suited to patterning designs with multiple different pitches, down to line width and spacing around 30nm. For such fine pitches, however, the number of mask steps required may make the technique prohibitively expensive. Local CD uniformity (LCDU) can also be a concern, especially at high throughput rates.

The initial hard-mask lithography process is the same for both EUV and DSA, but they diverge during pattern processing. Once the BCPs are deposited, DSA can achieve 30nm feature size without requiring additional masks. Annealing naturally separates the two phases into the correct morphology. The DSA process, however, is best suited to designs with a single pitch.

EUV can be used to pattern lower-resolution features on a chip, plus create spacers for subsequent DSA deposition. This combination provides the greatest design flexibility while streamlining the fabrication process, eliminating processing steps and reducing mask costs. LCDU is also better than with EUV alone.

DSA is best suited for devices with multiple repeating, regular fine-pitch features. Therefore, it likely will first be implemented in DRAM storage, later migrating to use in via layers on logic devices. Graphoepitaxy, especially using EUV to deposit the spacers, can enable more complex designs using DSA, where different regions of the chip require different pitches. This will presumably be the approach of choice for logic chips.

Despite the promise that leveraging both DSA and EUV offers, the semiconductor industry will only migrate to this approach once suppliers can convince IDMs that the materials have overcome their technical limita- tions. DSA has suffered from several challenges that have delayed its adoption: Primary issues are defectivity, pattern placement accuracy, ease of integration into manufacturing flows, and cost. But there is reason to be optimistic, as advances in chemistry and processing methods are improving all these metrics.

Overcoming technical challenges

The 2016 DSA Symposium survey identified defec- tivity as the greatest technical challenge. Defectivity and cost are related, in that the lowest defect levels are seen with the longest annealing times. While annealing for as little as five minutes causes the two phases to separate, the resulting material contains far too many defects to be suitable for commercial use.

Wafers are typically annealed one at a time, which can make the cost of annealing prohibitive. However, recent research using batch annealing in a vertical furnace showed great promise for reducing cost. By annealing 150 wafers in parallel for 30 minutes, researchers were able to demonstrate sufficiently low defect levels at a cost lower than that of SAQP.

Using both DSA and EUV has the potential to alleviate the problem of pattern placement errors. For example, EUV lithography can create prepatterned holes for doublet vias. The two vias may merge during the EUV process but will then automatically separate during DSA. Without DSA, an additional lithography step may be required to avoid merged vias.

This approach of leveraging EUV and DSA for fine- pitch vias is most reliable when the via shape is optimized. Studies have shown that a peanut shape, rather than an elliptical one, is ideal for creating doublet vias with minimal risk for pattern placement errors, even at the challenging N5 node.

Collaborating to advance DSA adoption

The semiconductor industry has extensive experience with lithography, but DSA requires a shift in mindset. BCP materials are not something that the industry is used to, and revolutionary rather than evolutionary changes in materials and processes can face resistance. DSA needs to be demonstrated on real devices before it can achieve traction in the semiconductor market.

Collaborative efforts between semiconductor industry materials suppliers and chemical companies with deep experience in BCPs are one route to bridge this gap. One such collaboration is currently underway. Brewer Science has teamed up with Arkema, a company with two decades of experience producing BCPs, but little leverage with the semiconductor industry. The partnership, begun in 2015, has led to pilot production of DSA materials, paving the way for the technique to move out of the laboratory and into commercial semiconductor products.

DSA and EUV should be envisioned as complementary, not competing, techniques that will eventually become mainstream for fine-pitch lithography at the N7 node and beyond. Partnerships between materials and chemical companies are poised to enable this transition, unlike previous efforts by single organizations.