Category Archives: Wafer Processing

IC Insights’ April Update to the 2016 McClean Report, to be released later this week, includes IC Insights’ final 2015 top 50 company rankings for total semiconductor and IC sales as well as rankings of the leading suppliers of DRAM, flash memory, MPUs, IC foundry services, etc.

Figure 1 ranks the top 13 IC foundries (pure-play and IDM) by foundry sales in 2015.

Apple TSMC sales

TSMC, by far, was the leader with $26.4 billion in sales last year.  In fact, TSMC’s 2015 sales were over 5x that of second-ranked GlobalFoundries (even with the addition of IBM’s chip business in the second half of 2015) and almost 12x the sales of the fifth-ranked China-based foundry SMIC.  As shown, there are only two IDM foundries in the ranking—Samsung and Fujitsu—after IBM and Magnachip fell from the list in 2015.  Despite losing a significant amount of Apple’s business, Samsung easily remained the largest IDM foundry last year, with more than 3x the sales of Fujitsu, the second-largest IDM foundry.

Illustrating the dramatic effect of exchange rate fluctuations on the IC sales numbers, TSMC’s 2015 growth rate was about half (6%) of what it was in its local currency (11%).  Thus, while the company met its stated goal of 10% or better growth in 2015 in NT dollars (840.5 billion), its growth rate in U.S. dollars was only 6%.

Driving home just how important Apple’s foundry business is, TSMC’s foundry sales increased by $1,464 million last year while its sales to Apple jumped by $1,990 million, representing more than 100% of TSMC’s total foundry sales increase in 2015.  As a result, without Apple, TSMC’s foundry sales would have declined by 2% last year, eight points less than the 6% increase it logged when including Apple.

Second ranked GlobalFoundries took over IBM’s IC business in early July of 2015.  It should be noted that besides $515 million in IDM foundry sales IBM made in 2014, the company also had about $1.0 billion of internal transfer IC revenue that year.  As a result, GlobalFoundries’ quarterly sales in 4Q15 were about $1.4 billion, an annual run-rate of $5.6 billion, about 12% greater than the company’s 2015 sales of $5.0 billion. However, without the addition of IBM’s sales in the second half of last year, GlobalFoundries’ sales would have declined by 2% in 2015.

Sales from the top 13 foundries’ shown in Figure 1 were $46.7 billion and represented 93% of the $50.3 billion in total foundry sales in 2015.  This share was two points higher than the 91% share the top 13 represented two years earlier in 2013.  With the barriers to entry (e.g., fab costs, access to leading edge technology, etc.) into the foundry business being so high and rising, IC Insights expects this “top 13” marketshare figure to continue to slowly rise in the future.

North America-based manufacturers of semiconductor equipment posted $1.38 billion in orders worldwide in March 2016 (three-month average basis) and a book-to-bill ratio of 1.15, according to the March Equipment Market Data Subscription (EMDS) Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.15 means that $115 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in March 2016 was $1.38 billion. The bookings figure is 9.4 percent higher than the final February 2016 level of $1.26 billion, and is 0.9 percent lower than the March 2015 order level of $1.39 billion.

The three-month average of worldwide billings in March 2016 was $1.20 billion. The billings figure is 0.5 percent lower than the final February 2016 level of $1.20 billion, and is 5.3 percent lower than the March 2015 billings level of $1.27 billion.

“Order activity remains steady and is on par with both the previous quarter and one year ago,” said Denny McGuirk, president and CEO of SEMI. “3D NAND and advanced logic are the key drivers for investments.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
October 2015

$1,358.6

$1,325.6

0.98
November 2015

$1,288.3

$1,236.6

0.96
December 2015

$1,349.9

$1,343.5

1.00
January 2016

$1,221.2

$1,310.9

1.07
February 2016 (final)

$1,204.4

$1,262.0

1.05
March 2016 (prelim)

$1,198.5

$1,380.5

1.15

Source: SEMI (www.semi.org), April 2016

Park Systems announced today the appointments of Charlie Park as Senior Vice President of Global Sales, and Jong-Pil Park as Vice President of Production.

“The addition of these highly talented executives is a continuation of Park’s strategic business focus on global expansion,” states Dr. Sang-il Park, Park Systems Founder and CEO. “The new appointments establish the groundwork for an integrated world-wide targeted sales operation and will jointly aggressively increase our production capabilities to meet anticipated product demands.”

Charlie Park’s role as Senior Vice President of Global Sales will focus on further establishing Park Systems trademarked global Atomic Force Microscope (AFM) brand. He brings over three decades of global sales and marketing experience at leading companies including Samsung Electronics where during his tenure as Senior VP he expanded global operations, leading the sales & marketing divisions in both the Korean and European Headquarters. He has had numerous global assignments in the UK, Germany and the Netherlands and will use his successful global sales experience to implement Park’s long-term strategy for growth and innovation leadership in Atomic Force Microscopes.

Jong-Pil Park, PhD-ME, newly appointed Vice President of the Production Division will expand the highly successful production capabilities of Park AFM with quality-driven state-of-the-art systems and leading-edge performance capabilities. His successful 30 year career as an engineering-based expert in production and quality management include operations vice president at Motorola Korea, production VP at Doosan Infracore Co and at Huneed Technologies Company, and a senior engineer at Defense Technology & Quality. His leadership skills combined with technical knowledge of automated atomic force microscope equipment will expand Park Systems world-renowned production systems to meet the AFM needs for an expanding world market.

Scientists at the U.S. Naval Research Laboratory (NRL) have devised a clever combination of materials — when used during the thin-film growth process — to reveal that particle atomic layer deposition, or p-ALD, deposits a uniform nanometer-thick shell on core particles regardless of core size, a discovery having significant impacts for many applications since most large scale powder production techniques form powder batches that are made up of a range of particles sizes.

Image shows high magnification bright field transmission electron microscopy (TEM) image showing obvious delineation of alumina film and surface of particle. Credit: (US Naval Research Laboratory)

Image shows high magnification bright field transmission electron microscopy (TEM) image showing obvious delineation of alumina film and surface of particle. Credit: (US Naval Research Laboratory)

“Particle atomic layer deposition is highlighted as a technology that can create new and exciting designer core/shell particles to be used as building blocks for the next generation of complex multifunctional nanocomposites,” said Dr. Boris Feygelson, research engineer, NRL Electronics Science and Technology Division. “Our work is important because shell-thickness is most often a crucial parameter in applications where core-shell materials can be used to enhance performance of future materials.”

Atomic layer deposition is a layer-by-layer chemical vapor deposition-based thin-film growth technique used extensively in the electronics industry to deposit nanometer-thick films of dielectric materials on devices. Combined with other deposition and shadowing masking techniques, ALD is an integral part of electronic chip and device manufacturing. The same gas-phase process can be applied in a rotary or fluidizing powder bed reactor to grow nanometer-thick films that are highly conformal and uniformly thick on individual particles.

Previous research on p-ALD, patented by ALD NanoSolutions, Inc., has shown that growth of each layer during the deposition process varies with particle size, with the underlying assumption that larger particles will always have less growth. To observe this growth phenomenon, the NRL team grew alumina on nano- and micron-sized particles of tungsten and measured the shell thickness in a transmission electron microscope. Because of the huge mass/density difference of the two materials, this pairing provides maximum contrast in the electron microscope and delineation was easily distinguishable between the particle core and shell.

In their research, the scientists created core and shell powders consisting of a tungsten particle core and thin alumina shell that were then synthesized using atomic layer deposition in a rotary reactor. Standard atomic layer deposition of trimethylaluminum and water was performed on varying batches of powder with different average particle sizes.

“Amazingly, we found that the growth per cycle of the alumina film on an individual particle in a batch was shown to be independent of the size of an individual particle, and therefore, a powder batch — which consists of particles sizes spanning orders of magnitude — has constant shell thicknesses on all particles. This result upsets the current understanding of ALD on particles,” said Dr. Kedar Manandhar, ASEE postdoc, NRL Electronics Science and Technology Division and leading author of the research paper.

The work, published recently in the Journal of Vacuum Science and Technology A, suggests that water, a reactant in the ALD process, is reason for the same rate of growth on different particles. This uniformity of thickness on different particle sizes in a particular batch is determined to be due to the difficulty of removing residual water molecules from the powder during the purging cycle of the atomic layer deposition (ALD) process. “Water is very sticky and it is very difficult to remove the last mono-layer from surfaces,” Feygelson says. “And when you have a tumbling bed of powders, the water sticks around between the particles and results in consistent shell growth in the tumbling powder.

Applications for this research demonstrate implications for use in materials like abrasion resistant paints, high surface area catalyst, electron tunneling barriers, ultra-violet adsorption or capture in sunscreens or solar cells and even beyond when core-shell nanoparticles are used as buildings blocks for making new artificial nanostructured solids with unprecedented properties.

The Electronic System Design (ESD) Alliance (formerly the EDA Consortium) and Semico Research today announced that they have entered into a joint marketing agreement (JMA) to work together on several business initiatives in support of the semiconductor design ecosystem.

The JMA will enable the ESD Alliance and Semico, a semiconductor marketing and consulting research company noted for its coverage of the intellectual property (IP) market, to promote their common business goals. Semico will assist the ESD Alliance in broadening its reach into the IP community, a large part of the semiconductor design ecosystem, by promoting it at Semico events, on its website and through promotional emails.

Additionally, Semico will provide a discount to ESD Alliance members for purchase of individual research reports, offer enterprise-wide access to its IPI Monthly Report and extend admission discounts to Semico conference events.

In exchange, Semico has become an associate member of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem. The ESD Alliance will post availability of new Semico research reports and provide a link to its website for Semico blogs and articles.

“Semico is connected to and understands the needs of IP community,” says Bob Smith, the ESD Alliance’s executive director. “Our new mission is focused on representing the design ecosystem and IP is a key component. We will rely on its Semico’s expertise as we expand our presence and showcase our benefits to IP vendors and suppliers.”

“The ESD Alliance recognizes that the IP community is an important element of the semiconductor design ecosystem and one that will benefit from its newly expanded charter and ongoing initiatives,” notes Jim Feldham, president of Semico. “We look forward to working with the the ESD Alliance to raise the visibility of the importance of the IP market.”

For more information on other aspects of the ESD Alliance and Semico partnership, visit: www.esd-alliance.org or www.semico.com.

By David W. Price, Douglas G. Sutherland and Kara L. Sherman

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which explored the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing. For this article, we are pleased to include insights from our guest author, Kara Sherman.

As we celebrate Earth Day 2016, we commend the efforts of companies who have found ways to reduce their environmental impact. In the semiconductor industry, fabs have been building Leadership in Energy and Environmental Design (LEED)-certified buildings [1] as part of new fab construction and are working with suppliers to directly reduce the resources used in fabs on a daily basis.

As IC manufacturers look for more creative ways to reduce environmental impact, they are turning to advanced process control solutions to reduce scrap and rework, thereby reducing fab resource consumption. Specifically, fabs are upgrading process control solutions to be more capable and adding additional process control steps; both actions reduce scrap and net resource consumption per good die out (Figure 1).

Figure 1. The basic equation for improving a fab’s environmental performance includes reducing resource use and increasing yield. Capable process control solutions help fabs do both by identifying process issues early thereby reducing scrap and rework.

Figure 1. The basic equation for improving a fab’s environmental performance includes reducing resource use and increasing yield. Capable process control solutions help fabs do both by identifying process issues early thereby reducing scrap and rework.

Improved process control performance

Process control is used to identify manufacturing excursions, providing the data necessary for IC engineers to make production wafer dispositioning decisions and to take the corrective actions required to fix process issues.

For example, if after-develop inspection (ADI) data indicate a high number of bridging defects on patterned wafers following a lithography patterning step, the lithography engineer can take several corrective actions. In addition to sending the affected wafers back through the litho cell for rework, the engineer will stop production through the litho cell to fix the underlying process issue causing the yield-critical bridging defects. This quick corrective action limits the amount of material impacted and potentially scrapped.

To be effective, however, the quality of the process control measurement is critical. If an inspection or metrology tool has a lower capture rate or higher total measurement uncertainty (TMU), it can erroneously flag an excursion (false alarm), sending wafers for unnecessary rework, causing additional consumption of energy and chemicals and production of additional waste. Alternatively, if the measurement fails to identify a true process excursion, the yield of the product is negatively impacted and more dies are scrapped—again, resulting in less desirable environmental performance.

The example shown in Figure 2 examines the environmental impact of the process control data produced by two different metrology tools in the lithography cell. By implementing a higher quality metrology tool, the quality of the process control data is improved and the lithography engineers are able to make better process decisions resulting in a 0.1 percent reduction in unnecessary rework in the litho cell. This reduced rework results in a savings of approximately 0.5 million kWh of power and 2.4 million liters of water for a 100k WSPM fab—and a proportional percentage reduction in the amount of resist and clean chemicals consumed.

Figure 2. Higher quality process control tools produce better process control data within the lithography cell, enabling a 0.1 percent reduction in unnecessary rework that results in better environmental performance.

Figure 2. Higher quality process control tools produce better process control data within the lithography cell, enabling a 0.1 percent reduction in unnecessary rework that results in better environmental performance.

As a result of obtaining increased yield and reduced scrap, many fabs have upgraded the capability of their process control systems. To drive further improvements in environmental performance, fabs can benefit from utilizing the data generated by these capable process control systems in new ways.

Traditionally, the data generated by metrology systems have been utilized in feedback loops. For example, advanced overlay metrology systems identify patterning errors and feed information back to the lithography module and scanner to improve the patterning of future lots. These feedback loops have been developed and optimized for many design nodes. However, it can also be useful to feed forward (Figure 3) the metrology data to one or more of the upcoming processing steps [2]. By adjusting the processing system to account for known variations of an upcoming lot, errors that could result in wafer scrap are reduced.

For example, patterned wafer geometry measurement systems can measure wafer shape after processes such as etch and CMP and the resulting data can be fed back to help improve these processes. But the resulting wafer shape data can also be fed forward to the scanner to improve patterning [3-5]. Likewise, reticle registration metrology data can be used to monitor the outgoing quality of reticles from the mask shop, but it can also be fed forward to the scanner to help reduce reticle-related sources of patterning errors. Utilizing an intelligent combination of feedforward and feedback control loops, in conjunction with fab-wide, comprehensive metrology measurements, can help fabs reduce variation and ultimately obtain better processing results, helping reduce rework and scrap.

Fig 3

Figure 3. Multiple data loops to help optimize fab-wide processes. Existing feedback loops (blue) have existed for several design nodes and detect and compensate for process variations. New, optimized feedback loops (green) provide earlier detection of process changes. Innovative feed forward loops (orange) utilize metrology systems to measure variations at the source, then feed that data forward to subsequent process steps.

Earlier excursion detection reduces waste

Fabs are also reducing process excursions by adding process control steps. Figure 4 shows two examples of deploying an inspection tool in a production fab. In the first case (left), inspection points are set such that a lot is inspected at the beginning and end of a module, with four process steps in between. If a process excursion that results in yield loss occurs immediately after the first inspection, the wafers will undergo multiple processing steps, and many lots will be mis-processed before the excursion is detected. In the second case (right), inspection points are set with just two process steps in between. The process excursion occurring after the first inspection point is detected two days sooner, resulting in much faster time-to-corrective action and significantly less yield loss and material wasted.

Furthermore, in Case 1, the process tools at four process steps must be taken off-line; in Case 2, only half as many process tools must be taken offline. This two-day delta in detection of a process excursion in a 100k WSPM fab with a 10 percent yield impact results in a savings of approximately 0.3 million kWh of power, 3.7K liters of water and 3500 kg of waste. While these environmental benefits were obtained by sampling more process steps, earlier excursion detection and improved environmental performance can also be obtained by sampling more sites on the wafer, sampling more wafers per lot, or sampling more lots. When a careful analysis of the risks and associated costs of yield loss is balanced with the costs of additional sampling, an optimal sampling strategy has been attained [6-7].

Figure 4. Adding an additional inspection point to the line will reduce the material at risk should an excursion occur after the first process step.

Figure 4. Adding an additional inspection point to the line will reduce the material at risk should an excursion occur after the first process step.

Conclusion

As semiconductor manufacturers focus more on their environmental performance, yield management serves as a critical tool to help reduce a fab’s environmental impact. Fabs can obtain several environmental benefits by implementing higher quality process control tools, combinations of feedback and feedforward control loops, optimal process control sampling, and faster cycles of learning. A comprehensive process control solution not only helps IC manufacturers improve yield, but also reduces scrap and rework, reducing the fab’s overall impact on the environment.

References

  1. Examples:
    1. https://newsroom.intel.com/news-releases/intels-arizona-campus-takes-the-leed/
    2. http://www.tsmc.com/english/csr/green_building.htm
    3. http://www.ti.com/corp/docs/manufacturing/RFABfactsheet.pdf
    4. http://www.globalfoundries.com/about/vision-mission-values/responsibility/environmental-sustainability-employee-health-and-safety
  1. Moyer, “Feed It Forward (And Back),” Electronic Engineering Journal, September 2014. http://www.eejournal.com/archives/articles/20140915-klat5d/
  2. Lee et al, “Improvement of Depth of Focus Control using Wafer Geometry,” Proc. of SPIE, Vol. 9424, 942428, 2015.
  3. Tran et al, “Process Induced Wafer Geometry Impact on Center and Edge Lithography Performance for Sub 2X nm Nodes,” 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, 2015.
  4. Morgenfeld et al, “Monitoring process-induced focus errors using high resolution flatness metrology,” 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, 2015.
  5. “Process Watch: Sampling Matters,” Semiconductor Manufacturing and Design, September 2014.
  6. “Process Watch: Fab Managers Don’t Like Surprises,” Solid State Technology, December 2014.
  7. “Reducing Environmental Impact with Yield Management,” Chip Design, July 2012.

About the Authors:

Dr. David W. Price, Dr. Douglas Sutherland, and Ms. Kara L. Sherman are Senior Director, Principal Scientist, and Director, respectively, at KLA-Tencor Corp. Over the last 10 years, this team has worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements

IC Insights recently released its new Global Wafer Capacity 2016-2020 report that provides in-depth detail, analyses, and forecasts for IC industry capacity by wafer size, by process geometry, by region, and by product type through 2020.  In 2008, 300mm wafers took over as the industry’s primary wafer size in terms of total surface area used. Furthermore, the number of 300mm wafer fabrication facilities in operation continues to grow and is expected to reach 100 this year (Figure 1).

Some highlights regarding 300mm wafer fabs are shown below.

•    A couple fabs that were scheduled to open in 2013 were delayed until 2014.  That, in conjunction with the closure of two large 300mm fabs by ProMOS in 2013, caused the number of active volume-production 300mm fabs to decline for the first time in 2013.

•    At the end of 2015, there were 95 production-class IC fabs utilizing 300mm wafers (there are numerous R&D IC fabs and a few high-volume fabs that make “non-IC” products such as CMOS image sensors using 300mm wafers, but these are not included in the count).

•    Currently, there are eight 300mm wafer fabs scheduled to open in 2017, which would be the highest single-year increase since 2014 when nine 300mm fabs were added.

•    By the end of 2020 there are expected to be 22 more 300mm fabs in operation, bringing the total number of 300mm fabs used for IC fabrication to 117.  If 450mm wafers enter production, the peak number of 300mm fabs may be somewhere around 125.  For comparison, the highest number of volume-production 200mm wafer fabs in operation was 210 (in December of 2015 there were 148).

Today’s 300mm wafer fabs can be huge, but they are being equipped in a modular format, with each “module” generally having the capacity to process somewhere around 25K-45K wafers per month.  Each module is closely connected to nearby fab modules.  TSMC has perfected this modular approach, with its Fab 12, 14, and 15 sites being expanded in phases.

Figure 1

Figure 1

Development of 450mm wafer technology continues to progress toward production, albeit at a tempered pace. Since lithography is one of the biggest challenges in the 450mm wafer transition, ASM Lithography’s announcement in March 2014 that it would temporarily hold off on the development of equipment for 450mm wafers made some in the industry believe it was a signal that the transition would never happen.  ASML reported also that the decision to postpone its 450mm development program was made at the request of its customers.

IC Insights does not believe that ASML’s announcement, along with a couple other signs of a pause in 450mm development, means the 450mm wafer transition won’t happen, but they do indicate that the pilot production status for 450mm won’t be reached until probably 2019.  Volume production might start two to three years after that.

IC Insights’ Global Wafer Capacity 2016-2020—Detailed Analysis and Forecast of the IC Industry’s Wafer Fab Capacity report assesses the IC industry’s capacity by wafer size, minimum process geometry, technology type, geographic region, and by device type through 2020. The report includes detailed profiles of the companies with the greatest fab capacity and gives comprehensive specifications on existing wafer fab facilities.

Nanoelectronics research center imec and Crystal Solar, a pioneer in direct wafer growing technologies for the next generation of solar photovoltaic products, today announced that they have achieved a 22.5 percent cell efficiency (certified by FhG ISE CalLab) with nPERT silicon (Si) solar cells manufactured on 6-inch mono-crystalline epitaxially grown kerfless wafers. Marking an industry first, imec and Crystal Solar have demonstrated the highest efficiency to-date for homojunction solar cells on epitaxially grown silicon wafers, paving the way toward industrialization of this promising technology.

Crystal Solar’s breakthrough manufacturing technology called Direct Gas to Wafer enables direct conversion of feedstock gas to mono crystalline silicon wafers by high throughput epitaxial growth. By skipping the polysilicon, ingoting and the wire-sawing steps altogether, this approach not only results in lowest cost/watt for the wafers but also significantly reduces the capital required to set up a manufacturing plant. Furthermore, this process enables the growth of high quality p-n junctions in-situ which reduces cell making steps while increasing the efficiency.

Imec has adapted its highly efficient nPERT Si solar cell process to align with the properties of Crystal Solar’s kerfless wafers. The 156x156mm2 cells were fabricated on 160 to 180 um thick grown n-type wafers with built-in rear p+ emitter. Imec’s n-PERT process included a selective front surface field realized by laser doping, advanced emitter surface passivation by Al2O3 and Ni/Cu plated contacts. The novel process using all industrially available processing steps resulted in record efficiencies for homojunction large area solar cells of 22.5 percent and a record Voc of 700mV. This high Voc illustrates the high quality of the wafers and the built-in junction.

Jozef Szlufcik, PV Department Director at imec: “We are extremely happy to have achieved such high conversion efficiencies on nPERT solar cells processed from kerfless wafers using imec’s pre-pilot industrial silicon PV manufacturing line. The combination of our advanced cell process and the innovative wafer manufacturing technique of Crystal Solar, is paving the way for manufacturing of highly efficient solar cells at substantially lower cost and will be disruptive for the complete solar manufacturing value chain.”

“We are pleased to see such a high conversion efficiency on our epitaxially grown n-type wafers with built in boron doped junctions,” said T.S. Ravi, CEO of Crystal Solar. “This approach represents a new paradigm in cell manufacturing with its unique ability to bypass significant steps in both wafer and cell manufacturing thereby dramatically reducing the capex and the overall cost per watt.  We expect to achieve >23% efficiencies with IMEC’s PERT technology in the very near future,” Mr. Ravi concluded.

By Paul Trio (SEMI); Dalia Vernikovsky (Applied Seals NA)

Evolving Industry Priorities

As the microelectronics industry becomes more mature and products become more advanced, there is greater emphasis on improving process control deeper within the supply chain. Whereas much of the attention has historically been at the fab as well as on equipment and materials, the spotlight is now focused on components and subcomponents.

As the industry prepares for 7nm and beyond, there is a realization that high-volume manufacturing at these advanced process nodes will be gated by equipment parts performance. With device manufacturers refining advanced process recipes pushing equipment, components, and subcomponents to the fringes of their performance envelopes, control is paramount. Industry standards will be as important in providing consistent parameters to enable users to compare similar parts and assess performance differences.

The Seal Situation

The subcomponent industry challenge outlined above certainly rings true for elastomeric seals. “Seals were invented near the end of the 19th century and the disturbing fact is that their manufacturing, material composition, and overall position in the vast industry is industrial in nature,” said Dalia Vernikovsky (Applied Seals North America), SCIS co-chair,  “Unless this industry comes together to forge guidelines or standards that correlate to SEMI’s stringent applications, and we bring the awareness that seal language still correlates to the mechanical make-up (thus the metal adders and constituents of things such as magnesium ferrous oxides), not the cleanliness specifications required, 7nm manufacturing will see defects traced to those components long after they are incorporated.”

Sealed with a Standard

With a myriad of applications and a variety of options, it is often difficult for users to select appropriate sealing materials. This problem is further compounded when O-ring suppliers use different criteria for quantifying O-ring performance coupled with inconsistent parameters and test methods. Control is key: making the right choice is essential for improving equipment uptime and reducing operational costs.

SEMI F51, Guide for Elastometric Sealing Technology, has been in publication since early 2000. This Document is a basic guide for the use of seals in semiconductor fabrication equipment. However, in order to meet the latest customer requirements, the standard needed an overhaul.

In 2014, the F51 Revision Task Force, under the North America Facilities Technical Committee Chapter was chartered to bring the standard to current industry specs. After a few ballot attempts, the task force’s 5080B proposal passed technical committee review at SEMICON West 2015 (July). By fall, the 5080B Ratification Ballot met the required acceptance conditions as well as clearing the necessary procedural reviews by the ISC Subcommittee on Audits & Reviews. The latest version of SEMI F51was published in November 2015 is now available for purchase from SEMI. It defines the criteria by which sealing performance can be judged in comparable measurements and seal materials can be chosen.

Behind the Scenes: A SEMI Special Interest Group

Determining how the SEMI F51 Standard would be revised didn’t happen overnight. Even before the F51 Revision Task Force was chartered, another SEMI group architected the characterization of seals parameters required at these advanced process nodes.

The Seals Group first identified seal performance criteria in several applications or process areas. The performance criteria was mainly divided into two groups: sealing requirements (e.g., etch rate, sealing force retention) and impurities (e.g., leachable, ash, outgassing, total organic carbon [TOC] testing). Process areas included: wet etch, etch, CVD/PVD, diffusion, and sub-fab.

Once the parameters were identified, the group prioritized which characteristics it needed to focus on. These included TOC, surface extractable metal contamination, and ash metal analysis. The Seals Group then developed test methodologies for measuring each performance. If test methods or standards already existed, the group simply referenced them.

Relative Importance of Seal Performance Criteria in Several Applications/Process Areas (1 – most important, 5 – least important) Figure 1

The Seals Group is part of a SEMI Special Interest Group (SIG) focused on Semiconductor Components, Instruments, and Subsystems (SCIS). SEMI SIGs provide a forum that fosters discussion and aligns stakeholders on industry-critical issues. SCIS represents companies that produce, package and/or distribute any of the following used in semiconductor or related industries:

  • Components such as seals, filters, mass flow controllers, valves, sensors, ion beam sources, etc.
  • Instruments for in-line and off-line data measurement, collection, and monitoring
  • Sub-systems that support process tools such as vacuum, robotics, power conversion, abatement, chillers, etc.

SCIS participation encompass Subcomponent-OEM-IDM stakeholders, including: Applied Seals NA; ASM; Brooks Automation; Busch Vacuum; Ebara; Edwards Vacuum; Entegris; Festo; GLOBALFOUNDRIES; Greene, Tweed; Horiba; Intel; KLA-Tencor; Lam Research; Pall; Parker; SMC; Swagelok; Texas Instruments; UltraClean Technology; VAT Valve.

SEMI SCIS SIG – Addressing Defectivity Problems in HVM

With defect and traceability playing a critical role in enabling high-volume manufacturing, SCIS is currently structured to focus on these problem areas. It aims to establish a framework that will enable industry partners to define:

  • Measurable defects for different components specific to intended process applications
  • Standardized test methods to measure the defects
  • Consistent methods for reporting the results

“Increased collaboration is required to establish new industry standards and parameters associated with semiconductor process control to meet the ever increasing yield, variability, and reliability challenges that comes with continued technology scaling,” said Gary Patton, CTO and SVP of WW R&D at GLOBALFOUNDRIES. “The SEMI SCIS group is playing a very crucial role in driving alignment between semiconductor manufacturers and equipment and sub-component suppliers on successful standards for sub-component defectivity and traceability needed for future technology nodes.”

The Seals Group is just one of four subteams under SCIS focused on defectivity. Subteams are established in the following areas:

  • Valves, Seals, and Pumps
  • Liquid and Gas Delivery
  • Critical Chamber Components and RF
  • Automation

As of this writing, each SCIS subteam has identified at least one process-critical component considered to be a primary contributor to defects:

Scope of Defectivity Components Figure 2

The subteams are now focusing on establishing a standard system of comparable metrics which will be used to rate, compare, and classify each of these identified components. This process is dictated by the following template:

SCIS Defectivity Template Figure 3

The Seals Group is not resting on its laurels with the latest revision to SEMI F51. The Seals team is now working on the next set of parameters including: sealing force retention, etch rate (range), permeation, and particles (size and range).

Visibility with Traceability

SCIS is also addressing the need for improved component parts traceability that will enable effective problem diagnosis and faster resolution.

Consider this rather common scenario: Fab yield excursion is traced to a batch of custom machined parts manufactured by Supplier A on a pump supplied by Supplier B on a process tool manufactured by Supplier C.  Fab engineer requests Supplier C to provide a list of all affected systems and spares to enable global containment plan. Without a standardized traceability process in place, the list takes a week to compile, introducing delays to the corrective action. 

The Traceability Verification Subteam under SCIS is chartered to implement an industry standard parts traceability process that will:

  • Define standardized formats and protocols
  • Facilitate communication among suppliers, OEMs, and IDMs.
  • Enable efficient problem diagnosis and resolution

“The Traceable Verification Model ensures Key Characteristics are controlled with compliance information easily accessed via a cloud based application. Intellectual property is secured via pre-approved access levels. The model holds all suppliers accountable but also ensures proprietary information is not compromised.” said Lance Dyrdahl (Lam Research), Defect Traceability Subteam leader.

Full Circle Engagement

As with the F51 seals activity, output from these SCIS Subteams will feed in to the various committees and task forces under the SEMI International Standards Program. As these Standards are used by the industry, new requirements will emerge and it will be up to SEMI Members to address them.

“Components standards should be effectively linked to the field performance for all-around benefits to component makers, OEMs and IDMs. The committee deliverables are structured to allow competitors to work together in driving commonality. Standardization and normalization methodology will provide IP-free participation.” said Ya-hong Neirynck (Intel), SCIS RF subteam co-leader. Lance Dyrdahl further pointed out, “Speedy ratification occurs when all participants agree on self-evident non-proprietary methods.”

The demands of the next-generation high-volume manufacturing will no doubt require a concerted effort among device manufacturers, OEMs, and suppliers. Diverse stakeholder participation is critical in solving these problems proactively. Failure to do so will certainly result in greater challenges (and pain) that will be shared by all.  “A piece of equipment or process line is only as strong as its weakest component,” said Sanchali Bhattacharjee (Intel), SCIS cochair.

Engaging in these SEMI SCIS initiatives provides a very strong value proposition for IDM-OEM-suppliers alike.

Engaging in SEMI SCIS Benefits All Industry Stakeholders Figure 4

The SEMI SCIS Special Interest Group is open to all SEMI Members. There will be an SCIS face-to-face meeting in conjunction with the SEMI Advanced Semiconductor Manufacturing Conference (ASMC) – May 16-19, 2016 – in Saratoga Springs, New York. Conference attendees are welcome to attend this face-to-face meeting. Future face-to-face meeting are also scheduled for SEMICON West 2016 (July) as well as the SEMI Strategic Materials Conference (SMC) in September. SCIS subteams meet via teleconference in between these face-to-face meetings. For more information or to join the SCIS SIG, please contact Paul Trio at SEMI ([email protected]).

Rudolph Technologies, Inc. today announced the availability of new, high-speed 3D metrology on its flagship NSX Series, a highly-flexible inspection and measurement platform for process development and control of die-level interconnects. Already in use by multiple customers worldwide, the NSX Series with high-speed 3D metrology is capable of both high-volume production monitoring and advanced process development.

“The new capability provides a 200-400 percent throughput improvement over our previous Wafer Scanner bump metrology system, and when paired with our Discover Software, provides a complete coplanarity solution for our customers,” said Scott Balak, Rudolph’s director, inspection product management. “With the increasing number of new packaging technologies being developed by foundries, outsourced assembly and test (OSAT) manufacturers, and integrated device manufacturers (IDMs), the flexibility and reliability of this new capability on the trusted NSX Series platform is especially valuable to customers seeking to move rapidly from pilot lines to production.”

Data is collected in seconds from millions of bumps and then analyzed by Rudolph’s Discover Software analysis database. Engineers gain unique insight into critical metrology applications, from both an individual bump point of view or holistically as a wafer, as part of a simultaneous product and process control solution.

“Manufacturers are looking for a more comprehensive and flexible process control solution that provides, not only inspection or bump data, but also usable analytical information about their processes,” said Mike Goodrich, vice president and general manager of Rudolph’s Process Control Group. “Our powerful Discover analysis software provides insight into the process that is otherwise unavailable to process control tool owners. The high-speed 3D bump metrology capability incorporates a three segment optical range, giving our customers the flexibility to control both smaller micro bumps and larger traditional solder bumps with a single inspection and metrology platform. When combined with Rudolph’s advanced automation capability, customers can measure thin and warped wafers without the extra expense of frame and tape mounting.”

Goodrich concluded, “We understand the importance of 3DIC and next-generation packaging processes and we have aggressively pursued development of this comprehensive 3D coplanarity solution to meet our customers’ needs for a cost efficient, multi-functional process control tool.”