Category Archives: MEMS

April 17, 2012 — The new laser lithography tool from Nanoscribe GmbH produces complex 3D submicron structures up to 1mm with 150nm widths, boasting full automation and precise repeatability. It is based on a 3-axis piezo nano-positioning stage from PI (Physik Instrumente).

The PImars P-563 flexure-guided, piezo-driven nanopositioning XYZ stage provides positioning ranges to 300 x 300 x 300µm and nanometer-range repeatability. A parallel-metrology position feedback system based on highly linear capacitive sensors allows the sample to be moved precisely and repeatedly in relation to the laser focus. A digital piezo motion controller provides path control.

The tool can be used to construct biometric characteristics or to create microstructures for small pumps and needles.

More information on XYZ piezo nano-positioning systems is available at http://www.nanopositioning.net/XYZ_nanopositioning_stage.php#P563

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April 16, 2012 – Marketwire — IC and MEMS maker Micrel, Inc. (NASDAQ:MCRL) received a 98% performance rating for its services and materials to a leading global micro electro mechanical systems (MEMS) designer and manufacturer in in a report covering Q4 2011.

Micrel mass produces MEMS sensors for the customer, which supplies sensors and sensor-based systems powered by MEMS devices. The customer, which was not named in Micrel’s release, is ranked among the top 20 global MEMS device makers.

Rating metrics are based on returns (30%), on-time delivery (30%), quality (20%) and quality events (20%).

Micrel has received 2 scorecards (the first was 97%) from the customer since expanding its San Jose, CA, MEMS 6” wafer and foundry operations in November 2011. Micrel is aiming for 100% on its customer scorecards, but is “pleased with our performance out of the gate on MEMS,” said Guy Gandenberger, VP, worldwide operations and foundry business unit for Micrel, who noted the improvement from their last scorecard.

Micrel invested several million dollars in capital for the MEMS fab ramp up, initiating 3D front-to-back wafer alignment capability and acquiring a state-of-the-art deep reactive ion etch (DRIE) tool to fab very deep trenches, through silicon vias (TSV), and large cavities required in MEMS designs.

The fab gives Micrel “greater control and flexibility over every element of the manufacturing process,” enables highly customizable services for CMOS and MEMS device customers, and reduces the number of vendors in a customer process, added Ray Zinn, president and CEO of Micrel. Micrel’s Wafer Fab Division facility is certified to ISO14001:1996, the International Environmental Management System Standard.

Micrel Inc. is a global IC manufacturer for analog, Ethernet and high bandwidth markets. Internet: http://www.micrel.com.

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April 13, 2012 — Georgia Institute of Technology researchers have used magnetic repulsion force as a fixtureless, noncontact tool for measuring the adhesion strength between thin films in microelectronic devices, photovoltaic cells, and micro electro mechanical systems (MEMS).

The magnetically actuated peel test (MAPT) could help electronics engineers understand and predict delamination/debonding, and improve resistance to thermal and mechanical stresses.

Figure 1. A specimen fabricated for the magnetically actuated peel test (MAPT). The silver cylinder in the center is the permanent magnet. SOURCE: Thin Solid Films.

The right materials will enable smaller, higher-performance, reliable electronic devices, said Suresh Sitaraman, a professor in the George W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology. “This technique would help manufacturers know that their products will meet reliability requirements, and provide designers with the information they need to choose the right materials to meet future design specifications over the lifetimes of devices.”

Thermal stresses occur when different layers within an electronic device have mismatched coefficients of thermal expansion (CTE), and will cause layers to separate. Researchers want to know if these layers will separate as the device is used over time, eventually causing failure, said Sitaraman.

Figure 2. Georgia Tech School of Mechanical Engineering professor Suresh Sitaraman (left) and doctoral student Gregory Ostrowicki (right) examine a specimen (seen in Figure 1) fabricated for the magnetically actuated peel test (MAPT). SOURCE: Thin Solid Films.

Sitaraman and doctoral student Gregory Ostrowicki have used their technique to measure the adhesion strength between layers of copper conductor and silicon dioxide (SiO2) insulator. They also plan to use it to study fatigue cycling failure, which occurs over time as the interface between layers is repeatedly placed under stress. The technique may also be used to study adhesion between layers in photovoltaic systems and in MEMS devices.

The Georgia Tech researchers used standard microelectronic fabrication techniques to grow layers of thin films that they want to evaluate on a silicon wafer. At the center of each sample, they bonded a tiny permanent magnet made of nickel-plated neodymium (NdFeB), connected to three ribbons of thin-film copper grown atop silicon dioxide on a silicon wafer.

The sample was then placed into a test station comprising an electromagnet below the sample and an optical profiler above. Voltage supplied to the electromagnet was increased over time, creating a repulsive force between the like magnetic poles. Pulled upward by the repulsive force on the permanent magnet, the copper ribbons stretched until they finally delaminated.

With data from the optical profiler and knowledge of the magnetic field strength, the researchers can provide an accurate measure of the force required to delaminate the sample. The magnetic actuation has the advantage of providing easily controlled force consistently perpendicular to the silicon wafer.

Many samples can be made at the same time on the same wafer, generating a quantity of adhesion data in a timely fashion.

To study fatigue failure — a common failure mode wherein delamination occurs over time with repeated heating and cooling cycles, Sitaraman and Ostrowicki plan to cycle the electromagnet’s voltage on and off. “A lot of times, layers do not delaminate in one shot,” Sitaraman said. “We can test the interface over hundreds or thousands of cycles to see how long it will take to delaminate and for that delamination damage to grow.”

The test station fits into an environmental chamber, allowing the researchers to evaluate harsh-environment electronics under the effects of high temperature and/or high humidity. “We can see how the adhesion strength changes or the interfacial fracture toughness varies with temperature and humidity for a wide range of materials,” Sitaraman explained.

Sitaraman and Ostrowicki have studied thin film layers about one micron in thickness, but say their technique will work on layers that are of sub-micron thickness. Because their test layers are made using standard microelectronic fabrication techniques in Georgia Tech’s clean rooms, Sitaraman believes they accurately represent the conditions of real devices. These are representative processes and representative materials, mimicking the processing conditions and techniques used in actual microelectronics fabrication.

“As we continue to scale down the transistor sizes in microelectronics, the layers will get thinner and thinner,” he said. “Getting to the nitty-gritty detail of adhesion strength for these layers is where the challenge is. This technique opens up new avenues.”

The research has been supported by the National Science Foundation, and was reported in the March 30, 2012 issue of the journal Thin Solid Films.

Learn more about Georgia Institute of Technology at http://www.gatech.edu/.

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April 13, 2012 — Blogger Michael A. Fury, Techcet Group, reports from the MRS Spring 2012 meeting in San Francisco. Highlights from the fourth day: nanowire FETs, laminate MEMS, nanoparticles in security printing, graphene nanoribbons, Ta2O5 memristors, redox flow batteries, graphene, and more.

MRS Spring:

Day 1

Day 2

Day 3

Day 4 of the MRS Spring 2012 meeting opened Thursday at Moscone West in San Francisco under sunny skies and a brief rain shower, after a stormy night of heavy rain. No scientists were lost in landslides in the surrounding hills.

AA7.1 Charles Lieber at Harvard University took us on a tour of the frontier between biology and nanotechnology. The field effect transistor (FET) structure is readily adaptable to monitoring basic biological signals. Nanowire FETs can bring us into the regime of 10nm active length detectors with diameters of 3-5nm. Devices have been demonstrated with femtomolar sensitivity to specific cancer markers, and 100-billion-fold discrimination in blood serum separation. Nanowire growth can be periodically slowed to introduce dopants with sharp interfaces, enabling pn junctions along the length of a single wire. These nano devices allow recording in a regime where the active device area is much smaller than the membrane area per ion channel. The wires can be shaped by altering the crystal growth, like a plumber bending pipes at the atomic level. Measurements were shown of electrical activity in a live beating-heart cell. Nanowires can be attached to probe arms and integrated into measurement circuitry for routine measurements, to the extent that probing a living brain or heart will ever be routine. The nanotube probe tip can also be joined directly as the gate of an FET, resulting in a “branched intracellular nanotube transistor” or BIT-FET. Nanotubes 2-3nm long achieve sufficient bandwidth to measure fast action potentials in cells. Extending these concepts to “cyborg tissue” will require fabrication of silicon and nanowire electronics on flexible, macro-porous substrates resembling biological scaffolds so that cells can interpenetrate with the addressable electronic matrix positions. Resistance is futile. Prepare to be assimilated. His stated objective is to blur the distinction between electronic devices, circuits, living cells and tissues.

B3.1 Guann-Pyng Li of University of California Irvine (UC Irvine) described several implementations of laminate micro electro mechanical systems (MEMS) for heterogeneous integrated systems. Mechanical frequency switching is likely to replace integrated circuitry as the band cutoff can be much more sharply defined. Microfluidic systems can be built up and integrated with conventional electronics dropped into place. Organic transistors can be fabricated in place on the laminated PCB substrates for on-board electronics. Vapor deposited pentacene for organic transistors costs $4000/g at the required 99.99% purity for an electron mobility ~3cm2/Vs. Solution deposition of pentacene uses 98% pure material at $20/g and gets you an electron mobility ~3cm2/Vs because solution processing has intrinsic purification properties. The choice is yours…

YY9.3 William Cross of the South Dakota School of Mines described the use of rare-earth-doped nanoparticles in security printing applications. The level of sophistication in covert authentication makes me wonder how counterfeiters can survive any more. Elements mentioned include Er, Yb, Tm and Y, so this technology poses no threat to the chemical mechanical polishing (CMP) CeO2 supply chain.

DD12.4 Iñigo Martin-Fernandez of Lawrence Berkeley National Laboratory (Berkeley Labs or LBNL) developed a method for direct growth of graphene nanoribbons (GNR) for device fabrication using 20nm-wide Ni catalyst patterned with an Al2O3 mask. Ribbons longer than 40µm were demonstrated, and selectivity to growth only on the catalyst was excellent.

E7.5 Antonio Torrezan of HP Labs shared his work on sub-nanosecond switching and energy efficiency in Ta2O5 memristors. A custom 20GHz testing apparatus was used to test the fast switching dynamics of memristors integrated into a coplanar waveguide. Reproducible resistance switching speeds ~100ps were demonstrated for both ON and OFF switching.

O7.6 Giu Yang of PNNL described a strategy for electrochemical energy storage and integration of renewable resources into grid applications. Electric cars address one mode of transportation energy, but only add to the grid capacity problem. Fortunately, an analysis of the usage modes and quality requirements shows that storage technologies can be optimized to address only one mode at a time, resulting in relatively bite-sized capacity to deal with. Redox flow batteries can be developed with a range of chemical components that can be stored separately in huge quantities until the power is needed. Such systems are typically operated at 1V or less to avoid hydrogen generation. Nafion is typically used as a separation membrane, but it allows too much cross-contamination between electrolytes as it is actually designed more for fuel cells. The many oxidation states of vanadium make it a most interesting system for designing redox systems that can be regenerated without requiring chemical separation. There is a long way to go, but the direction is promising.

EE7.1 Taishi Takenobu of Waseda U (Japan) showed some recent work on inkjet printing of single-wall carbon nanotubes (SWCNT) thin-film transistors (TFT). Separation of metallic from semiconducting CNT is required to avoid being trapped by a tradeoff between carrier mobility and on/off current ratio. Earlier work, which concluded that conductivity in high-density semiconducting CNT films was due to residual metallic CNT contamination, is disputed; rather, it is here proposed that it is due to unintentional doping of the CNT during the TFT fabrication process. A flexible ion gel CNT TFT built on polyimide underwent bend testing to a radius of 0.27mm at 178° (basically folded in half) suffered no degradation of on/off current ratio. Another TFT was built on SiO2 using S-CNT for gate and M-CNT for S/D. Performance with SiO2 gate dielectric was poor, while ion gel dielectric was good, indicating once again that CNT density itself is not the controlling factor in inkjet printed devices.

B5.2 Clint Landrock of Simon Fraser U (Canada) developed some autonomous function applications that integrate MEMS, ICs and organic photovoltaics (OPV) cells for low cost, flexible devices. These are fabricated and stored in air with no encapsulation and have shown stability beyond 2 years owing to a novel indium metal OPV cathode. Another component is a fast charging Na+ polymer supercapacitor ~100F/g developed in this group. The current energy cost for the system is estimated at $0.24/kWh, with a roadmap addressing known issues to take it to $0.01/kWh in 3-5 years.

II11.4 Daniel Collins of U Victoria (Canada) walked us through a focused ion beam (FIB) method for fabricating 2D and 3D graphene junctions with graphite that is non-destructive to the extremely delicate monolayer graphene. Fundamental studies will commence now that the fabrication method has been developed.

C10.5 Max Gage of Applied Materials described some modeling work on Cu through silicon via (TSV) CMP via reveal planarization. The model is designed for a single dielectric and circular via, but can be extended to other configurations. Separate equations are developed for each of three polishing regimes: pillar dielectric, Cu not exposed; pillar removal with Cu exposed but field not yet in contact with pad; and final planarization with field in full contact with pad. The model matches well with experimental data while allowing only the effective pattern density as an adjustable parameter.

EE7.6 Andrea Ferrari of U Cambridge spoke on graphene optoelectronics in applications ranging from ultrafast lasers to flexible displays. “Graphene will never replace silicon in our lifetime; that’s stupid.” Good thing. “Graphene Valley” lacks the cachet of “Silicon Valley.” But seriously… Graphene’s properties open up optical detection into the THz range (far IR). Graphene sheets have been fabricated into log normal antennae for effective capture of THz RF radiation, which may be applicable to security applications. The fast laser concept is based on the electroluminescence of graphene oxide, but the device itself remains hypothetical.

F12.3 Matthias Stender of Cabot Microelectronics described an enabling CMP process for GeSbTe (GST) phase-change random access memory (PRAM). GST has a Young’s modulus and shear modulus comparable to but slightly softer than Cu, and it does not form a protective oxide layer upon oxidation. An acceptable balance was found between oxidation and corrosion inhibition to remove the GST film uniformly without changing the GST composition remaining in the cells. Test structures were 30nm wide and 100nm deep in nitride. The slurry was based on colloidal SiO2 with H2O2 oxidizer; other additives are proprietary, though publication of a pending patent application is imminent. A high degree of customization is required for different GST compositions.

J13.10 Sangchul Lee of Gwangju Institute of Science & Technology (Korea) used patterned graphene as a transparent conducting electrode for organic TFT and OPV applications. Ni is used as an etch mask for O2 etch patterning, then the graphene electrodes are integrated with pentacene for an OTFT with reasonable performance, with higher mobility, lower contact resistance and higher injection efficiency than a comparable Au electrode device. Various surface pretreatments had a significant effect on the pentacene morphology and the associated OTFT performance. Fortunately, the highest mobility correlated with the lowest contact resistance. OPV devices benefitted from slight doping of the graphene layer and performed well under bending tests to 5mm radius.

Michael A. Fury, Ph.D. is director and senior technology analyst of Techcet Group.

Blogger Mike Fury reports from the MRS Spring 2012 meeting in San Francisco. Highlights from the third day: leakage and TDDB in low- κ dielectrics, flexible energy storage and conversion, Mn capping layers and diffusion barriers, hard masks for Cu interconnects, nanogenerators, Cu in RF, flexible temperature sensors, NEMS and MEMS in HDD, ZnO nanostructures, and various aspects of CMP.

Day 3 of the MRS Spring 2012 meeting opened Wednesday at Moscone West in San Francisco under partly sunny skies after an air-cleansing pre-dawn sprinkle. The halls were much more quiet and subdued than yesterday morning, suggesting a busy Tuesday night for all of the science bars in town.

C3.1 TM Shaw of IBM Watson Research opened the day with a reliability talk on leakage and TDDB in low-κ dielectrics. Leakage was measured with comb structures (60-100nm spaces) using step-wise voltage ramps; data recording started one minute after each step to eliminate charging transients. Over time, the Poole-Frenkel barrier height decreases continuously. At longer test times (>200 hours) the leakage data is more indicative of tunneling between trap sites; overlapping trap sites provide the leakage path. The rate of decrease of the Poole-Frenkel barrier height in early life testing was found to correlate well with TDDB behavior in longer time testing, and may serve as an early screening proxy.  Both moisture and Cu ions have a significant impact on time dependent leakage, but the magnitude of the leakage currents does not correlate well with TDDB lifetime.

C3.2 Sean King of Intel PTD studied the band diagram of the low-κ/Cu  system with XPS and REELS to elucidate some fundamental understanding of interconnect leakage mechanisms. He focused on the interface between Cu, the SiCON:H low-κ etch stop and the SiOC:H. Leakage through the etch stop was shown to dominate over direct via-to-via leakage through the Ta barrier and the dielectric. Future work will expand on the defect trapping states in this materials system. The talk concluded with an announcement that resumes of new graduates are welcome, as Intel needs to staff a new R&D facility currently under construction in Oregon.

C3.3 Brad Bittel of Penn State described some magnetic resonance studies of BEOL dielectrics; this work is a collaboration with Intel’s Sean King (above). Defects observed with EPR are likely important to leakage current as well as related reliability phenomena. SDT provides a direct link between EPR defects and electrical transport because only the centers involved in leakage can show up in SDT.

K3.5 Daniel Steingart of City College NY told us about flexible storage and energy conversion. Their approach was to focus on making the binders and electrodes flexible by embedding the MnO2 and Zn electrodes in a Ag-impregnated nylon mesh (this is the work I reported on earlier this week). This battery represents a conventional material set, but the Zn/MnO2 couple degrades over time as its charge/discharge cycles drive it to a stable equilibrium that is not a useful energy source. The limit seems to be ~600 cycles. Efforts to develop alternate material systems found adhesion failure between Al electrodes and a polymer/nanoparticle composite electrolyte in early test capacitors. It was resolved by using a seed layer of the nanoparticle alone as a surface roughening treatment to promote adhesion of the composite.

C4.1 Roy Gordon of Harvard U spoke on Mn capping layers and diffusion barriers in copper interconnects for TSV and on-chip vias, including a unique void-free via fill process.  The Mn CVD precursor for capping is a metal amidinate that deposits at 300°-350°C at 5 torr selectively on the Cu surface after passivating the dielectric with BDDS or DTS. Mn is a fast diffuser in Cu that migrates to SiO2 and Si3N4 interfaces, leaving the Cu resistivity after 400°C anneal at the pre-Mn level. Adhesion strength to the dielectric increases with Mn at the interface. An 8nm MnSixOy layer was shown to prevent both oxygen and moisture diffusion into the copper. Iodine-catalyzed copper bottom-up fill requires a copper seed layer before the mechanism can initiate. This work found that a seed layer of CVD Mn4N (Mn amidinate with NH3 at 130°C) will also adsorb the iodine sub-monolayer to initiate the CVD Cu fill at 180°C. Seam-free Cu fill was shown for <20nm vias with 5:1 AR, with large Cu grains across the entire via diameter prior to anneal. The Cu resistivity is lower than EP Cu due to the greater purity of CVD Cu. TSV copper fill was also demonstrated with AR>25:1 and 460mΩ/square Cu which exceeds the current roadmap.

C5.1 George Antonelli  of Novellus provided some insights into the ideal hard mask for copper interconnects at 20nm and below. Carbon films are deposited at 275°C with ion bombardment, yielding the same density as conventional films deposited at 500°C. Surface roughness was RMS 0.5-1.1nm, which impacts line edge roughness (LER). Line bending with this system was tested over the range AR 3.2 to 5.7 and was found to peak at AR 4.5 rather than increasing monotonically as AR increases. This was due to the interplay of mechanical stress with other process parameters and material properties. A doped SiC material was designed as an alternative to TiN hard mask to facilitate chemical removal or CMP after etch. More recently, work is underway on an undoped carbide variant that can be removed with wet etch and does not require CMP.

N7.1 Sang-Woo Kim from Sungkyunkwan U (Korea) described a high performance, transparent, flexible, stretchable, foldable (whew!!) nanogenerator based on multi-dimensional ZnO structures. Harvesting electrical energy from mechanical motion and vibration is the common objective, but the scope can range from replacing pacemaker batteries (not recommended for avowed couch potatoes) to embedding large area arrays in roadbeds to use traffic to generate power. PVDF is a material of choice for generating high output voltage, while ZnO is preferred for generating high output current. Graphene sheets were transfer printed onto a PEN polymer substrate, and ZnO vertical nanorods (1D) were grown on the graphene. The material functioned well, but the PEN distorted above 250°C. For such harsh conditions, a cellulose paper with Au seed layer was substituted for the PEN, and performed well even under harsh conditions. A 2D alternative was fabricated using ZnO nanosheets aligned vertically between electrodes. The work function of the top electrode limits the current output, with Au > graphene > ITO > Al.

C5.4 Ed Cooney of IBM talked about the stress effects in Cu inductors for RF technologies. While many of us are focused on 20nm and below, these devices still operate in the 0.18-0.35µm regime and require copper layers >3µm thick for proper inductor performance. At these feature sizes, reliability failure mechanisms are driven more by CTE mismatches.  Raising the post-plating anneal temperature from 100°C to 250°C reduced the room temperature tensile stress in the Cu which in turn reduces the driving force for delamination of the Cu from the SiN cap layer.

K4.5 Gregory Whiting of PARC showed a viable path toward high volume printing of flexible temperature sensors sensitive to 0.1°C up to 50°C. InSn/V2O5 was the eutectic mixture chosen for this work, with the ink scaled up to 1kg batches. Devices are printed on PET with screen printed Ag electrodes with gap widths varying from 250 to 500µm. The device shows a sensitivity of 1% change in resistance per degree between 20°C and 70°C, though a sensitivity to moisture dictates the needs for encapsulation for field use.

B2.1 Toshiki Hirano of Hitachi Global Storage (now Western Digital) gave an overview of MEMS and NEMS technology applications in the HDD world. HDD recording density has increased 3×108 times since the first IBM RAMAC in 1957. The track width on a 95mm disk today is 68nm (about the same as a human hair in a baseball field), with 3nm clearance between the R/W head and the disk surface. The next generation of actuator may be a moving magnetic element, now in R&D, in place of the moving slider. Another variation is a R/W head with heating elements on either side of the active area. Precise positioning is achieved by thermal expansion of the heater element on either side. Similarly, head height control can be positioned vertically with a resistance heating element, allowing a fly height of 1-3nm in combination with a contact sensor feedback loop. Bit patterned recording disk media are extendible to 10 Tbit/in2 using a self assembled polymer to guide the definition of individual domains. Thermal assisted recording can be facilitated with a near field transducer that has a spot size of 50nm.

N7.6 Rusen Yang of U Minnesota described energy harvesting with ZnO nanowires. ZnO nanostructures are unique in that they have been fabricated into nanobelts, nanosprings, nanorings, nanohelixes, and nanotubes, but nanowires are the focus here. These transducers are adequate to power pH and UV sensors, and the power can be stored to power LEDs. Power delivery is still in the µW to mW range. While the piezoelectric properties of ZnO are of primary interest here, it has other important and useful properties such as biocompatibility that add to its attractiveness for further research.

C6.3 John Zhang of ST Micro talked about the challenges in Cu CMP at 20nm and below. Center-to-edge uniformity is affected by the radial change in via sidewall angle, which gives a larger via top diameter at the edge and therefore a non-uniform tendency for dishing. In shrinking from 1µm L/S to 32nm L/S, Cu dendrites become increasingly problematic but can be controlled with PCMP chemistry. Validation must be established by looking for long term dendrite growth >100 hours after processing, and its effects can show up in TDDB data. The process window is shrinking as uniformity and defectivity often have competing optimization schemes. It was suggested that uniformity and defectivity parameters may have a minimum constant value, but no Heisenberg CMP uncertainty principle was actually articulated.

C6.4 Jae-Young Bae of Hanyang U (Korea) described the correlation of pad conditioning and pad surface roughness with CMP step height reduction, leading to a new slurry concept for initial step height reduction. Picolinic acid was added to ceria slurry; the maximum amount adsorbed on the pad surface for monolayer coverage was 0.36mg/m2. The acid increased the adhesion strength of the ceria particles to the pad surface by ~3x, leading to a 5x increase in removal rate, and 3x increase in planarization rate (60s vs. 180s).

C6.5 Bahar Basim of Ozyegin U (Turkey) talked about a wafer level CMP model to predict the impact of pad conditioning on process performance. Higher wafer scratch levels are correlated with points on the pad at which the conditioner sweep changes direction. Sweeping the conditioner over the edge of the pad surface also creates additional wear when the conditioner transits back onto the pad. The resulting pad profile model enables tailoring the wafer surface to best match the incoming wafer profile.

Also see Mike Fury’s other reports from MRS Spring 2012:

MRS Spring 2012: Day 1

MRS Spring 2012: Day 2

 

 

April 11, 2012 — Research and Markets released the "ST L3G3250A 3-axis MEMS Gyroscope Reverse Costing Analysis" report, providing a teardown of STMicroelectronics’ micro electro mechanical system (MEMS) gyroscope in a land-grid array (LGA) package.  

The package has a 3.5 x 3 x 1mm footprint, which is the smallest 3-axis gyroscope including VTI’s CMR3000, the report says. It is 27-40% smaller by volume (35% smaller by footprint) than the other main gyroscopes for consumer applications in production today, which typically have a 4mm2 footprint.

Also read STMicroelectronics’ article: Introduction to MEMS gyroscopes

The L3G3250A is suitable for various applications including gaming and virtual reality input devices, motion control with man-machine interface (MMI), GPS navigation systems, appliances, and robotics.

This report provides complete teardown of the MEMS gyroscope. For more information visit http://www.researchandmarkets.com/research/386cc1a5/st_l3g3250a_3axis

Visit the MEMS Channel of Solid State Technology, and subscribe to our MEMS Direct e-newsletter!

April 11, 2012 – BUSINESS WIRE — Tegal Corporation (TGAL) formed a partnership with HealthTech Capital (HTC), an investing group for emerging healthcare technology in Silicon Valley.

Micro electro mechanical systems (MEMS) power numerous new healthcare innovations. MEMS are "essential" to bringing the patient and healthcare closer together, said Philips Research Laboratories’ Hans Hofstraat at the inaugural MEMS Executive Congress Europe. MEMS can minimize the invasiveness of surgery, quickly screen for diseases (through microfluidics and lab-on-a-chip devices), and track motion.

HealthTech Capital invests in early-stage healthcare technology companies, with a focus on mobility and information technologies that improve healthcare delivery and decrease healthcare costs. Companies in its portfolio improve existing healthcare providers’ workflow or empower consumers to manage their chronic conditions or improve wellness.

Tegal has one portfolio company in healthcare technology, NanoVibronix Inc., a private company that develops medical devices and products that implement its proprietary therapeutic ultrasound technology. Tegal is intensifying its investment focus on healthcare technologies, said Thomas Mika, president and CEO, noting that government mandates and efficiency requirements can be served by semiconductor and MEMS technologies.

HealthTech Capital is a Silicon Valley-based angel investing group focused on emerging healthcare technology market where innovation improves healthcare delivery, empowers patients, and lowers costs. For more information, please visit www.HealthTechCapital.com.

Tegal Corporation develops and applies emerging technologies for microprocessors, magnetic memories, radio frequency ID chips, acoustic wave devices, sensors, LEDs, and an array of other semiconductor and MEMS devices. Internet: www.tegal.com.

Visit the MEMS Channel of Solid State Technology, and subscribe to our MEMS Direct e-newsletter!

April 10, 2012 — Vacuum and abatement equipment provider Edwards Limited uncrated the STP-iXR1606 series magnetically-levitated turbo-molecular pumps (TMP) with fully integrated onboard controllers. Its new rotary design improves throughput by about 40% at high gas flow rates; nearly 90% percent in maximum gas flow, compared to existing vacuum pump products, the company reports.

The pumps’ fully integrated controller eliminates the connection cable and rack conventionally required for vacuum pumps. This reduces the vacuum system footprint in the fab, and can cut installation time and costs. A small power supply for the on-board controller reduces energy consumption at high gas flows by about 32%.

The STP-iXR1606 matches the peak pumping speed of Edwards’ highest performing pump in the 8” TMP class, with higher throughput and maximum allowable gas flow. The STP-iXR1606 series delivers high reliability in dirty environments with equivalent IP54 protection against dust and humidity. It has I/O remote, RS232C, RS485 and STP-link standard communication ports, with Profibus and DeviceNet available as options. The magnetically-levitated TMPs require no maintenance.

Edwards creates vacuum products for electronics and other manufacturing environments. Learn more at http://www.edwardsvacuum.com/.

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April 10, 2012 — The 2012 Symposia on VLSI Technology and Circuits, June 12-14 (Technology) and 13-15 (Circuits), will take place in Honolulu, HI, with microelectronics manufacturing and circuit development research presentations. To foster joint interactions among device technologists and circuit/system designers, the technical programs of both symposia will overlap this year, and joint focus sessions on important topics will be held for the first time in the Symposia’s history.

More than 200 presentations will be given for approximately 1000 attendees. Short courses will occur prior to each symposium, with invited speakers addressing the industry’s most important issues. Evening rump sessions will spane a range of topics at the leading-edge of technology and circuit design. The VLSI Technology Symposium will be preceded by a satellite Silicon Nanoelectronics Workshop on June 10-11.

CMOS scaling and new 3D memory structures are highlights at this year’s Symposium on VLSI Technology, said Ming-Ren Lin, GLOBALFOUNDRIES, and General Chair.

The VLSI Circuits program will cover intelligent automotive vision systems, medical electronics, and diverse other applications, said Ajith Amerasekera, Texas Instruments, and General Chair, adding that more “universal topics” will also be covered, such as energy-efficient electronics and wireless communications interfaces.”

Short Courses

VLSI Technology Short Course (June 11), 14nm CMOS Technology & Design Co-Optimization and Memory.  This course will comprise 6 lectures given by distinguished speakers, covering state-of-the-art technology and circuit design for 14nm-generation CMOS.

VLSI Circuits Short Courses (June 12) — Two parallel full-day courses will be given by 12 distinguished international speakers from industry and academia.

– Designing in Advanced CMOS Technologies

– Ultra Low Power SoC Design for Future Mobile Systems

A single registration fee covers both, and participants can switch between the two. Afterward, a roundtable for both Circuits Courses will be held to foster interaction and discussion with all speakers.

New VLSI Symposia Technology/Circuits Joint Focus Sessions

The new Technology/Circuits Joint Focus Sessions are devoted to advanced device and circuit design co-optimization, a key ingredient for future progress.

– Memory (Wednesday morning, June 13)

– 3-D System Integration (Wednesday afternoon)

– Emerging Non-Volatile Memory (Wednesday afternoon)

– Advanced SRAM (Thursday morning, June 14)

– Design in Scaled Technologies (Thursday morning)

– Design Enablement in Scaled CMOS (Thursday afternoon)

– Embedded Memory (Thursday afternoon)

The Symposium on VLSI Technology will hold a special focus session Tuesday afternoon, June 12 on Low-Power and Steep Subthreshold Technology. The Symposium on VLSI Circuits will hold a special focus session Friday morning, June 15, Flash Memory.

Plenary Sessions

The Symposium on VLSI Technology will open with two invited plenary talks. First, Mike Mayberry of Intel will share his view through the “fog” of CMOS technology scaling, and identify directions for novel switching devices and new methods for computation.  Then, Prof. Ichiro Yamada of the University of Tokyo will describe how advances in information and communication technologies and micro-electro-mechanical devices (MEMS) can be leveraged to address the rapidly growing issues of the aging population and lifestyle-related diseases.

The Symposium on VLSI Circuits will open with two invited plenary talks by renowned experts. The Evolution of Next Generation Data Center Networks for High Capacity Computing will be given by Nicholas Ilyadis, Vice President & CTO of the Infrastructure and Networking Group at Broadcom. He will discuss the challenges of modern cloud computing and how they can be resolved by redefined network topologies and their underlying technologies and silicon solutions. The second plenary talk, Technology Innovations for Smart Cities, will be given by Akira Maeda, Chief Technology Officer, Infrastructure Systems Company, Hitachi, Ltd. He will discuss the technology innovations needed to realize “smart” cities, with emphasis on applications such as sensing, highly parallel processing, and mobile broadband communication for sophisticated social infrastructure systems. 

Evening Rump Sessions

The Symposium on VLSI Technology will hold two rump sessions in parallel on Tuesday evening, June 12 to foster open discussion of challenging R&D issues.

– Evolution of FinFET and Beyond? moderated by G. Yeap of Qualcomm and Y. Miyamoto of Tokyo Institute of Technology, will deal with the future of FinFET and other advanced transistor designs, such as ultra-thin body and ultra-thin BOX SOI, Ge and III-V transistors, tunnel FETs and other concepts.

– Patterning in Non-Planar World — EUV, DW or Tricky-193? moderated by G. Vandenberghe of IMEC and M. Tomoyasu of Tokyo Electron, will debate the future of patterning technologies.

The Symposium on VLSI Circuits also will hold two parallel rump sessions, on Thursday evening June 14.

– Is VLSI Innovation Dead? will feature seven experts (from IBM, Intel, AMD, NTT, and MIT, Shizuoka and Stanford Universities) discussing why companies in fields such as web software or server/OEMs are in the headlines, while semiconductor companies are noticeably absent. In short, the question for discussion is, is VLSI semiconductor innovation fine, dead, dying, or does it just need a kick-start?

– Will the Future Have More Analog or Digital Processing? Panelists from Analog Devices, Broadcom, Renesas Electronics, Xilinx, UC-Berkely and University of Tokyo will discuss whether the overall trend to digital circuit implementations is irreversible, or if the push toward digital circuits replacing analog counterparts is already finished. Digital circuits at new technology nodes don’t exhibit the same energy scaling as in the past, while analog-to-digital converter energy efficiency, for example, has improved more than 500-fold in the last decade.

A joint rump session will take place on Tuesday evening, Scaling Challenges Beyond 1xnm DRAM and NAND Flash Revolution?, moderated by R. Shrivastava of SanDisk and N. Lu of Etron. It will give the audience an opportunity to learn about future directions and issues for advanced memory technologies, including DRAM and NAND flash. The organizers of the VLSI Technology rump sessions (Thomas Skotnicki – STM and Katsura Miyashita – Toshiba) and of the VLSI Circuits rump sessions (Mark Bauer – Micron and Nicky Lu – Etron) invite all attendees of both VLSI Symposia to participate.

Luncheon

On Thursday, June 14, a luncheon sponsored by both Symposia will feature Nano-Satellites, CubeSats, and the Next Space Generation by Prof. James Cutler of the University of Michigan. He will discuss recent exciting trends in the space community, which are opening up access to space and sparking a wide variety of innovation globally. His talk will include stories of success and failure, and corresponding emerging challenges for the VLSI community will be highlighted.

Banquet

On Wednesday evening, June 13, a joint banquet will be held to provide an informal, relaxed atmosphere for information exchange between technologists and circuit designers.

The VLSI Technology Symposium began in 1981, while the VLSI Circuits Symposium was added in 1987. The two meetings have been held together ever since, rotating annually between Japan and Hawaii. The VLSI Technology Symposium is sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics, in cooperation with the IEEE Solid State Circuits Society. The VLSI Circuits Symposium is sponsored by the IEEE Solid-State Circuits Society and the Japan Society of Applied Physics, in cooperation with the Institute of Electronics, Information and Communication Engineers and the IEEE Electron Devices Society. Visit www.vlsisymposium.org

Visit the Semiconductors Channel of Solid State Technology!

April 9, 2012 – Marketwire — Coventor, Inc., micro electro mechanical system (MEMS) and semiconductor device fabrication software provider, launched the latest release of its SEMulator3D software, SEMulator3D 2012. It features improved predictive process modeling tools with increased capacity, speed, and automation for leading-edge process technology nodes.

The SEMulator3D 2012 release makes it possible to model devices in finer detail, down to the sub-nanometer level, and work with larger areas on the die. Assignment of boundary conditions for all process steps is now fully automated.

Unlike conventional TCAD simulation software, SEMulator3D models the complete front-end fabrication sequence at once. It can be used accurately on any device type — deployed now for 22nm logic devices, memory, etc — and can model all possible device variations. This allows users to predict process defect modes and reduce the number of scrap wafers.

SEMulator3D software is now being applied to accelerate development of the 14nm and 10nm nodes. SEMulator3D is also used by leading MEMS integrated device manufacturers (IDMs) and MEMS foundries for process development and design verification prior to tape out. Emerging applications for SEMulator3D include design rule development, failure analysis, and metrology.

Also read: Coventor updates CoventorWare 2012 MEMS design software

Coventor Inc. makes automated design tools for micro electro mechanical systems (MEMS) and virtual fabrication of MEMS and semiconductor devices. More information is available at http://www.coventor.com.

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