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by Debra Vogler, SEMI

In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers and industry experts to comment on the challenges they wanted to highlight. Many of the inputs focused on the need for precision in the processes used to form transistors, as well as how EDA can contribute to mitigating variability.

Likely enhancements on the logic roadmap below 20nm are a move to FinFET, improved FinFET implementation, high mobility channel, and gate all around (GAA) structures, noted Adam Brand, senior director, Transistor Technology Group at Applied Materials. He told SEMI that, “The increased complexity of the FinFET, high mobility channel, and GAA devices in combination with continued scaling requires more precision in structure formation and improved materials to address structure formation and parasitic effects.”

The key steps for maintaining the structural integrity of the fin are precision etch, void-free STI fill, recess, and precisely tailored corner rounding through dummy gate oxidation. Dummy gate oxidation addresses the challenge of ensuring that electric fields can be avoided in the corner explained Brand, who will present at SEMICON West 2013 (http://www.semiconwest.org). “The dummy gate serves two purposes,” said Brand. “It’s a structural element and it’s there when you do the transistor formation so it can serve roles such as being the etch stop for the gate etch. It’s also able to play a role in shaping the fin.” The fin can be shaped by changing the oxidation rate depending on the amount of oxidation needed for the side vs. for the corner.

Precision again comes into play when forming the gate — precision CMP is required to control the dummy gate and replacement metal gate height. The dummy gate material must also be easily removed. “Advanced CVD materials offer more choices in materials for differentiating selective removal,” said Brand. “Implant-based precision material modification (PMM) has been effective in changing selectivity to obtain better structure control.” He noted that in the past, CMP had not played a role in directly affecting the geometry of the transistor, but now, it is playing a much more direct role in determining the size of the transistor features. For example, in the replacement metal gate step, CMP is used to polish the metals used for the replacement gate structure and it’s also used for the self-aligned contact polish. “So now, you’re polishing the gate at least three times in order to form it, and you need very precise gate height control because it affects the overall stack height and contact height.”

Further complicating transistor scaling is that the 3-D structure adds complexity in strain-related mobility enhancement. “Source/drain stressor shaping is needed to optimize strain and control unwanted increase in the Miller capacitance,” said Brand.  “Lower k dielectrics are also needed to manage the Miller capacitance.” He further explained that when strain is implemented in a FinFET, each source/drain area is a separate fin — as opposed to when strain is being implemented on planar devices. “When you grow the source/drain [in a FinFET], it grows both horizontally and vertically, so when you scale the pitch of the fins, there’s the challenge that eventually those source/drain stressors come very close to each other and they might merge.” The solution, therefore, has to allow the stressors to grow without having them merge between the transistors and still obtain the amount of strain that is wanted. The solution must also address the Miller capacitance. 

The SOI value proposition changes below 20nm

Gary Patton, VP at IBM’s Semiconductor Research and Development Center, told SEMI that in order for the full benefit of the FinFET to be realized below 20nm, a dielectric isolation scheme is necessary to counter the uniformity and variability challenges. “The arrival of the FinFET era has brought about a fundamental paradigm shift in the SOI value proposition such that the advantages of SOI-based innovation now extend well beyond just device performance as in the planar case,” said Patton.  Indeed, Soitec, and others, such as STMicroelectronics, are betting that SOI-based technology will be used as a bridge enabling the industry to get the performance benefits of a fully-depleted transistor while staying with a planar transistor all the way from 28nm down to 14nm, or perhaps even sub-14nm.

To those who question the added cost of going with an SOI-based platform, Patton said that the cost of dealing with the isolation challenge offsets the cost of using SOI substrates. “Offset costs are due to both additional process steps required for bulk, and increases to die area,” said Patton. “An STI isolation module must be added for bulk FinFETs, as well as a series of masking steps and implants for isolation-leakage control and latch-up avoidance. Estimated additional processing costs of bulk isolation offsets the cost advantage of bulk substrates over SOI.” He also pointed out that die area increases are driven by the need for well contacts, and I/O guard-rings (latch-up avoidance). “We also anticipate the overall die yield to be challenging for the bulk FinFET process due to variability and the need for matching performance of critical circuit paths in a chip.”

Another consideration for proponents of SOI-based technology is the issue of process variability. “A buried oxide layer (BOX) in SOI fins is responsible for three areas of improvement in variability over bulk-isolated FinFETs,” Patton told SEMI. “First, the top silicon layer is terminated by the buried oxide, is proven to be extremely uniform in thickness, and defines the height of the fin both physically and electrically, since any fin over etch does not contribute to the fin height.” He further explained that the source and drain are completely separated by the gated channel, unlike in a bulk FinFET, where there is a continuous path for leakage, requiring a highly doped punch-through stop.

“The non-abrupt nature of doping introduces a non-uniform doping profile, and hence, turn-on current, between the top and bottom of the fin, further eroding the FinFET advantage.” Patton noted that a more practical consideration is the slope or taper of the fin itself. “From an electrical point of view, the ideal fin would be perfectly vertical and of uniform thickness from top to bottom. In a bulk fin process, a degree of taper must allow for the subsequent oxide fill and etch-back, and also to accommodate a reduced spacer over-etch budget (vs. an SOI fin). The fin taper introduces further non-uniformity to the FinFET, which reduces switching speed.”

EDA tackles variability

Reducing/mitigating process variability is ever more critical to yield as the industry scales transistors below 20nm, and much can be done in the design arena to help. For example, EDA considerations can mitigate “noise” in the optical system [lithography] that is a source of variability.

Mike Rieger, group director, R&D, Silicon Engineering Group at Synopsys, uses communication theory to analyze certain aspects of a lithographic system. He told SEMI that when there are optical systems [lithography] without tuning, i.e., a “plain vanilla” system — all the spatial frequencies in the visible limit are present. Conversely, when the design is friendly to specific spatial frequencies and you then try to print that design with an optical system that is friendly to all spatial frequencies, there are other frequencies that leak through. This “leakage” causes a lowering of the contrast in the optical image. “With the lower contrast, the image is more susceptible to other sources of variation like defocused variation, or dose variation, and that translates into your printed features having more variation in their dimensions,” said Rieger, another speaker at the upcoming SEMICON West (http://www.semiconwest.org).

Rieger added that, if you can prevent the unwanted frequencies from even being passed through the optical system, the net result is that the contrast is improved. Additionally, by tuning these frequencies, the diffraction orders in the stepper (the rays of light used to form the image) are manipulated. “You can eliminate the zero order ray. This zero order ray reduces contrast and it also limits the maximum frequency that you can image.” The tuning process – also known as source mask optimization (SMO) – really isn’t the end game, noted Rieger. “It’s source design optimization that is the end game. You tune the configuration of your design to be consistent with the optimization of the source.”

Regarding the parallel paths the industry is taking – extending optical lithography while developing EUVL — Rieger is realistic in his assessment of what EDA can bring to the table. “We’re going to be using 193i for the foreseeable future — it will be years before 193i is replaced,” said Rieger. But, “Optical lithography on a single exposure is maxed out in terms of the density it can print, so if you want to get more transistors per chip or more details per chip, you must do a couple of things.” Those are: tuning the optics, which comes at a cost, and using multiple exposures. “To get an effective result, the whole process of the tuned optics and the multiple exposures must be comprehended in the physical layout software, and some of the things that need to be done go beyond what you can accomplish with the traditional rule-based constraint that you put on the layout.”

For more information on SEMICON West 2013, visit http://www.semiconwest.org. To view all the TechXPOT info, visit http://www.semiconwest.org/SessionsEvents/TechXPOTs.

Register through June 7 at only $50 here: http://www.semiconwest.org/registration. Note that registration fees increase on June 8.

 

Critical trends and developments in the technologies, methodologies, and applications challenges in semiconductor test will be presented at the 6th annual IEEE Test Vision 2020 Workshop held in conjunction with SEMICON West 2013, on July 10-11 at the San Francisco Marriot Marquis Hotel. The one and one-half day workshop will feature speakers from Flextronics, Broadcom, Qualcomm, Texas Instruments, AMD, ON Semiconductor, Mentor Graphics, Micron, along with those from key semiconductor test industry suppliers. Organized by SEMI and sponsored by the IEEE Instrumentation and Measurement Society, Test Vision 2020 is a two-time winner of the ATE Test Technology Technical Council’s “Most Successful Event” Award.  Registration for Test Vision 2020 is now open at www.testvision2020.com, and includes free admission to SEMICON West.

Test Vision 2020’s purpose is to facilitate learning, forecasting and debate on the future of semiconductor test and serves as a valuable platform where leading foundries, IDMs and fabless companies discuss their critical test requirements with leading test equipment and solution providers.  This year’s program will feature panel discussions and leading industry experts that focus on the following key questions:

  • How can we achieve faster time to market with lower product costs?
  • What are the Test challenges in emerging technologies?
  • How much Test is enough?
  • What are the possible paths to economical high-speed test?
  • What are the next big innovations in Semiconductor Test?
  • What will be the new skills and competencies needed by future test engineers?

The keynote speaker for Test Vision 2020 will be Dr. Erik Volkerink, chief technology officer at leading end-to-end supply chain powerhouse, Flextronics.  He will present on the topic, “Product Foundry: Next Paradigm in Product Design and Engineering.” Featured speaker will be Sri Jandhyala, Strategic Marketing Director for ON Semiconductor, whose presentation will be, “LED Lighting — Opportunities, Challenges and the Future.”  Leading test equipment and solution providers will also highlight the latest test developments and trends, including speakers from Advantest, LTX-Credence, Roos Instruments, and Teradyne.

Starting at 3:00 p.m. on Wednesday, July 10 and concluding at 4:45pm on Thursday, July 11, Test Vision 2020 will also include a networking and casual social event on Wednesday evening.

GLOBALFOUNDRIES plans to unveil a comprehensive set of certified design flows to support 2.5D IC product development with its most advanced manufacturing processes at next week’s 50th Design Automation Conference (DAC) in Austin, Texas. The sign-off ready flows, jointly developed with the leading EDA providers, offer robust support for implementing designs using sophisticated multi-die packaging techniques, leveraging through-silicon vias (TSVs) in 2.5D silicon interposers and new bonding approaches.

Multi-vendor support is available, with full implementation flows from Synopsys and Cadence Design Systems. Physical verification with Mentor Graphics’ suite of tools is included in the flow.

The GLOBALFOUNDRIES 2.5D technology addresses the challenges of multi-die integration with solutions for front-end steps such as via-middle TSV creation, and flexibility for the backend steps, like bonding/debonding, grinding, assembly, and metrology.

“Our 2.5D technology provides designers with a path to enable heterogeneous logic and logic/memory integration, offering increased performance and reduced power consumption, without the need for additional packages,” said Andy Brotman, vice president of design infrastructure at GLOBALFOUNDRIES. “These benefits can now be realized very efficiently with certified design flows that provide support for the additional steps and design rules involved in the design process. By working closely with our EDA partners, we can greatly reduce the development time and time-to-production using the most advanced multi-die approaches.”

The flows allow designer to quickly and reliably address the additional requirements of 2.5D design, including top-level interposer design creation and floor planning, as well as the increased complexity of using TSVs, front-side and back-side bumps, and redistribution layer (RDL) routing. The flows support the need for additional verification steps brought on by 2.5D design rules.

The design flows work with GLOBALFOUNDRIES’ process design kits (PDKs) to provide real examples that demonstrate the entire flow. The user can download the design database, the PDK, detailed documentation and multi-vendor scripts to learn how to set up and use the GLOBALFOUNDRIES design flow. The flows use open source examples and provide the customer with working, executable and customizable flows.

The flows come with a CPU core and memory IP and all the scripts and settings to execute a Synopsys Galaxy Implementation Platform-based flow or Cadence Encounter-based implementation flows with the GLOBALFOUNDRIES PDK. Similarly, the Mentor Calibre 3DSTACK tool is exercised in the flow to verify DRC, LVS and extraction within and between the various die stacks leveraging the same golden design kits as used inside of GLOBALFOUNDRIES .

At next week’s 50th Design Automation Conference (DAC) in Austin, Texas, GLOBALFOUNDRIES will unveil a comprehensive set of certified design flows to support its most advanced manufacturing processes. The flows, jointly developed with the leading EDA providers, offer support for implementing designs in the company’s 20nm low power process and its 14nm-XM FinFET process. Working closely with Cadence Design Systems, Mentor Graphics and Synopsys, GLOBALFOUNDRIES has developed the flows to address the most pressing design challenges, including support for analog/mixed signal (AMS) design, and advanced digital designs, both with demonstration of the impact of double patterning on the flow.

The GLOBALFOUNDRIES design flows work with its process design kits (PDKs) to provide real examples that demonstrate the entire flow. The user can download the design database, the PDK, detailed documentation and multi-vendor scripts to learn how to set up and use the GLOBALFOUNDRIES design flow. The flows use open source examples and provide the customer with working, executable and customizable flows.

“As the developer of the industry’s first modular 14nm FinFET technology and one of the leaders at 20nm, we understand that enabling designs at these advanced process nodes requires innovative methodologies to address unprecedented challenges,” said Andy Brotman, vice president of design infrastructure at GLOBALFOUNDRIES. “By working with a new level of collaboration with EDA partners, we can provide enhanced insight into our manufacturing processes in order to fully leverage the capabilities of 20nm and 14nm manufacturing. This provides our mutual customers with the most efficient, productive and risk-reduced approach to achieving working silicon.”

Production ready AMS flow from specification to verification

To address the unique requirements of analog/mixed signal (AMS) design at advanced processes, GLOBALFOUNDRIES has enhanced its design flows to provide production quality scripts and packaged methodologies. The new reference flow establishes a working flow from specification to physical verification that has been taped out to be verified on working silicon.

The AMS reference flow provides comprehensive double pattern design guidelines. It gives overview of decomposition flow for both block level and chip level. The flow also addresses decomposition for different design styles. Recommendations for color balancing, hierarchical decomposition, ECO changes are discussed. The flows also present decomposition impact on DRC run time and resulted database size.

Notably, the reference flow includes support for efficiency and productivity improvements in the Cadence Virtuoso environment specifically for designing in a double patterned process. The flow includes support for Virtuoso Advanced Node 12.1 and provides efficient access to the tool’s productivity benefits for physical design with real-time, color-aware layout. Circuit designers can assign “same net” constraints in the schematic, and the layout designers can meet these requirements as they create the physical view. Additionally, layout designers can take advantage of Virtuoso tool support for local interconnect, and advanced layout dependent effect management.

The flow also features interoperability with Mentor’s Calibre nmDRC, nmLVS, and extraction products which address multipatterning requirements for both double and triple patterning. In addition special settings for analog design; auto-stitching and when to use it; and fill and color balancing are described in detail.

The AMS flow provides detailed information on parasitic extraction and layout dependent effects, both of which introduce new challenges at 20nm and 14nm. For parasitic extraction, the flows are described in detail and customizable scripts and examples demonstrate OA and DSPF back annotation. In addition the flows illustrate methodologies to predict layout-dependent effects during schematic design and methods to include full models in post layout extraction. PEX flows for Synopsys StarRC extraction, Cadence QRC and Mentor CalibrexRC are supported.

These flows serve as references to validate the correctness of the accompanying PDK as well as the vendor tools setup.

Sign-off ready RTL2GDSII flows that address double patterning

GLOBALFOUNDRIES is also making available new flows that support a complete RTL-to-GDSII design methodology for targeting its 20nm and 14nm manufacturing processes. The company worked with EDA vendors to certify the flows in their respective environments and provide a platform for optimized, technology-aware methodologies that take full advantage of the performance, power and area benefits of the processes.

The result is a set of fully executable flows containing all the scripts and template files required to develop an efficient methodology. The flows serve as a reference to validate the correctness of the accompanying PDK as well as the vendor tool setup. In addition the flows offer access to other critical and useful information, such as methodology tutorial papers; guidelines and methodologies for decomposition of double patterned layouts; PEX/STA methodology recommendations and scripts; and design guidelines and margin recommendations.

A critical aspect of manufacturing at this level is the use of double patterning, an increasingly necessary technique in the lithographic process at advanced nodes. Double patterning extends the ability to use current optical lithography systems and the GLOBALFOUNDRIES flows provide comprehensive double pattern design guidelines. They address design for double patterning and the added flow steps for different design styles and scenarios.

This includes support for odd cycle checking, a new type of DRC rule that must be met to allow for legal decomposition of the metals into two colors. This check is detailed in the flow and guidelines are provided to make sure it is met.

Synopsys and GLOBALFOUNDRIES worked together to minimize the impact of changes associated with the 3-D nature of FinFET devices as compared to planar transistors.  The two companies focused on making FinFET adoption transparent to the design team.  The collaboration on Synopsys’ RTL to GDSII flow includes 3-D parasitic extraction with the Synopsys StarRC tool, SPICE modeling with the Synopsys HSPICE product, routing rules development with the Synopsys IC Compiler tool and static timing analysis with the Synopsys PrimeTime tool.

Cadence contributed a complete RTL-GDSII flow, including physical synthesis, and planning and routing developed with the Encounter Digital Implementation (EDI) System foundation flow. The seamless implementation flow, using Cadence Encounter RTL Compiler and EDI System, supports double patterning and advanced 20- and 14-nm routing rules.

Mentor’s Olympus-SoC place and route system is supported in the flow, providing support for new DRC, double patterning, and DFM rules. The Olympus-SoC router has its own native coloring engine along with verification and conflict resolution engines that detect and automatically fix double patterning violations. Expanded features include DP-aware pattern matching, coloring aware pin access, pre-coloring of critical nets, and DP aware placement. The Calibre InRoute product allows Olympus-SoC customers to natively invoke Calibre signoff engines during design for efficient and faster manufacturing closure.

Double patterning also impacts LVS and other DRC issues, and the flows provide methodology details to address these areas, including hierarchical decomposition to reduce data base explosion. Parasitic extraction methodologies and scripts are provided as well, offering ways to address double patterning-induced variations via DPT corners or with maskshift PEX features.

Peregrine Semiconductor Corporation, a fabless provider of high-performance radio frequency integrated circuits (RFICs), today announced the signing of a collaborative agreement with Murata Manufacturing Company on a multi-sourcing arrangement for RF switches based on Peregrine’s proprietary UltraCMOS technology. Under the collaboration agreement, Murata agrees to source a majority of its RF switching requirements from Peregrine in exchange for being granted a license to purchase or manufacture RF CMOS switches utilizing Peregrine’s technology and intellectual property (IP). The parties expect this agreement to result in an expanded source of supply for these critical RF components and to assure global OEMs broad access to RF CMOS products.

Peregrine Semiconductor pioneered RF CMOS-based devices with its UltraCMOS technology, a form of silicon-on-insulator (SOI) process, and more than 20 years of research and development have resulted in 150 patents issued and pending. With this strong IP portfolio, Peregrine has established its position in the RF front-end section of mobile devices for RF switches and tunable RF components.

Murata is a supplier of RF front-end (RFFE) modules for the global mobile wireless marketplace. RF front-end modules are products that incorporate RF switches and tuning devices with SAW filters, passive components, and advanced packaging techniques.

“Global OEM customers of both Peregrine and Murata have for some time requested that the companies implement an independent source of supply for the critical switching elements that are widely utilized in today’s smart phones and other wireless-communications products,” said Jim Cable, Peregrine’s president and CEO. “This agreement marks the first license of Peregrine’s switch-based intellectual property to a third party; we look forward to working collaboratively with Murata to expand the deployment of UltraCMOS technology.”

Aptina’s board of directors yesterday announced that Phil Carmack has joined Aptina as chief executive officer and as a member of the board of directors. Aptina is a provider of CMOS image sensor solutions.

“We are extremely pleased that Phil is joining Aptina. Phil’s impressive industry experience and leadership skills will unleash Aptina’s potential and take the company to the next level,” said Nicholas Brathwaite, chairman of the board of Aptina.

Carmack most recently served as the senior vice president for NVIDIA’s Mobile Business Unit, which he established in 2003. Prior to his 13 years at NVIDIA, Carmack was the executive vice president of Research and Development at 3DFX Interactive, Inc. which was acquired by NVIDIA. His professional experience also includes leadership positions with innovative Silicon Valley companies including senior vice president and COO for Gigapixel and chief executive officer and founder of Raydiant, Inc. Carmack earned a Bachelor of Science degree in Electrical Engineering at Brigham Young University and a Master of Science degree in Electrical Engineering from Stanford University.

Carmack succeeds Nicholas Brathwaite who has been Aptina’s interim CEO since August 2012. Brathwaite will continue in his role as the chairman of the board of directors for Aptina, a position he has held since July 2009.

Aptina is a global provider of CMOS imaging solutions that enable Imaging Everywhere.

Association Connecting Electronics Industries announced today the April findings from its monthly North American Printed Circuit Board (PCB) Statistical Program. Notable among the month’s findings is the PCB book-to-bill ratio, which reached 1.10, its highest level since July 2010.

PCB bookings gain strength

Total North American PCB shipments were down 7.0 percent in April 2013 from April 2012, but bookings increased 7.2 percent year over year. Year to date, PCB industry shipments were down 5.1 percent and bookings were down 2.3 percent. Compared to the previous month, PCB shipments in April decreased 9.9 percent, and bookings declined 14.3 percent. Bookings have outpaced shipments for the past five months.

“North American PCB sales in April continued to lag behind 2012 levels, although sales in the flexible circuit segment are strengthening,” said Sharon Starr, IPC director of market research.  “Rigid PCB orders for the month exceeded last year’s orders and continued to push the book-to-bill ratio up to a strong 1.10. This is the fifth consecutive monthly increase in the ratio, which reinforces our hope that PCB sales will strengthen during the coming months.”

The book-to-bill ratios are calculated by dividing the value of orders booked over the past three months by the value of sales billed during the same period from companies in IPC’s survey sample. A ratio of more than 1.00 suggests that current demand is ahead of supply, which is a positive indicator for sales growth over the next three to six months.

Domestic production holds steady

IPC’s monthly survey of the North American PCB industry tracks bookings and shipments from U.S. and Canadian facilities, which provide indicators of regional demand. These numbers do not measure U.S. and Canadian PCB production. To track regional production trends, IPC asks survey participants for the percent of their reported shipments that were produced domestically (i.e., in the USA or Canada). In April 2013, 85 percent of total PCB shipments reported by survey participants were domestically produced. These numbers are significantly affected by the mix of companies in IPC’s survey sample, which change slightly in January, but are kept constant through the remainder of the year.

Interpreting the data

Year-on-year and year-to-date growth rates provide the most meaningful view of industry growth. Month-to-month comparisons should be made with caution as they may reflect cyclical effects and short-term volatility. Because bookings tend to be more volatile than shipments, changes in the book-to-bill ratios from month to month may not be significant unless a trend of more than three consecutive months is apparent. It is also important to consider changes in bookings and shipments to understand what is driving changes in the book-to-bill ratio.

Benefiting from its leadership position in AM/FM tuner and audio processing chips, NXP Semiconductors NV in 2012 retained its rank as the world’s top supplier of application-specific standard product (ASSP) semiconductors for the automotive infotainment market.

Netherlands-based NXP last year posted automotive infotainment ASSP revenue of $459 million, giving it a market share of 15 percent, according to insights from a forthcoming report from the IHS Automotive and Telematics Service from information and analytics provider IHS. The company’s market share remained unchanged compared to 2011.

top suppliers of ASSP semiconductors

“NXP is extremely well-positioned with its ASSP portfolio for the AM/FM tuner and audio processing segment, accounting nearly for half of all sales of these products in 2012,” said Luca DeAmbroggi, senior analyst for automotive infotainment at IHS. “While NXP’s market share held steady, the firm actually expanded is infotainment ASSP revenue by 2 percent, cementing its top-ranked status for the second year in a row. Like the other top infotainment ASSP suppliers, NXP achieved its leadership position by maintaining dominance in specific business lines.

French-Italian manufacturer STMicroelectronics was in second place with $389 million for a 13 percent share, separated by just $1 million from third-ranked Renesas Electronics of Japan with $388 million, also with a 13 percent portion of the market.

The rest of the Top 10 each had revenue ranging from $91 million to $280 million. Overall, the semiconductor market for automotive infotainment last year was worth $3.02 billion, up 2 percent from $2.96 billion in 2011.

STMicroelectronics dominated in the audio amplifier and digital/satellite radio tuner and decoder trades, with market share of 47 percent and 71 percent, respectively. However, STMicroelectronics suffered a 12 percent contraction in sales during the year, due to inventory reduction among its key customers as well as delays in the introduction of new devices and technologies.

With STM’s loss, Renesas has managed to narrow the gap between itself at No. 3 and the runner-up position after a 6 percent gain in revenue. Renesas is now a threat to STM after recovering from the 2011 Japan tsunami disaster.

Renesas is followed in fourth place by another Japanese supplier, Panasonic, with $280 million in revenue and a 9 percent share; and by British chipset maker CSR in fifth spot with $212 million or 7 percent share.

The rest of the Top 10 were, in descending order, Toshiba of Japan; Dallas-based Texas Instruments; Freescale Semiconductor, also from Texas; and Fujitsu Semiconductor and Rohm Semiconductor, both from Japan.

Other notable players in the space but outside of the Top 10 were Nvidia, Intel and Qualcomm, all from California; as well as Arizona-based Microchip Technology. In particular, Nvidia successfully imported its experience in multimedia and graphics processing from the consumer segment into automotive, mainly concentrating its initial efforts on infotainment premium brands. Less successful than Nvidia but likewise flexing its muscle was Intel, which is moving into the multimedia sector of car infotainment via the chipmaker’s Atom processor platform.

All the vendors reporting results for the year were tracked strictly by ASSP sales confined to the vehicle infotainment sector. Unlike general-purpose microcontrollers, memories or optical semiconductors, the ASSP silicon chips involved in this case are deployed to enable features such as AM/FM radio, digital terrestrial and satellite radio, audio amplifiers, GPS and navigation, multimedia logic and connectivity solutions like Bluetooth, Wi-Fi and vehicle networking, to name a few.

The semiconductor industry’s march toward broader 3D IC integration marked an important milestone this week at the 2013 Electronic Components & Technology Conference (ECTC), with the report of an advanced new temporary bonding solution for 3D Through-Silicone-Via (TSV) semiconductor packaging. The breakthrough was unveiled during ECTC’s 3D Materials and Processing session, when Ranjith John, materials development and integration engineer at Dow Corning, presented a paper co-authored by Dow Corning, a developer of silicones, silicon-based technology and innovation, and SÜSS MicroTec, a supplier of semiconductor processing equipment.

The paper, titled Low Cost, Room Temperature Debondable Spin on Temporary Bonding Solution:  A Key Enabler for 2.5D/3D IC Packaging, details the development of a bi-layer spin-on temporary bonding solution that eliminates the need for specialized equipment for wafer pretreatment to enable bonding or wafer post-treatment for debonding. Thus, it greatly increases the throughput of the temporary bonding/debonding process to help lower the total cost of ownership. 

“This advance underscores why Dow Corning values collaborative innovation. Combining our advanced silicone expertise with SÜSS MicroTec’s knowledgeable leadership in processing equipment, we were able to develop a temporary bonding solution that met all critical performance criteria for TSV fabrication processes. Importantly, the spin coat-bond-debond process we detailed in our co-authored paper takes less than 15 minutes, with room for further improvement,” said John. “Based on these results, we are confident that this technology contributes an important step toward high-volume manufacturing of 2.5D and 3D IC stacking.”

Both 2.5D and 3D IC integration offer significant potential for reducing the form factor of microelectronic devices targeting next-generation communication devices, while improving their electrical and thermal performance. Cost-effective temporary bonding solutions are a key enabler for this advanced technology by bonding today’s ultra-thin active device wafers to thicker carrier wafers for subsequent thinning and TSV formation. However, in order to be competitive, candidate temporary bonding solutions must deliver a uniformly thick adhesive coat, and be able to withstand the mechanical, thermal and chemical processes of TSV fabrication. In addition, they must subsequently debond the active and carrier wafers without damaging the high-value fabricated devices.

Through their collaboration, Dow Corning and SÜSS MicroTec were able to develop a temporary bonding solution that met all of these application requirements. Comprising an adhesive and release layer, Dow Corning’s silicon-based material is optimized for simple processing with a bi-layer spin coating and bonding process. Combined with SÜSS MicroTec equipment, the total solution offers the benefits of simple bonding using standard manufacturing methods. In their co-published paper, the collaborators report a solution exhibiting a total thickness variation of less than 2 µm for spin-coated films on either 200- or 300-mm wafers. The bonding material exhibited strong chemical stability when exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. In addition, the bonding solution and paired wafers showed good thermal stability when exposed to the 300°C temperatures common to the TSV process.

Dow Corning builds on a long history of silicon-based innovation and collaboration in semiconductor packaging. From die encapsulants for stress relief, to adhesives for sealing and bonding, to thermal interface materials for performance and reliability, Dow Corning’s well-established global infrastructure ensures reliable supply, quality and support, no matter where you are in the world.

Shipments in March of large-sized liquid crystal displays (LCD) exceeded total production when measured in terms of area, the result of a deliberate move by panel manufacturers to digest accumulated inventory, according to an LCD Fab and Inventory Management Tracker from information and analytics provider IHS.

Large-sized LCD displays in March reached a total shipment area of 11.3 million square meters, a metric showing the expanse of shipped panels during the period and distributed among the panels’ four major applications for TVs, notebooks, monitors and tablets. In comparison, production area measuring the spread and breadth of manufactured panels equated to 11.0 million square meters—approximately 340,000 square meters less than the total shipment area.

“March represented the first time in four months that shipments outpaced production for large-sized LCD panels,” said Ricky Park, senior manager for large-area displays at IHS. “The last time the same phenomenon took place—when shipment was higher than production—occurred in November 2012, an understandable occurrence as manufacturers raced to pump out more displays in time for the December holiday season and Lunar New Year holiday season in China. In March, panel suppliers applied the same tactic to chip away at creeping inventory, the upshot of shipments falling below production levels from December 2012 to February 2013.”

After March, however, the current dynamic took a different turn. Pending final figures, forecasts show that production would catch up to shipments starting in April as both indices reach 11.0 million square meters, with production then exceeding shipments beginning in May, as shown in the figure below. The new movement starts as the industry ramps up for the higher demand anticipated in the second half of this year.

shipments of large-sized LCD display panels

Calculated efforts pay off

For all the vicissitudes of the market, panel manufacturers need to continually negotiate a delicate balancing act—between making sure there is enough inventory, and preventing the inventory at hand from ballooning and crossing into dangerous oversupply. A potent weapon in their arsenal is to turn the screws on production, intentionally limiting manufacturing capacity in fabs, while continually shipping out panels taken from both current assembly and leftover inventory in their possession. Constant vigilance is required in an industry where oversupply is usually the norm, with panel manufacturers always striving to perfect their game.

Utilization rates are also adjusted to achieve targets. In March, utilization rose to 80 percent from 72 percent in February, but the pace of fabrication remained lower than was originally intended, estimated at 82 percent and consistent with the plan to keep production lower than shipments. Fab utilization rates were expected to remain unchanged in April and then jump to 83 percent in May—again in keeping with plans for production to start growing and overtake shipments.

Even so, panel manufacturers are not expected to exceed 85 percent utilization and risk producing more than the channel can swallow. Inventory has been particularly problematic because of slow demand, but manufacturers are also careful that pricing doesn’t drop further even with anemic demand plaguing the system.

Tablet panels continue to reign

Overall, shipments for large-area LCD displays during the first quarter this year compared to year-ago levels fell for monitors and notebooks, but rose for TVs and tablets. Monitor panel shipments were down 17 percent to 38.7 million units, while notebooks suffered an even larger 20 percent contraction to 43.2 million units. Shipments for TV panels, however, climbed 10 percent to 55.9 million units, while tablets posted an outsized 175 percent increase to 60.3 million units.

The reason for such disparate movements is not hard to guess. Monitors and notebooks have been under a cloud for some time, overshadowed among consumers by more appealing devices like smartphones and tablets. TVs, while a mature commodity in advanced markets like the United States, Europe and other highly industrialized countries, continue to enjoy increasing demand in the vast China market, compensating for any losses that may occur elsewhere.

Tablets are in even more fortunate circumstances. The devices continue to shine with blockbuster sales, their powerful status also demonstrated in unbeatable panel shipment numbers.