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Chip Memory Technology Inc. (CMT), a new embedded memory technology developer, has emerged from stealth mode to reveal company details and its latest product.

CMT’s LogicFlash boasts a unique solution for embedded NVM. Designed for implementation in industry standard CMOS logic processes, LogicFlash requires no extra foundry steps or extra mask layers. This radically reduces the expense and delay required to qualify and port chip designs that use LogicFlash to new foundries or new processes. CMT says Chrontel Inc., a provider of video ICs to the global computer and display markets, is currently incorporating LogicFlash into devices being produced in a 130nm standard logic process.

“Chrontel’s high-volume applications demand integrated NVM solutions that offer clear benefits in cost, yield and manufacturability,” explained Chrontel CEO and president Dr. David Soo. “LogicFlash offers us advantages that are not available with other embedded NVM technologies.”

Patented technology supports high densities

In development for several years, LogicFlash was designed to overcome the challenges facing embedded NVM production. Competing embedded NVM technologies require as many as 10 additional masks and 20 to 30 additional process steps when implemented on a standard logic process. By eliminating the requirement for extra masks and process steps, LogicFlash is highly portable and scalable, while supporting densities up to 4Mbit.

CMT holds four granted and two pending patents on its LogicFlash technology. Already qualified in five processes and three process nodes–at 180nm, 160nm and 130nm–multiple customers are currently in volume production with LogicFlash utilizing three different foundries.

“We are pleased to offer our latest technology to Chrontel, a company whose products are used in high-volume by computing and display manufacturers worldwide,” said CMT founder and CEO, Dr. Wingyu Leung. “By utilizing standard logic processes without modification, LogicFlash offers customers like Chrontel the ultimate in supply chain flexibility, scalability and low-cost.”

CMT was founded by several leading chip industry executives that collectively hold more than 150 patents. Dr. Leung, founder and CEO, has served as a senior technology executive, most recently as Executive Vice President, CTO and board member at MoSys.

CEA-Leti said today that Europe is strongly positioned to design and manufacture volume silicon photonics devices because of the success of the recently completed HELIOS program. The €8.5 million European Commission project developed a complete design and fabrication supply chain for integrating a photonic layer with a CMOS circuit, using microelectronics fabrication processes.

HELIOS, which was coordinated by Leti, also demonstrated a complete design flow, integrating both silicon photonics device design and electronic/photonic system design in an EDA-compatible framework.

“It is strategically important for Europe to maintain photonic chip-design and chip-integrating functions to compete with other countries and to encourage innovation by European microelectronics companies,” said Leti CEO Laurent Malier. “HELIOS’s success in creating the essential building blocks for integrating photonics with CMOS circuits and making the process available to a variety of users underscores the key role that broad European technological cooperation plays in a very competitive global business environment.”

Thomas Skordas, head of the EC’s photonics unit, said HELIOS has shown the large potential silicon photonics has in many different applications, such as data communications.

“The technology roadmap of silicon photonics becomes clearer now. Europe will have to move fast to become competitive in this new field,” Skordas said. “Strategies for the industrialisation of silicon photonics are currently being discussed in the context of Horizon 2020, the EU’s new framework program for research and innovation for 2014-2020."

Silicon photonics is seen as key to developing optical telecommunications or for optical interconnects in microelectronic circuits, because of the cost advantages of integrating photonic and electronic functions on the same chip. CMOS photonics may lead to low-cost solutions for a range of applications such as optical communications, optical interconnections between semiconductor chips and circuit boards, optical signal processing, optical sensing, and biological applications.

Launched by the European Commission in 2008, HELIOS focused on developing essential building blocks like efficient optical sources (silicon-based and heterogeneous integration of III-V on silicon), integrated lasers, high-speed modulators and photo-detectors. The project, which had 20 members, also combined and packaged these building blocks to demonstrate complex functions that address a variety of industrial needs.

These include a 10Gb/s modulator integrated with an electronic BiCMOS driver, a 16×10 Gb/s transceiver for WDM-PON applications, a photonic QAM-10Gb/s wireless transmission system and a mixed analog-and-digital transceiver module for multi-function antennas.

The building blocks also led to results exceeding the original specifications, positioning the partners at the leading edge in their fields:

  • High-performance passive devices were obtained and introduced in the demonstrators (rib/strip waveguides transitions with less than 0.2dB losses, grating couplers with 1.6dB losses, inverted taper couplers with 1dB losses, AWG and micro-ring based de-multiplexers).
  • The wafer-level integration of laser by III-V/Si bonding led to the demonstration of single-mode operation with 3dBm output power, 30dB SMSR, Ith < 35mA in CW.
  • 40G carrier depletion Si modulators were demonstrated in MZI, Ring, slow wave, interdigitated modulators configuration.
  • An integrated tunable laser–Mach-Zehnder modulator working at 10Gb/s.

The work of the HELIOS consortium led to more than 170 publications and communications in peer-review journals and international conferences.

 

David DiPaola is managing director for DiPaola Consulting, a company focused on engineering and management solutions for electromechanical systems, sensors and MEMS products.  A 17-year veteran of the field, he has brought many products from concept to production in high volume with outstanding quality.  His work in design and process development spans multiple industries including automotive, medical, industrial and consumer electronics.  He employs a problem solving-based approach working side-by-side with customers from startups to multi-billion dollar companies.  David also serves as senior technical staff to The Richard Desich SMART Commercialization Center for Microsystems, is an authorized external researcher at The Center for Nanoscale Science and Technology at NIST and is a senior member of IEEE. Previously,he has held engineering management and technical staff positions at Texas Instruments and Sensata Technologies, authored numerous technical papers, is a respected lecturer and holds five patents. Visit www.dceams.com.

After a functional A-sample prototype is built, it doesn’t take long for a project to gain traction that has market pull.  This is usually the point that a project becomes highly visible within a company and it enters the Technology Development Process (TDP). The TDP is made up of multiple phases including concept, prototype, pilot and production with gates at the end of each phase.  Design and process reviews are required at each gate but may also occur within a phase. These reviews are an open forum for communication of project progress and gaps towards technological, business and schedule milestones. Furthermore, the product is constantly evaluated against the market need and potential changes in market that may have occurred. The audience for the reviews at a gate include peers and management, who provide feedback on the project to date and collectively decide whether additional work is needed to complete the current phase or the completed work is sufficient to allow the project to proceed to the next phase with additional funding.  In certain instances, a project that has not met all of the deliverables may be allowed to proceed to the next phase, but under strict conditions, that must be fulfilled within a given timeline.  The goal of the TDP is to focus the team on high quality execution, effectively screen projects allowing only the best to proceed and hence accelerate successful innovation and profitability. 

The MEMS Industry Group (MIG) Technology Development Process Template is an excellent tool for companies to use to implement the TDP within their organization (Marty et al. 2013). The goal of the TDP was to create a simplified frame work that could be easily customized to fit a company’s needs. The TDP structure shown below is a slightly modified version of the TDP developed by MIG.  In this version there are four major phases including concept, prototype, pilot and production with three major gates. 

 

Figure 1

TDP Structure

MEMS new product development

 

 The concept phase is where ideas are generated and the initial A-samples are developed. It is also where the business case is first generated and the market need is defined.  It is highly desirable to have market pull at this point. The prototype phase is where the design is developed in detail and B-samples are fabricated to support various levels of validation. The outcome of the prototype phase is to have design that can be manufactured in volume production. Towards the end of the prototype phase, production tooling is often released. The pilot phase is where production tooling is built and qualified.  In addition, the product is made on production tooling (C-samples) and revalidated. It is important to note that there should be no change in the product design between the last revision in prototype and the first samples off the production tooling. The production phase is low to high volume production ramp. Often customers will require revalidation of products in production once a year for the life of the product.   

At each gate, there is a design and process review for the project. In order for the team to be focused and efficient, there needs to be a clear set of deliverables defined for completion of each phase.  These deliverables range from business and market definition to project technical details to production launch.  This checklist provides an in-depth set of deliverables for the design reviews at each gate that can be tailored to the specific needs of an organization. It is noted that a fourth gate is common 3-6 months after production launch to review project status but is not depicted in Figure 1.

This table can be downloaded from the following link in PDF format.  Many of the items listed above are self-explanatory.  Others are explained in more detail in previous blogs posts such as DFMEA and tolerance stacks.  

The Technology Development Process is an essential element of successful MEMS new product launches.  The Design Review Checklist can also provide a frame work for discussion between management and engineers on required deliverables to pass a particle gate.  With improved communication and efficient execution of technology development, the TDP is a great tool for accelerating innovation and profitable MEMS products.  In next month’s blog, the necessary attributes of a MEMS engineer for new product development will be discussed.  

Works Cited:

Marty, Valerie, Dirk Ortloff, and David DiPaola. "The MIG Technology Development Process       Template." MEMS Industry Group, Mar. 2013. Web. 28 Apr. 2013.

 

Studying 1/f noise


May 13, 2013

Welcome to the first of what I expect will be many blogs from ProPlus Design Solutions. While our name may be new to readers of Solid State Technology, we are known by the foundries as their supplier of device modeling software. We’re expanding our product portfolio and our industry presence, and a key reason why we jumped at the chance to blog for SST.

The topic of this blog is on-wafer measurement for flicker noise, a.k.a., 1/f noise, an engineering challenge I’ve been studying for more than 10 years, motivated by the needs of wafer fabs and circuit designs. 1/f noise is an important characteristic for various semiconductor devices, such as MOSFETs, BJTs, JFETs, Diode, and IC resistors. Not only does it directly impact the circuit performance of modern ICs, but it has been used also as an important technique to characterize the manufacturing process quality.

In recent years, on-wafer noise measurement has been done more often in massive volume by many of the foundries. SPICE models are built, often with statistical corners, to enable circuit designers to accurately analyze the impact of noise on circuit performance, especially for RF, low noise, and highly sensitive devices. However, accurately measuring flicker noise at the wafer level is challenging and time consuming, mostly due to the noisy probing environment, accurate DC bias requirement, and complicated cable connections. This creates a strong need to improve wafer-level noise measurement systems and methods to validate noise data.

Noise is a figure of merit for semiconductor process quality and characteristics impacting circuit performance today. Just like so many areas in our industry, process technologies at 28nm and beyond are calling for new tools and methodologies or significant improvement to existing tools. Noise data indicates how good the oxide and interface layers are. From it, fab process engineers can evaluate the related process quality and variations, and modeling engineers can build noise models. Then, circuit designers can simulate the impact of 1/f noise variation on analog or RF designs, or how the increasing RTS at advanced nodes reduces SRAM design margins.

Advanced wafer fabs use 7*24 1/f noise measurement data to assess process quality with the decades old 9812B wafer-level, 1/f noise measurement system. While it may be the industry’s de facto standard, it’s showing its age.

Circuit designers worry about variation effects at leading-edge process nodes, increasing the need for statistical noise models. Generating statistical noise models requires massive amounts of data collection at low frequencies. In some circumstances, when the 1/f noise corner frequency is high of greater than 1MHz, designers are expecting to see noise data at higher frequencies.

However, in a noise measurement system, there is a trade-off between system resolution and frequency bandwidth. In fact, in most commercial systems with only voltage LNAs, measuring MOSFET noise at frequencies higher than 1MHz on the wafer level, especially in the weak inversion region that is critical to analog designs, is practically impossible due to system gain roll-off.

Accuracy is a key requirement for on-wafer noise measurement. Noise is statistical in nature, and usually its magnitude is in the pA range. Measuring such a signal for devices on-wafer is challenging, especially when considering different device types at different bias conditions. The measurement accuracy relates to many factors, such as the system capability, measurement instruments, cables and environment. 

With all the new challenges and requirements discussed above, I’m advocating mothballing 9812B with a faster and more accurate system able to provide more accurate data collection in the range of 1Hz to 10MHz. This next-generation low-frequency 1/f noise measurement system is able to measure low-frequency noise characteristics of on-wafer or packaged semiconductor devices, including MOSFETs, SOI/FinFET, BJT/HBT, JFETs, TFT, diodes and diffusion resistors.

On-wafer noise is a fascinating subject and one I enjoy talking about. I also manage a talented R&D team at ProPlus that has built 9812D, the latest generation wafer-level, 1/f noise measurement system, a product we introduced earlier this year.

I’m hosting a 60-minute webinar May 14 titled, “Accurate and Efficient Wideband On-wafer Flicker (1/f) Noise Measurement.” Of course, I’ll talk about 9812D, but it will be a discussion on noise issues at 28nm and below nodes. The webinar is open to anyone interested in the topic, including academics, engineers and engineering managers who want to improve on-wafer noise measurement quality. For more information or to register, go to: http://tiny.cc/vcmdww.

Silex Microsystems, the world’s largest pure-play MEMS foundry, today announced that it has joined an international European Union-funded program aimed at developing a new MEMS manufacturing platform based on advanced inkjet-based printing technologies. The program, “Processes for MEMS by Inkjet Enhanced Technologies,” or PROMINENT, is leveraging the proven benefits of inkjet technologies to enable higher manufacturing efficiencies, increased product innovation, faster time-to-market, and lower costs throughout the entire MEMS manufacturing process. Silex’s contributions in this effort will include new low-cost technologies for through-wafer vias, hermetic high-vacuum seals for wafer-to-wafer bonding including advanced material deposition, advances in piezo-MEMS fabrication, and other functional materials processing.

As an innovation-driven industry, MEMS manufacturing depends on continuous innovation and exploitation of new technologies such as ink-jet processes. Ink-jet technology is one of the most mature MEMS technologies, having been in production since the late ‘70s and a mainstream of the digital printing industry since the early ‘80s. Similar to the impact that inkjet printing has had on the printing industry, the technology offers the promise of direct-to-wafer digitally-based patterning of wafer processing which can allow highly flexible prototyping and low-volume production for MEMS devices. In addition, advances in materials, electronics, and thin film compounds in recent years have opened up new avenues to apply ink-jet techniques to traditional manufacturing challenges such as metallization patterning using metallized inks. PROMINENT has been formed to exploit these new techniques and to advance the competitiveness of the European technology community.

“As a key partner in the PROMINENT project, Silex brings its extensive experience in metal TSVs and wafer bonding which will help end-users, partners in the consortium, and future customers advance the use of inkjet technologies for production purposes,” says Dr. Thorbjörn Ebefors, chief technologist at Silex Microsystems. “These new technologies have the potential to reduce costs and speed development time of new MEMS products, at no loss of performance for the customer.”

“Printed electronics have recently achieved considerable progress due to new printing technologies and the introduction of nanoparticle inks, paving the way towards integrating these capabilities within silicon-based nanoelectronics,” says Dr. Markku Tilli of Okmetic Oyj, PROMINENT project coordinator.  “The objective of the ENIAC JU project PROMINENT is to demonstrate significant cost reduction in MEMS manufacturing by using printing technologies to reduce materials, chemicals and energy consumption, waste water production, processing cycle time and capital investments.”

PROMINENT will develop novel low-cost, digitally controlled additive manufacturing methods that can radically change the manufacturing methods for MEMS and bring a substantial competitive edge to the European MEMS industry. The objective is not to replace the whole MEMS manufacturing process, but rather to introduce a new way of making its selected steps flow in a different, more flexible and cost-efficient way using methods developed in the printed electronics field.

By using maskless, digitally controlled, localized additive processes instead of the subtractive processes currently in use, selected steps in MEMS manufacturing can be done with a simplified process sequence. This will result in:

  • Lower initial investment costs for a MEMS line, making it easier for manufacturers to introduce new products.
  • New features in the MEMS devices, new application areas.
  • Greatly increased flexibility in production, allowing for smaller batches, mass customization and fast changes in the production process.
  • Increased flexibility, easier prototyping and shorter time-to-market for new MEMS devices.
  • Greatly reduced production costs and environmental impact.

Silex TSV and wafer-bonding

Combo MEMS sensors for automotive applications are off to another exhilarating ride this year as revenue continues to climb, spurred by rapidly accelerating use in car safety systems, according to an IHS iSuppli MEMS and Sensors Report from information and analytics provider IHS.

Global revenue in 2013 for combo inertial sensors used in motor vehicles will reach a projected $163 million, up a notable 77 percent from $92 million last year. The anticipated increase continues a hot streak for the market, which saw a phenomenal 338 percent surge last year from just $10 million in 2011, as shown below.

MEMS combo sensors

Combo inertial sensors are multiple-sensor devices integrating accelerometers, gyroscopes into a single package, providing inertial inputs to the electronic stability control (ESC) system in cars to prevent or minimize skidding.

“ESC systems are mandated in North America, Europe and in other areas where the edicts are maturing, such as Australia, Japan, Canada and South Korea,” said Richard Dixon, Ph.D., principal analyst for MEMS and Sensors at IHS. “But a huge growth opportunity exists in untapped territories like China, which would significantly impact the penetration of ESC worldwide given the vast size of the Chinese market. Such gains, in turn, would provide tremendous impetus and momentum for automotive combo sensors overall.”

Why combos?

Three architectures are currently possible for ESC systems in cars: on a printed circuit board as a separate ESC engine control unit (ECU); attached to the brake modulator to save cabling; or collocated in the airbag ECU. Of these three usable locations, the current trend favors placing ESC systems in the airbag ECU to achieve a smaller footprint and greater efficiency, given that there is a space constraint for the ECU in this position near the cup holder in a vehicle, which favors an architecture of reduction.

All told, as much as a fivefold reduction in space could be achieved for the sensors in a combo-sensor ESC system made by a manufacturer like Continental, compared to the same accomplished via separate sensors.

A non-combo solution also exists in the form of the sensors separately mounted on the printed circuit board. But deploying the sensors in a combo form factor saves not only on packaging cost but also on expensive real estate for the semiconductors being used, since the two sensors in the combo package share the same application-specific integrated circuit.

Cost is a factor

A paramount issue for ESC systems is cost. Cost is especially important because ESC formerly was considered an optional feature—but since being mandated by governments—it now has attained the same required status as the seat belt.

As a result, the entire supply chain and price structure for automotive combo sensors has been experiencing huge pressure, exerted from car makers down the chain. Tier 1 companies then pass on this pressure to their suppliers, accounting for the accelerated move to provide efficient combo sensor solutions for inertial sensors in the system.

Because of such pressure, some top-tier companies have indicated that only legacy businesses will use older arrangements featuring separate sensors—not a combo solution—on a printed circuit board in the future. All new car models will use combo sensors.

Top suppliers identified

The major suppliers of automotive combo inertial sensors are Bosch of Germany and Japan’s Murata (formerly VTI). Two other potential manufacturers, Panasonic of Japan and Massachusetts-based Analog Devices, will need to develop similar solutions to have a chance in the market.

For its part, Panasonic has indicated that a product will be available by 2014. Panasonic Industrial makes the gyroscope part of the solution, while Panasonic Electric Works makes the accelerometer component.

However, the two entities do not have a good track record of working together, so it remains to be seen how soon a unified combo sensor solution from Panasonic will come to market.

Meanwhile, Analog Devices is divulging little information, but it will almost certainly develop a combo sensor solution, IHS iSuppli believes, based on an analysis of developments surrounding the competition.

Teledyne Technologies Incorporated announced today that its subsidiary, Teledyne DALSA B.V., has acquired Axiom IC B.V., a fabless semiconductor company that develops high-performance CMOS mixed-signal integrated circuits. Terms of the transaction were not disclosed.

Located in Enschede, the Netherlands, Axiom IC was founded in 2007 and is a spin-off from the University of Twente. Axiom IC’s customers include global companies in a number of industries, including space systems, wireless communications, automotive and medical technologies. Axiom has delivered design breakthroughs including high speed, high resolution analog to digital converters and advanced audio signal processing chips.

“The acquisition of Axiom adds an innovative team of skilled engineers to Teledyne,” said Robert Mehrabian, chairman, president and chief executive officer of Teledyne. “While continuing to serve external customers, Axiom will provide additional resources to benefit both our digital imaging and electronic test & measurement instrumentation businesses.”

“The Axiom team will further enhance our ability to bring to our customers innovative and highly differentiated CMOS-based image sensor and camera products,” said Brian Doody, chief executive officer of Teledyne DALSA, Inc. “Axiom’s unique mixed-signal design expertise and experience represent a valuable strengthening of our design capabilities across the company, complementing our existing expertise in CMOS image sensor design, high voltage driver chips for MEMS, and embedded software development.”

Teledyne Technologies is a provider of sophisticated instrumentation, digital imaging products and software, aerospace and defense electronics, and engineered systems. Teledyne Technologies’ operations are primarily located in the United States, Canada, the United Kingdom and Mexico.

TowerJazz, the global specialty foundry leader, today announced collaboration with TLi (Technology Leaders and Innovators), a fabless company that designs non-memory integrated circuits (ICs) focused on timing controllers and driver ICs on TFT-LCD panel modules. TLI says they have developed an acceleration sensor control IC and proximity illumination sensor IC based on TowerJazz’s 0.18um CMOS technology, which enables TLi to provide local offerings to mobile phone suppliers in Korea where the market leaders are located.

As of 2012, the worldwide mobile phone market was 1.7 billion dollar and 43 percent of this was attributed to smartphones with acceleration sensor control ICs and proximity and illumination sensor ICs. The portion of smartphones with these ICs is expected to grow steadily, and TLi is targeting this fast growing market with two of its products utilizing TowerJazz’s process. A mass production is expected to start in Q3, 2013.

The acceleration sensor market is mostly dominated by a few major foreign companies, however in January of this year, TLi succeeded in developing an acceleration sensor control IC and a proximity illumination sensor IC in Korea. These products are the first released from the very close collaboration between TowerJazz and TLi. By utilizing the advanced features of TowerJazz’s 0.18um CMOS process, TLi realized accurate modeling as well as flash memory without mask adder for its acceleration sensor control IC and succeeded in realizing the sensing block without expensive color filtering for its proximity illumination sensor IC.

"We have been very pleased with our collaboration on these exciting products which has enabled us to provide local offerings to Korean mobile phone suppliers that are expected to be the most cost effective solutions in this market. This is the result of our close discussions with TowerJazz to utilize the advanced features of their 0.18 CMOS process. Also, these products showed full functionality from first silicon," said Soonwon Hong, vice president of TLi.

"Korea is an important region for technical and manufacturing innovation and we are very excited to work with a leading-edge partner such as TLi to enable localization of their specialized sensor ICs," said Michael Song, VP of Sales and president of TowerJazz Korea. "TLi has trusted us to co-develop and bring to market their latest products and we are pleased with the progress we have made in this region which is home to many leading semiconductor companies."

IQE plc announces the launch of gallium nitride-based, high electron mobility transistor (GaN HEMT) epitaxial wafers on 150mm diameter semi-insulating silicon carbide (SiC) substrates, supplied by the WBG Materials subsidiary of II‐VI Inc. a global provider of engineering materials and optoelectronic components.

GaN power amplifiers offer superior power capability, efficiency, bandwidth and linearity compared with silicon (Si) or gallium arsenide (GaAs)-based technologies commonly used, providing significant benefits in terms of both higher performance and lower overall system costs.

GaN-based low-noise amplifiers exhibit improved robustness, noise figure and dynamic range when compared to incumbent solutions. In addition, GaN-based transistors can operate at high temperatures, thus reducing system cost, size and weight. As a result, GaN transistors are now established as a leading new technology for a wide range of defense applications.

Introduction of 150mm GaN HEMT epi wafer products also enables cost reduction, production capacity and yield improvement, as well as potential for insertion into a wider range of chip fabrication facilities. To date, commercial market penetration of GaN HEMTs has been limited by the higher cost of epitaxial material grown on 100mm SiC substrates.

IQE said it’s customers have demonstrated GaN HEMT fabrication using LDMOS (laterally diffused metal oxide semiconductor) process lines, so the Group’s 150mm products are compatible with existing LDMOS processing lines that have been made available as a result of the silicon industry’s transition to 200mm technology.

 “Scaling up to 150mm wafer diameter is a critical milestone on the path to technological maturity and wide market acceptance of GaN HEMTs on SiC,” Russ Wagner, VP of IQE Wireless Business Unit said. “IQE has established an industry-leading position by offering a full range of GaN-based high-power RF transistor wafers in formats that enable the most cost-effective processing and system designs.”

 “The WBG Materials subsidiary of II-VI Inc. has developed high quality 4H – 150mm SiC substrates, for both the RF and power markets,” said Dr. Tom Anderson, General Manager of II-VI Inc. subsidiary WBG Materials. “These 150mm SiC substrates will greatly reduce device costs by increasing the number of devices produced per wafer, enabling 150mm wafers to be processed using modern, high volume semiconductor tools designed for large wafers and by providing competitive sourcing and leveraging of high volumes into commercial markets.”

Researchers from IMDEA-Nanociencia Institute and from Autonoma and Complutense Universities of Madrid (Spain) have managed to give graphene magnetic properties. The breakthrough, published in the journal ‘Nature Physics’, opens the door to the development of graphene-based spintronic devices, that is, devices based on the spin or rotation of the electron, and could transform the electronics industry.

Scientists were already aware that graphene, an incredible material formed of a mesh of hexagonal carbon atoms, has extraordinary conductivity, mechanical and optical properties. Now it is possible to give it yet one more property: magnetism, implying a breakthrough in electronics.

magnetizing graphene
This is a computerised simulation of TCNQ molecules on graphene layer, where they acquire a magnetic order.

This is revealed in the study that the Madrid Institute for Advanced Studies in Nanoscience (IMDEA-Nanociencia) and Autonoma Autonomous (UAM) and Complutense (UCM) universities of Madrid have just published in the ‘Nature Physics’ journal. Researchers have managed to create a hybrid surface from this material that behaves as a magnet.      

"In spite of the huge efforts to date of scientists all over the world, it has not been possible to add the magnetic properties required to develop graphene-based spintronics. However these results pave the way to this possibility," said Prof. Rodolfo Miranda, director of IMDEA-Nanociencia.

Spintronics is based on the charge of the electron, as in traditional electronics, but also on its spin, which determines its magnetic moment. A material is magnetic when most of its electrons have the same spin.

As the spin can have two values, its use adds two more states to traditional electronics. Thus, both data processing speed and quantity of data to be stored on electronic devices can be increased, with applications in fields such as telecommunications, computing, energy and biomedicine.

In order to develop a graphene-based spintronic device, the challenge was to ‘magnetize’ the material, and researchers from Madrid have found the way through the quantum and nanoscience world.

The technique involves growing an ultra-perfect graphene film over a ruthenium single crystal inside an ultra high vacuum chamber whereorganic molecules of tetracyano-p-quinodimethane (TCNQ) are evaporated on the grapheme surface. TCNQ is a molecule that acts as a semiconductor at very low temperatures in certain compounds.

On observing results through a scanning tunneling microscope (STM), scientists were surprised: organic molecules had organised themselves and were regularly distributed all over the surface, interacting electronically with the graphene-ruthenium substrate.                                                    

"We have proved in experiments how the structure of the TCNQ molecules over graphene acquires long-range magnetic order with electrons positioned in different bands according to their spin," clarifies Prof. Amadeo L. Vázquez de Parga.

Meanwhile, his colleague Prof. Fernando Martin has conducted modelling studies that have shown that, although graphene does not interact directly with the TCNQ, it does permit a highly efficient charge transfer between the substrate and the TCNQ molecules and allows the molecules to develop long range magnetic order.

The result is a new graphene-based magnetized layer, which paves the way towards the creation of devices based on what was already considered as the material of the future, but which now may also have magnetic properties.