Category Archives: Online Magazines

Newport Corporation introduced long-lived deep ultraviolet (UV) excimer laser mirrors with projected lifetimes greater than 30 billion pulses when used in the proper photocontamination controlled environment.  The advanced new mirrors feature all dielectric high reflector coatings to minimize absorption and maximize reflected energy at 193nm.

The high energy laser mirrors are designed with excimer-grade UV-fused silica substrates which are polished to better than λ/10 flatness to preserve wavefront quality and maintain excellent stability.  All coating and testing are done in a special photocontamination controlled deep UV cleanroom that has been qualified to 193nm standards.

According to Optics product manager at Newport, Anna Sansan Wang,“Extensive analysis, research and testing have been done to better understand the conditions at these short wavelengths. Our coating scientists have investigated various conditions including thermal issues, densification of materials, and wavelength shift in order to properly optimize the performance of the mirrors at 193 nm under long term use.”

Newport’s new laser mirrors offer exceptionally high laser damage resistance.  Special Pet-G and metal foil packaging ensure that parts are delivered clean and protected from any environmental photocontamination.  The long-lived deep UV Excimer laser mirrors will be featured at SPIE Photonics West in Newport’s booth #1301 at Moscone Center, San Francisco, CA, February 5 – 7, 2013. 

 

China’s rapid transition from a low-cost manufacturing hub to an innovation hotspot with growing foreign ambitions represents both a threat and an opportunity for companies and investors around the globe, according to Lux Research.

Chinese firms in such sectors as energy storage, advanced lighting, emerging electronics and red-biotechnology industries are more likely to pursue both overseas growth and introduction of foreign capabilities into China.

During 2009-2011, Chinese companies’ foreign merger and acquisition (M&A) deals grew 75% to $28.1 billion. Simultaneously, M&A deals by foreign companies in China increased 16 times – from $400 million to $6.9 billion, suggesting new momentum in opportunities inside the world’s fastest growing country. All indications are that this is only the beginning.

“From Chinese companies’ perspectives, acquiring advanced technologies globally and entering foreign markets are major goals as they seek to shed the tag of a low-cost manufacturing hub,” said Zhuo Zhang, Lux Research Associate and the lead author of the report titled, “From the Horse’s Mouth: How Chinese Companies Value Foreign Partners and Opportunities.”

“Entities around the globe need to navigate the new reality of an increasingly crowded market in China where global leaders must learn to operate while developing strategies to face the imminent threat in their own backyard,” he added.

Lux Research analysts studied China’s complex emerging technology ecosystem, surveying and analyzing 380 entities. Among their findings:

  •  Sectors to watch. Energy storage, advanced lighting, emerging electronics and red-biotechnology all sat in the upper-right quadrant of the grid on Lux’s China Innovation Partnership Grid. This indicates that companies in these sectors have both strong foreign growth inclination and strong willingness to introduce appropriate foreign partners into China. In comparison, water treatment and construction material industries are closed to foreign growth and introduction.
  • IP drives openness. Chinese companies with a strong IP portfolio are more open to foreign partnerships. Contrary to conventional wisdom regarding China, it is the companies that value IP, rather than just those looking to infringe upon the IP of others, who are most open. Specifically, 51% of companies with strong IP are open to partnering with foreign entities in China, compared to only 31% of those with weak IP.
  • Government relationships enable growth introverts. Companies with poor government relationships are driven to look overseas, with 54% of these companies having meaningful foreign growth activities compared with only 44% percent of the companies with good government relationships. In many of China’s emerging technology industries, government relationships represent domestic sales channels, reducing the urgency for foreign growth.

The report, titled “From the Horse’s Mouth: How Chinese Companies Value Foreign Partners and Opportunities,” is part of the Lux Research China Innovation Intelligence service.

Cadence Design Systems, Inc. (NASDAQ: CDNS) announced the availability of Virtuoso® Advanced Node, a new set of custom/analog capabilities designed for the advanced technology nodes of 20nm and below.Built on the industry-leading Cadence® Virtuoso custom/analog technology, Virtuoso Advanced Node features capabilities that prevent errors before they are created rather than detect them late in the design process. Working in concert with Cadence Encounter® RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node enables the development of mixed-signal chips that power today’s consumer electronics devices.

The new and advanced Virtuoso technologies address layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers. They integrate with the Cadence Integrated Physical Verification System (IPVS) to conduct on-the-fly checks that reduce layout iterations.

LDE analysis using incremental layout — Virtuoso Advanced Node enables engineers to build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end.  It delivers novel technology that helps decrease costly design iterations by allowing designers the ability to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle.  LDEs — such as stress effects, poly and diffusion spacing/length, well proximity effects, and parasitics — are handled with detailed test benches that analyze multiple corners to ensure that the circuit will function as specified.

When this technique is combined with Cadence MODGENs and constraints, IPVS and final hotspot detection and correction with Virtuoso DFM, users can expect up to a 30 percent improvement in their overall verification time.  By methodically building and checking the design, the designer should eliminate massive “rip ups” and “reroutes” that can be found at the end if the circuit wasn’t checked along the way.

Double patterning and color-aware layout—Double patterning, a manufacturing requirement at 20 nanometers, splits the design layers into two masks, separating structures that are too close together. But double patterning brings “coloring” challenges to designers. Virtuoso Advanced Node delivers real-time automated color-aware, design-rule-driven layout to enable the creation of area-optimized layout. It provides engineers the ability to match, lock and store colors on critical nets and geometries (through schematic constraints or directly on the layout), and to identify, debug and fix errors as they go, rather than later in the design process, when they are more difficult to fix.

New routing layers—Foundries require the utilization of new local interconnect (LI) layers, or middle-of-line (MOL) layers, that are used to create densely packed routes inside complex devices. These layers have restricted design rules governing local interconnect and the vias that are used with them, presenting the challenge of maintaining signal integrity from pin to pin of the transistors. Virtuoso Advanced Node technology provides a local interconnect-aware wire editor and router that address the issue of complex LI rules.

Developed specifically for the most cutting-edge designs, the Virtuoso Advanced Node options do not replace the industry-leading 6.x version of the Virtuoso technology, which targets mature and mainstream geometries, and which will continue to be enhanced by Cadence.

“Moving to smaller geometries always creates new obstacles, but the move to 20 nanometers has been especially challenging for our customers, many of whom are reporting that layout is taking two to five times as long as for 28nm on the same circuit,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “Virtuoso Advanced Node enables design teams to optimize their designs for performance, power and area while reducing or even eliminating tasks that would make 20nm design much more time consuming and labor intensive.”

ProPlus Design Solutions, Inc., announced it is shipping a new wafer-level, 1/f noise measurement system. Increasingly, circuit designers are interested in 1/f noise data at higher frequencies. They are concerned also about variation effects at leading-edge process nodes, increasing the need for statistical noise models. Generating statistical noise models requires massive amounts of data collection that is particularly challenging at low frequencies.

The 9812D low-frequency 1/f noise measurement system is designed to measure low-frequency noise characteristics of on-wafer or packaged semiconductor devices, including MOSFETs, bipolar junction transistors (BJTs), junction field effect transistors (JFETs), diodes and diffusion resistors. In addition to frequency domain measurement, 9812D can measure device noise in the time domain and can be used to perform on-wafer auto measurement for flicker (1/f) noise and Radom Telegraph Signal (RTS) analyses.

9812D improves upon 9812B, the company’s 1/f measurement system used for more than a decade by foundries, integrated device manufacturers (IDMs) and research organizations. The system, which has a frequency range that exceeds 10 Megahertz (MHz), has a built-in dynamic signal analyzer (DSA) with multi-threaded processing for improved performance and reduced cost.

“Noise is a key figure of merit for semiconductor process quality and also an intrinsic characteristic impacting circuit performance,” said Dr. Zhihong Liu, executive chairman of ProPlus Design Solutions. “To meet the new challenges at 28 nanometer and beyond, we worked with leading foundries on significant improvements of the 1/f system.”

Wafer fabrication facilities use 7*24 1/f noise measurement data to assess process quality. A three-to-10X throughput improvement of the 9812D system means faster data collection and early detection of process issues.

Thomas Edison invented the first incandescent light bulb 130 years ago, which greatly contributed to the advancement of civilization. However, that technology is antiquated, economically inefficient to operate, and fragile.

Fluorescent lights are energy efficient but they are bulky and have to ‘warm-up’ when turned on. Their bulbs contain phosphorus and mercury, which are toxic to the environment. Today’s LED lights are also energy friendly but are expensive and difficult to manufacture. The process to make conventional LEDs is very complicated, as it involves the growth of single crystal layers on the single crystal substrate. Each layer has to contain low defects for it to work. The cost of LED lights is usually ten times the cost of the incandescent bulb, because the equipment to produce them is expensive, the raw materials are expensive, and the environmental and safety issues are critical. Another disadvantage of the current LEDs is they do not produce white light from a single chip. This requires extra manipulation, such as using a set of 3 chips emitting different lights or adding a phosphors material to the blue or UV chip to produce the white light. 

Professor Yue Kuo of the Artie McFerrin Department of Chemical Engineering at Texas A&M University has fabricated a new type of LED, capable of producing a wide spectrum light while operating for long periods of time at atmospheric conditions. This device is based on a new concept of light emission from an ultra-thin amorphous dielectric layer.     

Figure (left) Low- and (right) high-magnification photos of light emission from the new LED.

An article published in Applied Physics Letters, describes the light emission mechanism, characteristics of the emission spectrum, fabrication method, and the operation parameter effects on this type of LED. The device was fabricated with the room-temperature sputter deposition method on a silicon wafer. The light emission intensity could be enhanced with a nanocrystal layer embedded in the dielectric film. Most importantly, the complete process and materials are compatible with the existing IC fabrication facility.

“There is a need for a new type of LED that is: low cost, long operation life, small in size, emits white light, and easy to fabricate with environmentally friendly materials and process.” Dr. Kuo says. “ What makes this new LED unique is it meets all of these requirements plus it is extremely easy to fabricate with the existing equipment in all semiconductor fabs.” 

The light emitted is composed of small bright dots evenly distributed across the electrode surface.  The input voltage controls the intensity or brightness of the LED.  Dr. Kuo is very optimistic with the results of his findings. “We have discovered this phenomenon and studied this kind of LED for more than a year. It can be operated continuously for more than ten hours. A longer operation time is expected.”

Kuo‘s discovery has larger implications than just lighting. These LEDs could potentially be integrated into a computer processor; dramatically increasing the speed by transporting signals optically rather than by electrons through copper lines.  They could have use in various industries, entertainment, medical, commercial, and military areas due to the compact size and low cost. 

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc., San Jose, CA, blogs about the evolution of 3D technology seen at the International Electron Devices Meeting. 

From our biased point of view we see the recent IEDM12 as a pivotal point for monolithic 3D. Here’s why:

We start with the EE Times article IEDM goes deep on 3-D circuits, starting with "Continuing on the theme of 3-D circuit technology addressed in an earlier post about this year’s International Electron Device Meeting, Rambus, Stanford University and an interesting company called Monolithic 3D will address issues related to cooling 3-D circuits. .." and follow with a quote from the abstract to IEDMs short course "Emerging Technologies for post 14nm CMOS" organized by Wilfried Haensch, of IBM’s Watson Research Center: "Scaling the dimension was the key for the unprecedented success of the development of IC circuits for the last several decades. It now becomes apparent that scaling will become increasingly difficult due to fundamental physical limits that we are approaching with respect to power and performance trade-offs. This short course will give an overview of several aspects in this “end-of-scaling” scenario. …"

We then continue with statements made by Dr. Howard Ko, a Senior Vice President and General Manager of the Silicon Engineering Group of Synopsys in his 2013: Next-generation 3-D NAND flash technology article: "Yet there are a variety of developments in another type of 3-D scaling that are likely to have a similarly large impact on semiconductors in the near future – 3-D devices for NAND flash…. And as in planar CMOS logic, NAND flash technology has been progressively scaled to smaller feature sizes, becoming the process leader in driving the smallest line-widths in manufacturing as evidenced by the current 1x-nm (~19-nm) process node. Yet, despite plans to scale down to the 1y-nm (~15-nm) and possibly 1z-nm (~13-nm) nodes, the traditional planar floating gate NAND flash architecture is approaching the scaling limit, prompting the search for new device architectures.  Not to be upstaged by the planar to 3-D (FinFET) transition in logic devices, NAND flash has embarked on its own 3-D scaling program, whereby the stacking of bit cells allows continuous cost-per-bit scaling while relaxing the lateral feature size scaling."

In our recent blog 3D NAND Opens the Door for Monolithic 3D we discussed in detail the adoption of monolithic 3D for the next generations of NAND Flash. The trend was very popular subject of this year’s IEDM and is nicely illustrated by this older chart:

And accordingly the updated ITRS 2012 present the change from dimension scaling to monolithic 3D scaling as presented in the following slide.

This year’s IEDM brought up two of the driving forces behind the shift from dimensional scaling to monolithic 3D IC scaling, that we will detail below as #1 and #2.

The current 2D-IC is facing escalating challenges:

On-chip interconnect (#1): Dominates device power consumption, Dominates device performance, Penalizes device size and cost

Lithography (#2): Dominates Fab cost, Dominates device cost and diminishes scaling benefits, Dominates device yield, and Dominates IC development costs.

The problem with on-chip interconnect didn’t start today. This vintage Synopsys slide below clearly indicates that on-chip interconnect started to dominate overall device performance a decade ago:

In response, the industry has spent an enormous amount of money to convert from aluminum to copper and to low-K inter-metal dielectrics. But now, we have very few additional options left (perhaps air-bridge?) as illustrated by the following chart:

It shows that neither Carbon Nano Tube (CNT) nor Optical interconnect are better than copper, and that monolithic 3D still is the best path.

The practiced ‘band-aid’ fix so far has been throwing more transistors (they are getting cheaper, right? No longer. See father below) at the problem in the form of buffer and repeaters. But as we scale down we need exponentially more of these ban-aids as illustrated by the following:

Copper, however, is now reaching its inflection point as was articulated in a special session organized by Applied Materials attached to this IEDM, the 14 nanometer node is expected to be an inflection point. Quoting from the abstract:

"The 14 nanometer node is expected to be an inflection point for the chip industry, beyond which the resistivity of copper interconnects will increase exponentially and may become a limiting factor in chip design. On December 11, 2012, Applied Materials, Inc. will host an important forum in San Francisco to explore the path that interconnect technology must take to keep pace with transistor scaling and the transition to new 3D architectures.” (emphasis added)

This had been illustrated before in the following chart:

And to make it crystal clear, IBM presented the following chart in its short course:

 
Power is now dominating IC design and clearly dimensional scaling does not improve the interconnect’s impact – see the following chart built from the ITRS Roadmap. The only effective path forward that addresses interconnect is monolithic 3D.

As for the second challenge – lithography – we start again with an old chart by Synopsys:

The implication is that any new node of dimensional scaling comes with escalating lithography costs; and sure enough, that’s what is happening. When litho costs are plotted over time, it fits a log-linear scale….this is not a sustainable trend.
The following chart illustrate the lithography escalating cost of equipment which directly reflect the wafer cost.

This resulted in the following slide by IBM at the GSA Silicon Summit 2012:

Quoting from the slide: "Net: neither per wafer nor per gate [are] showing historical cost reduction trends." Another EE Times IEDM12 article covering a keynote given by Luc van den Hove, chief executive of IMEC,  IEDM: Moore’s Law seen hitting big bump at 14 nm, repeats the same conclusion.

In fact, some vendors are already changing course accordingly. GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium (11 December, 2012) during IEDM12 week also acknowledged that their 14nm node will have a 20nm node metal pitch, and, just like GlobalFoundries, a similar die size and increase in per-transistor cost.
So it would seem that also for lithographic reasons, the industry’s next generation path, and the continuation of Moore’s Law, would be achieved by leveraging the third dimension.

Now that monolithic 3D is feasible and practical, the time has come to move in this new direction, as has been nicely illustrated by this concluding chart below:

SiTime Corp. introduced the SiT8920 MEMS oscillator for industrial and high reliability applications. While operating over the widest temperature range, -55°C to +125°C, the SiT8920 consumes half the power of quartz oscillators, is twice as stable, 20 times more reliable and 30 times more robust to shock and vibration. These key benefits dramatically improve system performance and reduce failures in harsh environments.

Piyush Sevalia, executive vice president of marketing at SiTime, said: “SiTime’s MEMS oscillators incorporate unique features that are simply not available from quartz products. For example, the SiT8920 incorporates SiTime’s unique SoftEdge rise/fall time control that reduces system EMI without additional components, expensive shielding or PCB re-design.”

SiTime is also introducing two additional devices that are well suited for replacing quartz oscillators and crystal resonators.

  • SiT1618 – a fixed-frequency oscillator that operates over -40°C to +125°C
  • SiT8918 – a programmable oscillator that operates over the same temperature range and supports any frequency between 1 and 110 MHz as well as 1.8V and 2.5 to 3.3V operation

 These new high-temp oscillators offer many unique features and benefits listed below.

  • Best robustness: 30 times better than quartz oscillators; 0.1 ppb/g vibration sensitivity; 50,000 g shock and 70 g vibration resistance
  • 500 million hours MTBF (2 FIT), 20 times better than quartz oscillators
  • ±25 PPM over the operating temperature for better system timing
  • Low power consumption: < 4 mA typical
  • Five industry-standard package options including a tiny 2.0 x 1.6 mm, all of which are drop-in replacements for quartz oscillators

The SiT8920, SiT8918 and the SiT1618 MEMS oscillators are sampling now with mass production scheduled for April 2013. Pricing is available upon request.

MEMS Industry Group (MIG) will host its second annual MEMS Executive Congress® Europe, March 12, 2013 in Amsterdam. This European edition of MIG’s executive event features an opening presentation by MIG Managing Director Karen Lightman, keynotes by Continental Automotive GmbH and SORIN GROUP, and panels exploring micro-electromechanical systems (MEMS) as a core enabling technology in both established and emerging markets.

“European companies and research organizations are breaking new ground in mobile communications, automotive systems, energy production and conservation, and medical/quality of life applications for aging populations—and a share of the astounding progress they are making is attributable to MEMS,” said Karen Lightman, managing director, MEMS Industry Group. “MEMS Executive Congress Europe allows the global MEMS community to tap into the expertise of some of the top European minds in these growing fields. It is a forum for exchanging vital information about business and market challenges and opportunities in using MEMS for life-improving and life-changing applications.”

Keynotes

  • Ralf Schnupp, PhD, vice president, Segment Occupant Safety & Inertial Sensors, Continental Automotive GmbH—“Future Trends in Automotive — Smart Systems and Sensors”
  • Renzo Dal Molin, PhD, advanced research director, SORIN CRM within Cardiac Rhythm Management business unit, SORIN GROUP—“Vision for Implanted Medical Devices Healthcare Solutions and Technical Challenges”

Panels

  • “MEMS in Consumer Products”—MEMS is pervasive in consumer electronics. Consumers are demanding—and receiving—more natural user interfaces in smartphones, tablets and remotes; more immersive gaming experiences; more personalized consumer-health applications; and so much more. European companies are leading innovation in this rapidly growing market—but why? Panelists will explore whether the climate for innovation, including corporate-government partnerships and consumer-OEM relationships, fosters greater innovation in the EU than in other regions. Panelists will also discuss the intense pressures of this highly competitive but lucrative market.
  • “MEMS in Automotive”—MEMS has been critical to advancements in the automotive industry for decades, starting with accelerometers in airbag crash sensors and other automotive safety and environmental control applications. Today MEMS is opening a whole new world of safety, energy-efficiency and performance features in automotive. We are moving towards cars that drive themselves, zero-emission vehicles, and automobiles that meet the ubiquitous connectivity needs of today’s consumer. Panelists will examine how MEMS is enabling new classes of applications in the well-established yet highly competitive and consumer-driven automotive industry. They will explore the maturation of MEMS components into essential elements used in every new automotive technology—and will examine if lessons learned on the journey can be applied to other applications and industries.
  • “MEMS in Energy”—the energy industry is undergoing significant change—from deregulation in existing markets and expansion into new energy sources and regions to the rapid increase of energy costs. With current energy sources not able to meet future global demand, we require new solutions that are portable and highly efficient. Once again the EU is leading the way. European organizations are looking to MEMS in harnessing alternative energy and in generating more energy-efficient, lower-cost power. Panelists will discuss current MEMS initiatives for energy applications and will explore areas of the energy industry that might benefit from integration with MEMS.
  • “MEMS in Medical — Focus on Aging”—medical and quality of life applications that allow people to live longer and more independently are gaining mindshare—and market share. With medical-device manufacturers increasingly pursuing growing commercial opportunities, they are turning to MEMS for patient monitoring, management, rehabilitation, replacement, and drug delivery, including microfluidics. As people in the developed world live longer, and expect a high quality of life to the very end, how can MEMS help to meet the needs of a vast and aging populace? Panelists will address the MEMS’ connection to lifesaving and life-enhancing applications.

About MEMS Executive Congress Europe 2013

MEMS Executive Congress Europe 2013 brings together business leaders from a broad spectrum of industries: automotive, industrial/energy, biomedical/quality of life, and consumer goods. It is a unique professional forum at which executives from companies designing and manufacturing MEMS technology sit side-by-side with their end-user customers in panel discussions and networking events to exchange ideas and information about the use of MEMS in commercial applications.

Premier sponsors of MEMS Executive Congress Europe include: Platinum Sponsor – EV Group; Gold Sponsor – SPTS Technologies; Silver Sponsors – Analog Devices, STMicroelectronics and SUSS MicroTec; and Bronze Sponsor – Applied Materials.

Sponsors include: Akustica, Bosch Automotive Electronics, Bosch Sensortec, Fries Research & Technology (FRT), imec, IVAM, Maxim Integrated, MEMS and Nanotechnology Exchange, MinacNed, Polytec, Roessingh Research and Development, Semicon Europa,Silex Microsystems, Solid State Technology and Tronics.

MEMS Executive Congress Europe will be held March 12, 2013 at the Steigenberger Airport Hotel, Amsterdam, The Netherlands. It is conveniently co-located with Smart Systems Integration 2013.

For more information, please contact MIG via phone: +1 412/390-1644, email: [email protected] or visit MEMS Executive Congress at: www.memscongress.com.

MEMS Industry Group (MIG) is the trade association advancing MEMS across global markets. Close to 150 companies comprise MIG, including Analog Devices, Applied Materials, Bosch, Freescale Semiconductor, GE, Honeywell, HP, Intel, InvenSense, Murata Electronics Oy, OMRON Electronic Components, Qualcomm Technologies, STMicroelectronics and Texas Instruments. For more information, visit: www.memsindustrygroup.org.

When a 300mm wafer is vacuum mounted onto the chuck of a scanner, it needs to be flat to within about 16nm over a typical exposure field, for wafers intended for 28nm node devices.1 A particle as small as three microns in diameter, attached to the back side of the wafer—the dark side, if you will—can cause yield-limiting defects on the front side of the wafer during patterning of a critical layer. The impact of back side particles on front side defectivity becomes even more challenging as design rules decrease.

Studies have shown that a relatively incompressible particle three microns in diameter or an equivalent cluster of smaller particles, trapped between the chuck and the back surface of the wafer, can transmit a localized height change on the order of 50nm to the front side of the wafer.2 With the scanner’s depth-of-focus reduced to 50nm for the 28nm node, the same back side particle or cluster can move the top wafer surface outside the sweet spot for patterning. The CD of the features may broaden locally; the features may be misshapen. The result is often called a defocus defect or a hotspot (Figure 1). These defects are frequently yield-limiting because they will result in electrical shorts or opens from the defective feature to its neighbors.

A particle on the back side of the wafer may remain attached to the wafer, affecting the yield of only that wafer, or it may be transferred to the scanner chuck, where it will create similar defects on the next wafer or wafers that pass through the scanner.

At larger design nodes, back side defects were not much of an issue. The scanner’s depth of focus was sufficient to accommodate a few microns of localized change in the height of the top surface of the wafer. At larger design nodes, then, inspection of the back side of the wafer was performed only after the lithography track and only if defects were found on successive wafers, indicating that the offending particle remained on the scanner chuck, poised to continue to create yield issues for future wafers. In this case corrective measures were undertaken on the track to remove any suspected contamination. The track was re-qualified by sending another set of wafers through it and looking for defectivity at the front side locus of the suspected back side particle. This reactive approach was economically feasible for most devices throughout volume production of 32nm devices.

At the 28nm node, however, lithography process window requirements are such that controlling back side particles requires a more proactive approach. Advanced fabs now tend to inspect the wafer back side before the wafer enters the scanner, heading off any potential yield loss. Scanner manufacturers are also encouraging extensive inspection of the back side of wafers before they enter the track. As we see what lithography techniques unfold for the 16nm, 10nm nodes and beyond, it’s entirely possible that 100% wafer sampling will become the best-known method.

As with inspection of the front side of the wafer, sensitivity to defects of interest (DOI) and the ability to discriminate between DOI and nuisance events are important. Even though particles need to be two to three microns in diameter before they have an impact on front side defectivity, the inspection system ought to be able to detect sub-micron defects, since small defects can agglomerate to form clusters of critical size. Sub-micron sensitivity is beneficial for identifying process tool issues based on the spatial signature of the defects—while high-resolution back side review enables imaging of localized defects, so that appropriate corrective actions can be taken to protect yield. Sub-micron sensitivity also serves to extend the tool’s applicability for nodes beyond 28nm.

For further information on back side inspection equipment or methodologies, please consult the second author.

Rebecca Howland, Ph.D., is a senior director in the corporate group, and Marc Filzen is a product marketing manager in the SWIFT division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

Notes:

1.       Assuming 193nm exposure wavelength, NA = 1.35 and K2 = 0.5, then depth of field = 50nm. Normally 30% of the DOF is budgeted for wafer flatness.

2.       Internal studies at KLA-Tencor.

January 25, 2012 – Given the ascension of smartphones, it’s no surprise that Samsung and Apple remain far and away the biggest end-users of semiconductors, and are widening their lead on the rest of the field, according to the latest Gartner rankings.

Together they consumed $45.3 billion worth of semiconductors in 2012, nearly $8 billion more than in 2011, growing double-digits while overall chip consumption fell -3% (and several top-10 chip consumers actually fell by double-digits). They now represent 15% of the entire market for chips, up from 12% in 2011. (Samsung also has a big IDM foundry operation by which it supplies chips to others, including Apple.)

A weak macroeconomic environment, and a "dramatic change" in consumer demand hampered overall semiconductor demand in 2012, explained Masatsune Yamaji, principal research analyst at Gartner. The PC market still represented the largest end application, but the market noticeably shifted from traditional desktop and mobile PCs to mobile devices such as smartphones and media tablets which contain less semiconductor content.

On the flip side, the limited computing and storage capabilities of new mobile computing devices will require more resources in cloud computing services, meaning data centers and communications infrastructure will continue to be a key demand driver for semiconductors, Yamaji pointed out. Another factor in mobile computing devices: there’s been very little hardware differentiation, as new capabilities are quickly proliferated among other hardware vendors with commercial system-on-chip (SoC), software, and reference designs. "Semiconductor vendors must aid, or at least monitor, the hardware innovations of the market leaders," he says.

Top 10 semiconductor design total available market (preliminary) in US $B. (Source: Gartner)