Category Archives: SST

Engineering samples of The Hybrid Memory Cube (HMC) are expected this summer, with high volume manufacturing coming next year. It will be one of the first high volume devices employing 3D integration and through silicon vias (TSVs), employing a bottom logic layer and 4-8 stacked DRAM layers.

The HMC is the result of a consortium formed in late 2011 by Micron, Samsung, Altera, Xilinx and Open-Silicon to define an industry interface specification for developers, manufacturers and architects of high-performance memory technology. The consortium has grown to 110 members, including SK Hynix, IBM and ARM. Analysts are projecting the TSV-enabled 3D market to be a $40billion market by 2017, or roughly about 10% of the global chip business.

We caught up with Micron’s Scott Graham, General Manager, Hybrid Memory Cube, at Semicon West. “Today, we’re very close to delivering our engineering samples this summer to our lead customers that are taking the technology into their system designs,” Graham said.  The lead applications are in high performance computing, such as supercomputers, as well as the higher end networking space. “Those will be the early adopters. As we move forward in time, we’ll see that technology evolve as costs come down for TSVs and manufacturing technology, it will enter into future space where traditional DDR type of memory has resided. Beyond DDR4, we can certainly see this of memory technology being a mainstream memory,” Graham said.

Since the HMC is an open specification in terms of the architecture of the device, it will be up to each memory manufacturer to decide how it might be customized and manufactured. “The way it’s done today is we source the substrate, we source the logic layer and then we bring those in-house and we complete the finishing of those logic wafers as well as all the slicing, dicing, stacking, assembly and test,” Graham said. “What we end up providing for the customer is a known good cube, or known good piece of memory, just like we would if it was a DDR device or wide I/O device,” he said. He added that the HMC is designed so that it has not only the repair capability during manufacturing but also out in the field. “It’s very flexible and very robust, so reliability is very high with this device,” he said.

The consortium delivered its first specification earlier this year. “We’ve since extended the consortium to work on both future generations of the HMC technology in both the short-reach and ultra-short reach configurations,” Graham said.

The HMC was designed to get high density and high bandwidth in a relatively small package. The team adopted an off-the-shelf SERDES I/O and that’s based on IBM’s 32nm process. “With that, we can achieve 10 Gbps, 12.5 Gbps, or 15 Gbps for those SERDES links,” Graham said. “If you look at a 2 GByte or a 4GByte HMC device, those first devices will deliver a total aggregate bandwidth of 160GBytes/sec. I want to emphasize those are bytes not bits. It’s a very high bandwidth and low energy per bit device that is something that can be designed into a multitude of systems.”

The consortium has several generations of the HMC device planned (this summer’s engineering samples are Gen2). “As we move forward, you’ll see us moving into the 28 Gbps SERDES as far as the I/O goes,” Graham said. Bandwidths are going to be 320 Gigabytes/sec and higher, and the density will be in 4Gbyte and 8 Gbyte configurations.

Graham said one of the main challenges they had to overcome was the stacking. “We’re stacking a logic layer on top of a substrate and then four to eight DRAM on top of those logic layers,” he said. “We have over 2000 TSVs in this package and it was a challenge to stack these ultrathin die and make sure that what we end up with is a high performance and very reliable package.” Graham declined to comment on the exact TSV process flow used at Micron, saying only that it was leading edge. “We had to make sure our equipment partners were up to speed and could deliver us the technology that would allow us to manufacture this in high volume,” he said.  

Because customer can customize the HMC design, another challenge it to make sure that the design capabilities are available at the foundry for that logic layer, Graham said.  

Heat dissipation in the device is achieved through a metal lid, and through the TSVs which acts as chimneys (in addition to conducting electricity). The photo shows two Gen2 HMC devices. The larger one, in a 31mm x31 mm package, is a 4 link device that will achieve 160 Gig-bytes per second. The smaller one is a two link device capable of 120 Gigabytes/sec, measuring 16mm x 19.5 mm. “Both are being manufactured now in our plant and we’re doing the whole debug phase,” explained Aron Lunde, program manager, DRAM solutions group at Micron in Boise. He said the metal lid was in contact with not only the top layer, but different internal layers. “We call it an integrated heat spreader. It makes contact at more than one level and that’s what really helps,” he said.

Although manufacturers such as Micron, Samsung and SK Hynix must now handle the manufacturing, assembly and test process, Graham believes that it could eventually evolve to the point where select foundry partners would be able to provide volume manufacturing services for these HMC cubes.

Graham said DDR4 will likely be the last DDR device. “Beyond DDR4, you have to move to managed memory like HMC technology,” he said.  “We’re solving the memory wall problem with HMC-like architecture and what’s really going to be happening in the future is that you’ll be running into a CPU wall. That’s going to be the barrier to system progress as we move forward.”

Graham expects some challenges with scaling of conventional memory at sub-20nm process nodes. “We get into physical challenges of meeting the timing requirements and the 12 pages of JEDEC specifications to be able to yield properly and to be able to provide a cost-effective memory device moving forward,” he said.  

Although the HMC is now designed around DRAMs, Graham said it would be possible to use other types of memories, and even a mixed set of memories. He noted Micron is looking at alternatives to the conventional DRAM cell, such as spin torque and resistive memories. “Micron is investing heavily in research in those technologies and of course the HMC team here at Micron is looking at future technologies that we can take HMC architecture and be able to utilize different DRAM or even flash types of memory,” he said. “As the technology matures and it becomes lower cost, we can see this technology certainly evolving into more global applications and utilizing different memory types in that stack – and perhaps even multiple memory types in that stack.”

HMCs could eventually make their way into mobile devices, but Graham said that is likely to be three or four years away. Mobile applications presently employ low power DDR3 solutions, which will be used for several years. “We’ll see quite a few interesting designs start spinning when the mobile folks see they can differentiate with a managed memory solution. It’s not going to be HMC as we know it today, it will have to be optimized for mobile,” Graham said.

Executives from the world’s leading microelectronics companies will meet with delegates representing Vietnamese government, academia, research, and industry to explore and discuss the key strategies and opportunities in the growing Vietnam semiconductor industry at the SEMI Vietnam Semiconductor Strategy Summit. The Summit will be held on September 9-10 at the InterContinental Asiana Hotel in Ho Chi Minh City. The event includes an optional tour of the Saigon Hi-Tech Park where Intel’s assembly and packaging plant is located, followed by a one-day executive conference and networking event.

Following Intel’s successful $1 billion in manufacturing investment in Ho Chi Minh City, and the government’s recent decision to invest in a 200mm/0.18 micron front-end fab, Vietnam will become an alternative design and production location for electronics and semiconductor manufacturers in Southeast Asia.  The executive event will bring together the key decision-makers shaping the future of the industry in Vietnam and help forge the connections and relationships that will drive further growth over the next decade and beyond.  A featured presentation will provide perspectives on infrastructure and technology requirements for the new 200mm fab presented by executives from M+W and FabMax.

While both the Vietnamese and Ho Chi Minh City governments have made investments in both front-end and back-end semiconductor manufacturing a priority, advancing the semiconductor industry in Vietnam will also require development of the local supply chain, allocation of water and energy resources, a growing skilled workforce, partnerships with established microelectronic markets, and other infrastructure needs.

The SEMI Vietnam Semiconductor Strategy Summit is organized by SEMI and co-organized by the Saigon Hi-Tech Park (SHTP) and the Ho Chi Minh City Semiconductor Industry Association (HSIA). Participation in the SEMI Vietnam Semiconductor Strategy Summit is available exclusively through corporate sponsorship or by invitation.

Current sponsors include Kulicke & Soffa, Millice, KLA-Tencor, Disco, Advantest, and FabMax.  Several sponsorship categories are provided that offer different levels exposure and benefits.  For additional information on corporate sponsorships and to inquire about an invitation, please contact [email protected] or visit www.semi.org/vietnam

Smart lighting is an advance technology in lighting that makes use of intelligent lighting control systems to intelligently control light based on various parameters like occupancy, movement, color temperature, amount of natural/daylight etc. Smart lighting market is growing at a phenomenal way and main drivers for this growth are energy efficiency, development in electronics and sensor technology, eradication of incandescent lamps, favorable government policies and evolution of novel wireless technology. Entry barriers are low for this market and many new players are arriving in this market. For example: the smart lighting market in the U.S. is being dominated by start-ups that are just three years old. In the present scenario, many companies are launching new products in the market. It can be observed that LED-based products which are based on wireless technology are being launched at a large scale at present.

At present, Europe has the largest market for smart lighting especially in commercial industrial buildings, outdoor lighting, and automobiles applications. The presence of lighting giants like Philips (The Netherlands), Osram Gmbh (Germany) and Zumtobel AG (Austria) is an important reason behind the implementation of smart lighting system in this region. Smart lighting has the second largest market in North America. Several new players have emerged in this region, especially in the U.S., who has developed breakthrough products related to smart lighting. APAC is the emerging market for smart lighting. It is believed that market will grow at an exponential rate of 37.7 percent between 2013 and 2018.

Commercial and industrial buildings are the most prominent application of smart lighting. In commercial buildings, lighting adds up to 40 percent of total energy cost. Deployment of intelligent lighting control is being supported by building owners, governments, utilities, and many other stakeholders as it helps to drastically reduce energy consumption. Public and government building have the second largest share among all application in the smart lighting market. As smart lighting projects for public and government buildings are government-funded projects, the growth of this application area will be stable as it would be given priority in every economy. Residential buildings application has largest growth potential and will grow at the highest CAGR of 87.5 percent from 2013 to 2108 when compared with other application. Initial investment will pose as a restraint initially, however it is predicted that once the customers become aware of the energy savings benefits of intelligent lighting system in the long run, it will grow exponentially. Outdoor lighting application is another promising application. The greatest opportunity area in this market is the prospect of its integration with other important systems in the city like traffic signals, energy meters, pollution sensors, parking-lot lights, and traffic sensors to form a smart city. Smart lighting systems are mainly employed by high end cars. Companies like Mercedes-Benz and Audi have already incorporated the systems in their luxury cars.

 

With most of the top brands introducing new flagship models in the first half of 2013, smartphone buyers now have more choices than ever, a phenomenon that will contribute to an expected doubling in market shipments from 2012 to 2017.

Worldwide smartphone shipments will reach 1.5 billion units in 2017, up from 712 million in 2012, according to a new Mobile & Wireless Communications Report from information and analytics provider IHS Inc. Shipments this year are set to rise to 897 million units, up from 712 million in 2012, as shown in this figure.

In the years that follow, shipments of smartphones will expand at a compound annual growth rate (CAGR) of 15.8 percent, reaching 1.1 billion units in 2014, followed by 1.2 billion in 2015, and 1.4 billion in 2016.

“The volume of new flagship smartphone releases from top original equipment manufacturers (OEM) this year has been astounding,” said Wayne Lam, senior analyst for consumer and communications at IHS. “These include the new BlackBerry Z10, the aluminum uni-body HTC One, and an update to the Samsung Galaxy S4 featuring a Full HD 5-inch active matrix organic light emitting diode (AMOLED) display.”

On the other hand, Apple’s iPhone franchise appears to be stalling as first-quarter shipments of 37.4 million fell below expectations. With the next iPhone model not expected until the second half of the year, there is a real possibility that the full-year 2013 sales volume of the iPhone may be essentially flat at around 150 million units, compared to 134 million units in 2012.

“The possible slowing growth of the iPhone and the rapid pace of competitive smartphones releases speak to the ferocious nature of the handset business, especially now as the market continues to pivot from a market dominated by lower-end handsets known as feature phones to one that is increasingly smartphone-centric,” Lam said.

Outshipped

The trend of deeper smartphone penetration continued in the fourth quarter of 2012 and the first quarter this year, as smartphones outshipped feature phones in the overall branded cellphone market.

After a seasonally high fourth quarter, which saw total mobile handset shipments topping 400 million units for the first time, handset shipments in the first quarter of 2013 contracted by nearly 50 million units quarter-over-quarter, keeping with seasonal sales trends.

Samsung continued its strong growth in the first quarter with a sequential increase of 9 million units, while  brands such as Coolpad and Gionee outshipping the likes of HTC and Motorola in the first quarter.

Chinese smartphone OEMs were able to accomplish such growth on the back of a catalog of largely affordable smartphones, while Samsung rolled out a number of low-cost variants to its high-end flagship products.

These competitive forces, as well as changing consumer demand, will place pressures not only on Apple but also on other OEMs, IHS believes, forcing players to innovate and diversify smartphone offerings in order to continue growing.

Just innovate

Innovation in smartphone design is becoming a necessity for OEMs as consumers demand more immersive user experiences and visual content. Many smartphones, for instance, are moving to 5-inch or larger full HD displays to accommodate consumer desire for these experiences.

In parallel with an expanded display, the overall footprint of smartphones is likewise increasing because of larger batteries, which will then allow for more powerful processors, associated memory and sensors.

But these expanded features come at a cost to OEMs, driving up the dollar content of electronics and pushing the bill- of-materials (BOM) cost for the devices. Still, as variations in smartphone designs increase, opportunities to win design slots multiply as well for component suppliers—developments that bode well for the overall smartphone supply chain.

The latest trends, challenges and business opportunities in advanced materials for semiconductors, MEMs, power devices, storage, and other electronic devices will be addressed at the 2013 SEMI Strategic Materials Conference (SMC), to be held on October 16-17 at the Santa Clara Marriott in Silicon Valley, California. Electronic device manufacturers, materials suppliers, market analysts, and other industry experts will speak and participate in the only executive conference in the world dedicated to advanced electronic materials.  Last year’s conference sold out and attendees are encouraged to register early to ensure participation.

Organized by the Chemical and Gas Manufacturers Group (CGMG), a SEMI Special Interest Group comprised of leading manufacturers, producers, packagers and distributors of chemicals and gases used in the microelectronics industry, SMC offers presentations from leading market analysts, device manufacturers, industry consortiums, top suppliers and academic researchers, in combination with an innovative interactive format designed to facilitate business contacts and networking. SMC also provides valuable forecasting information, helps accelerate advanced materials markets, and serves as a forum for collaboration among all sectors of the advanced materials supply chain. Over 94 percent of the attendees at last year’s conference said SMC provided information useful to their jobs and provided valuable business contacts.

Featured topics for the two-day conference will include:

  • New materials and processes for next generation memory
  • Material metrology and characterization challenges at leading-edge nodes
  • Graphene and other carbon-based materials for semiconductor, storage, and industrial applications
  • Materials challenges for MEMS devices
  • Wafer processing and packaging materials outlook
  • The coming revolution in wide bandgap semiconductors
  • Latest advances in printed, large area and flexible electronics

The Strategic Materials Conference has provided valuable information and networking opportunities to materials and electronics industry professionals since 1995. Held this year at the Santa Clara Marriott in the heart of Silicon Valley, the event provides critical forecasting, emerging market, and materials trends for the microelectronics industry.

For more information and to register, visit www.semi.org/smc

 

DRAM average selling prices (ASPs) have increased every month throughout 2013 and are now at levels last seen in October 2010, according to data in IC Insights’ Mid-Year Update to The McClean Report, which will be released at the end of this month.  On a quarterly basis, the DRAM average selling price jumped an estimated 42 percent in 2Q13 compared to the same period in 2012.  The increase followed a 22 percent rise in 1Q13. IC Insights forecasts the DRAM ASP will grow to $2.53 in 3Q13, 50 percent greater than in 3Q12, and then taper slightly to $2.52 in 4Q13, which would represent a 46 percent increase compared to 4Q12.

The increase in DRAM average selling prices has not come as a complete surprise.  One factor contributing to rising prices is the fact that fewer suppliers are participating in the DRAM market today compared to 2010.  Micron is (still) expected to complete its acquisition of Elpida Memory and two prominent Taiwan IC suppliers (Powerchip and ProMOS) have essentially exited the commodity DRAM business.  Consequently, shipments of DRAM are in the hands of (and more tightly controlled by) fewer suppliers.

Meanwhile, several years of greatly reduced capital expenditures in the DRAM market have resulted in little new capacity being added.  DRAM capital spending as a percent of sales has dropped from 31 percent in 2011, to 19 percent in 2012, and is forecast to decline 12 percent in 2013.  With little new capacity being added, the supply-demand balance is now favoring DRAM suppliers as demand (particularly for higher-priced mobile DRAM) is beginning to outstrip supply, resulting in upward pressure on prices.

Third, the computer industry is undergoing a major transition to mobile computing.  Shipments of smartphones and tablet PCs are increasing rapidly while shipments of traditional notebook and desktop PCs are falling.  Most DRAM suppliers have changed their product mix to meet the needs of the growing mobile market.  DRAM suppliers have scaled back their output of lower-priced commodity PC DRAM and transitioned to higher-priced, low-power, mobile DRAM.  Even though DRAM unit shipments are forecast to fall eight percent in 2013, the DRAM average selling price is expected to jump 40 percent for the year. After DRAM market declines of 25 percent in 2011 and 11 percent in 2012, IC Insights now forecasts the volatile DRAM market to grow 28 percent in 2013.

Micron Technology, Inc., today announced that it is sampling next-generation, 16-nanometer (nm) process technology, enabling the industry’s smallest 128-gigabit (Gb) multi-level cell (MLC) NAND Flash memory devices. The 16nm node is not only the leading Flash process, but it is also the most advanced processing node for any sampling semiconductor device.

Micron’s 128Gb MLC NAND Flash memory devices are targeted at applications like consumer SSDs, removable storage (USB drives and Flash cards), tablets, ultrathin devices, mobile handsets and data center cloud storage. The new 128Gb NAND Flash memory provides the greatest number of bits per square millimeter and lowest cost of any MLC device in existence. In fact, the new technology could create nearly 6TB of storage on a single wafer.

“Micron’s dedicated team of engineers has worked tirelessly to introduce the world’s smallest and most advanced Flash manufacturing technology,” said Glen Hawk, vice president of Micron’s NAND Solutions Group." Our customers continually ask for higher capacities in smaller form factors, and this next-generation process node allows Micron to lead the market in meeting those demands.”

“Cost reductions will always be fundamental to the NAND industry and so companies who can continue to lead on the flash process technology will be poised for success, particularly in vertically integrated solutions,” according to Gartner.*

Micron is sampling the 16nm, 128Gb MLC NAND with select partners now and plans to be in full production in 4Q13. Micron is also developing a new line of solid-state drive (SSD) solutions based on these devices and expects to ship SSDs with 16nm Flash in 2014.

Micron NAND

Researchers sponsored by Semiconductor Research Corporation (SRC), the world’s leading university-research consortium for semiconductors and related technologies, today announced that they have developed a more efficient purge technique that reduces the consumption of ultra-high purity (UHP) purge gases by more than 20 percent during the production of semiconductors. The new process has been co-developed with Intel Corporation and can be applied to a wide range of manufacturing operations beyond the chip industry.

In response to industry demand, the research performed by the SRC Engineering Research Center (ERC) for Environmentally Benign Semiconductor Manufacturing has focused on minimizing the amount of UHP bulk gases used to purge and clean tools and gas distribution systems. The new technique—called Pressure Cyclic Purge (PCP)—can easily replace the industry’s standard steady-purge method while delivering welcomed energy and gas savings.

Currently, the widely used conventional steady-purge method for cleaning and drying highly sensitive equipment and gas distribution systems requires flowing large amounts of expensive gases through production equipment and distribution systems; this procedure results in higher cost and waste of consumables. As contamination continues to be a major concern in scaling devices to smaller feature size for enhanced density and performance, the inefficient use of expensive purge gases to eliminate contaminants is a key challenge to the productivity of future IC technologies.

“The widespread use of ultra-pure gas for purging purposes, which essentially all goes to waste, has been a significant environmental and efficiency issue for more than a decade,” said Farhang Shadman, lead researcher and the ERC Director at the University of Arizona for the SRC-funded research. “Reduction of both UHP gas usage as well as the resources used for purification processes are environmental gains in the fab, as well as in the production and supply of these gases.”

Through direct measurement and system simulations, the SRC-supported research has demonstrated that the unique flow and cyclic change in the new PCP technique utilizes substantially smaller amounts of purge gases and achieves the required cleanliness in a shorter period of time. For example, the new approach can accelerate the time for the industry’s standard gas distribution system ‘dry down’ process by greater than 30 percent for large, complex systems with the PCP technique.

“Continual increase in environmental quality and cost-effectiveness are on-going goals for our R&D and we have already demonstrated the benefits of this new approach at several sites,” said Carl Geisert, Senior Principal Engineer at Intel. “As we continue to push reduction of contaminant levels towards the parts per trillion level, collaboration between industry and the ERC is key to continued progress toward our goals.”

In addition to Intel, other SRC members have access to a simulator program that can be customized with the PCP technique for their needs. Tests with the new purge technique suggest that the simulator will be ready for commercialization by early 2014. The PCP technique is expected to be relatively easy to implement with minimal change in hardware or configurations for existing fabs and facilities.

In addition to semiconductor equipment and manufacturing companies, other industries that use ultra-clean gases for planar or patterned surfaces and small structures should also benefit from this technology. For example, makers of optics, optoelectronics and flat panel display are expected to show great interest in the tightly regulated semiconductor manufacturing processes such as the PCP technique. As this new purge technology moves quickly toward commercialization, development is underway for its integration into various process tools.

“This progress is reflective of the kinds of innovative approaches that simultaneously provide environmental gain, process improvement and cost reduction for semiconductor and other industries,” said Bob Havemann, Director of Nanomanufacturing Sciences at SRC. “That’s been the legacy and the mission of the SRC Engineering Research Center in the projects that we conduct jointly with industrial members for the purpose of enhancing the environmental sustainability of semiconductor manufacturing.”

Part 1 of this blog covered International Technology Roadmap for Semiconductors (ITRS) updates to System Drivers, Design, Modeling and Process Simulation, Process-Integration Device and Structures (PIDS), and Front-End Processing, as presented in a session on the last day of SEMICON/West 2013.

SEMATECH’s Mark Neisser provided a sobering overview of the challenges associated with extending Lithography technology to pattern device structures below a half-pitch of 20nm. The ITRS Lithography International Technology Working Group (ITWG) works with pitch and half-pitch ranges as lithographically determined and so do not have an exact correspondence to “nodes.” ArF light sources at 193nm wavelength have been extended as far as possible using immersion, and all so-called “next-generation lithography” (NGL) technologies have problems, such that it’s unsure if any will be ready at the decision points needed insertion into future chip-making lines. Today, we can look at anticipated  half-pitch ranges needed for proposed device structures and determine which proven technologies could be used:

  • 30-20nm half-pitch is the limit of ArF Double-Patterning,
  • 19-15nm half-pitch is estimated as the limit of EUV Single-Patterning,
  • 14-11nm half-pitch is estimated as the limit of ArF Quadruple-Patterning, and
  • 10-8nm half-pitch corresponds to the estimated limit of EUV Double-Patterning at the current NA.

“The industry needs an alternative to Quadruple-Patterning,” opined Neisser, “and the price-per-bit won’t necessarily go down.”

Front End Processes (FEP) needed for future chip-making were reviewed by Joel Barnett of Tokyo Electron. The FEP team is in flux, and Barnett solicited new team members. “Really what’s driving FEP these days is new materials for both logic and memory,” explained Barnett. New materials raise unpredictable integration challenges, for deposition, etch, cleaning, and metrology. We need to know the correlation between electrical properties and materials structures, and how can interfaces be engineered. Continued scaling of High-Performance finFET logic devices is challenging in all aspects:  EOT, junctions, mobility enhancement, new channel materials, parasitic series resistance, and contact silicidation. Fin pitch has now been set by consensus with the PIDS and Lithography ITWGs to be 0.75 of M1 pitch.

Emerging Research Devices (ERD) that could replace standard CMOS FETs were discussed by An Chen of GLOBALFOUNDRIES with an emphasis upon novel memory technologies. One surprise was the removal of “nano-mechanical memory” from tracking in the main ERD table due to lack of progress. Resistive-RAM (RRAM) is now anticipated to move into commercial manufacturing in 2018, and the ERD ITWG plans to start tracking 4 different RRAM technologies in a new table: conductive-bridge RAM (CBRAM), metal-oxide bipolar filament, metal-oxide unipoloar filament, and metal-oxide bipolar interface effect. Unlike conventional Flash many emerging memory devices need a “select device,” and while transistors provide the best performance 2-terminal devices are more easily scaled. On the logic side, ERD anticipates new devices with “learning capabilities” to be developed in the long-term such as neuromorphic chips.

Emerging Research Materials (ERM) that could be needed to integrate new functionalities into integrated circuits were shown by C. Michael Garner, now with Stanford and Garner Nanotechnology Solutions. Alternate-channel materials such as Ge and III-V compounds seem destined to be used in future CMOS, and the best results to date combine Ge pMOS with III-V nMOS. However, integration cost and complexity would be reduced if only one new material could be coaxed into use as the alternate-channel, and so there is continuing work on Ge nMOS and III-V pMOS transistors. Contacts are important for all new materials, so the engineering of atomic-interfaces will be critical for future devices.

“A few people have demonstrated that providing a very thin barrier counter-intuitively lowers contact resistance,” shared Garner.

Click here for more news from SEMICON West 2013.

In the afternoon of the last day of SEMICON/West 2013, a session was devoted to updates from the International Technology Roadmap for Semiconductors (ITRS) Front End of Line Technologies. Representatives from the different International Technology Working Groups (ITWG) provided highlights from the work now happening on the 2013 update.

Andrew Kahng of U.C. San Diego provided two presentations on challenges associated with future ICs:  System Drivers and the Design. Systems today are clearly driven by System-on-Chip (SoC) and mobile. The size of a typical mobile phone SoC is expected to double from ~50 mm2 to ~100 mm2 due to increased  integration of new functionalities such as Graphics Processing Units (GPU), memory controllers, and input/output (I/O) interfaces. Overall power for such a chip in the distant future would consume >200W of power compared to today’s ~8W unless new technologies are employed. Some future drivers such as medical and defense are now in question; will these segments develop unique devices and processes or will they simply ride on the progress of mainstream commercial IC development.

“The latter scenario is looking more likely now,” said Kahng.

Constant area-factors allowed prior node scaling to be 2x, however since 2009 the real scaling has been 2E(2/3)x or ~1.6x due to an “IC Design Gap.” This gap is due to overheads from non-core blocks and additional overheads from PIDS effects on the area needed for cores. Design cost for a SoC consumer portable chip in 2011 were $40M, helped by commercial EDA software advances over the last decades. Today only at most 2.4 percent of the logic in an SoC is turned on at any time, which is how the power can be kept to ~8W.

Modeling and Process Simulation challenges were covered by Lothar Pfitzner of Fraunhofer IISB, with understanding that the overarching goal of this ITWG is to use virtual cycle-of-learning to lower R&D costs. To do so there are different models needed in different conceptual domains, “based on quantitative physical understanding of processes, devices, circuits, and systems,” explained Pfitzner. “Both short-term and long-term challenges remain in modeling of chemical, thermo-chemical and electrical properties of new materials.”

PIDS updates on logic, DRAM, and Non-Volatile Memory (NVM) were provided by Mustafa Badaroglu of Qualcomm. PIDS mission is to forecast device technologies likely to be used 15 years in the future of main-stream manufacturing. With Denard-scaling now part of history, the specifications for future transistors using either FD-SOI or multi-gate (such as finFET) technologies require TCAD simulations of source-to-drain tunneling, band structure effects due to strong confinement, as well as crystallographic orientation and strain. The current target is an overall eight percent power reduction per year in logic, but parasitics dramatically limit device performance, and gate-length scaling is endangered by increased tunneling.

A 2013 survey recently done by the Japan PIDS regional group provides a consensus on when new devices are expected to reach volume manufacturing. For DRAM cells there has been a slight relaxation of the planned half-pitch, and  the cell size transition from 6F2 to 4F2 planned for 2016 (delayed by two years from the last ITRS update), and vertical transistors are likewise planned for 2016. RRAM is now planned as mainstream technology in 2018, and is projected to catch-up with the bit density of 3D Flash in 2021; however, development of a selector diode in a 3D architecture remains a challenge. The Purdue University TCAD tools (NanoHub) will continue to be developed to better project device characteristics, and new websites within NanoHub will be created to allow free public access to the tools.

Part 2 of this blog will cover ITRS updates on Lithography, Front-End Processing, and Emerging Research Materials/Devices.

Click here for more from SEMICON West.