Category Archives: SST

At Leti Day during SEMICON West, Leti Lithography Program Manager Serge Tedesco highlighted different lithography options for advanced technology nodes. Dr. Tedesco suggested that an “optical forever” solution using 193nm immersion lithography in combination with a pitch-multiplication strategy could well provide lithography solutions to very advanced nodes on the industry’s technology roadmap.

Nevertheless, this option will face cost issues, and maskless lithography (ML2) and directed self assembly (DSA) could be very effective as complementary techniques that provide significant cost reductions on some critical levels.

To support their development, Leti created two industrial programs, IMAGINE for ML2, and IDeAL for DSA. Tedesco presented the roadmaps and technical status for both programs, which include large consortiums of industrial partners: IMAGINE around MAPPER Lithography tools, and IDeAL around Arkema’s block copolymer materials for DSA.

Tedesco also noted that Leti’s goal with both programs is to set up the necessary infrastructure to support the industry’s transition toward these complementary technologies.

Biography Dr Serge Tedesco:

Serge Tedesco joined CEA-Leti in Grenoble to take charge of e-Beam lithography, and consequently all advanced lithography activities. Since 2003 he has managed CEA-Leti’s lithography strategy and programs as lithography program manager. Dr. Tedesco has authored or co-authored more than 110 papers in the field of lithography and is a program committee member of the major International lithography conferences. He has been involved in numerous European projects, both as project leader and expert.

CEA-Leti and EV Group (EVG) have launched a three-year common lab to optimize temporary- and permanent-bonding technologies related to 3D TSV integration and all direct bonding heterostructures. 

The lab, which continues more than 10 years of collaboration between the two organizations, is focusing on hardware, software and process development.

“Temporary and permanent bonding equipment and process solutions are key product offerings for EVG,” said Markus Wimplinger, EVG’s corporate technology development and IP director. “This project leverages CEA-Leti’s global leadership in wafer-bonding research and EVG’s unparalleled expertise in developing wafer bonding equipment and process technology.”

“Like all common labs that Leti creates with its partners, this project is designed to produce specific, practical solutions that address current and future market requirements,” said Laurent Malier, CEA-Leti CEO. “This collaboration is targeting results that will make 3D TSV integration more efficient and cost effective and open new areas of wafer bonding using covalent bonding at room temperature.”

“Bringing these approaches to high-volume manufacturing with reliable wafer bonding requires innovative fabrication processes,” said Fabrice Geiger, head of Leti’s Silicon Technology division. “The new equipment and process technology developed within the common lab will allow exciting possibilities, especially for heterogeneous materials stacks, that require very low-temperature wafer bonding.”

Leti is an institute of CEA, a French research-and-technology organization with activities in energy, IT, healthcare, defence and security. Leti is focused on creating value and innovation through technology transfer to its industrial partners. It specializes in nanotechnologies and their applications, from wireless devices and systems, to biology, healthcare and photonics. NEMS and MEMS are at the core of its activities. CEA-Leti operates 8,000-m² of clean room space on 200mm and 300mm wafer platforms. It employs 1,700 scientists and engineers including 320 Ph.D. students and 200 assignees from partner companies. CEA-Leti owns more than 2,200 patent families.

EV Group (EVG) is a supplier of equipment and process solutions for the manufacture of semiconductors, microelectromechanical systems (MEMS), compound semiconductors, power devices, and nanotechnology devices.  Key products include wafer bonding, thin-wafer processing, lithography/nanoimprint lithography (NIL) and metrology equipment, as well as photoresist coaters, cleaners and inspection systems.  Founded in 1980, EV Group services and supports an elaborate network of global customers and partners all over the world.

Click here for more announcements from SEMICON West 2013 or follow us on Twitter.

SEMICON West 2013 included a robust set of technical and marketing presentations on the general theme of developing new semiconductor devices in the session “Lab to Fab: From R&D to High Volume Manufacturing” held 1:30-3:30PM on July 9. Ably moderated by Paula Doe, the session included presentations on modeling, experimenting, and prototyping new materials and structures such that they can profitably moved into high-volume manufacturing (HVM). Two of the presentations that described not just technologies but new fundamental methodologies for R&D came from Coventor and Intermolecular, small innovative companies based in Silicon Valley.

Dr. David Fried, CTO of Coventor, presented how the company’s “SEMulator3D” software modeling product based on “voxels” allows for advanced physics-based modeling of unit-processes, integrated-processes, device structures, and even device electrical parameters. The modeling starts with unit-processes such as depositions, etches, and epitaxial growth at the nanometer-scale. However, unlike TCAD and other device models, this software can also extend across length scales to provide full-wafer maps of physical parameters.

Fried explained how the model is built on data extracted from publicly available leading device information, such as the cross-section SEMs in Intel’s seminal IEDM paper on 22nm finFETs. The model is “behavioral” since it can predict the effects of changes in dynamic process conditions, and can therefore be used to do “virtual fabrication” of targeted devices. “You can do some interesting explorations,” explained Fried, “like what if you had a defect on a fin that was used to grow an epi-layer?” He showed how the complex interactions of different growth rates in different crystalline directions on 3D structures could be predicted by the software, and that the predicted structural shifts  appear to match the SEM cross-sections shown in the literature.

This modeling software can thus be used as a “virtual metrology” tool that can mimic real in-fab metrology. It can replace slow out-of-fab destructive characterization, and can provide local virtual measurements of structural parameters. It can be used to study the effects of incoming geometric parameters as well as process variations on the final structure. For example, the Cu cross-section area of a BEOL interconnect layer can be predicted, in contrast to unit-process models/controls that merely create wafer-uniformity-maps of  Etch, Cu-barrier/seed PVD, Cu-ECD, Cu-CMP, and other process steps.

Combinatorial R&D

Dr. Raj Jammy, Sr. VP & GM Semiconductor Group, Intermolecular, Inc.—most recently a SEMATECH VP—discussed the need for new ways of doing R&D now that the integration of new materials dominates device enhancements. As semiconductor technology has evolved to smaller and smaller device geometries, the number of new materials used on CMOS chips continues to increase. Consequently, the cost of discovering and integrating new materials into complex devices structures continues to increase.

New materials are needed for 3D FinFETs (alternate-channel materials), 3D Flash Memories and ReRAM (storage cells), and 3D packaging (through-silicon vias and through-mold vias), and all  use complex processes with unpredictable interactions. Developing and optimizing these new materials leads to high costs for R&D and even higher costs to integrate into HVM.

Intermolecular has created High Productivity Combinatorial (HPC™) tools for PVD, CVD, ALD, and wet-processing steps that allow for multiple site-isolated experiments to be done on a single 300mm wafer. When combined with throughput-match characterization tools using an automated database into what the company terms an application-specific “HPC workflow,” everything from an initial design-of-experiments (DOE) to full HVM integration can be done in 3-6 months instead of the 3-5 years needed by conventional R&D approaches.

HPC workflows can accelerate R&D in the early stages of materials exploration such that an entire cycle-of-learning can occur in just 4 hours. HPC workflows can also be used with short-loop flows through a customer’s fab to allow for a 3-4 week cycle-of-learning.

As an example of this methodology’s ability to accelerate learning, Jammy showed how hundreds of experimental parameters had to be explored in developing a germanium (Ge) MOS cap for CMOS integration. Variations in the substrate, surface cleaning, High-K stack, metal electrode, and post-treatment all play significant roles in determining the final device parameters. All these factors had to be co-optimized iteratively, and the project was accomplished in <3 months.

IMI started in 2004 with SanDisk and ATMI, and has since added Guardian Corp., Toshiba, IBM, First Solar, GlobalFoundries, Epistar, Micron as customers.

 

When Ajit Manocha, GlobalFoundries CEO, polled his audience during his keynote address on Tuesday at SEMICON West 2013, nearly 60 percent of the audience believed that the biggest challenge facing the semiconductor industry was the economy. However, during his presentation, Manocha seemed to suggest otherwise.

The technology business is booming, according to Manocha, who shared with SEMICON attendees that the mobile business is forecast to be double the size of the PC market in 2016. The mobile business drives many new requirements, said Manocha, including power, performance and features, higher data rates, high resolution multicore processors and thinner form factors.

This incredible growth is driving new dynamics, said Manocha, and pushing the industry to the new technology node each year, which is presenting the industry with what Manocha deems the Big Five Challenges. Manocha believes these challenges are: cost, device architectures, lithography and EUV, packaging and the 450mm wafer transition.

Cost, said Manocha, continues to be the underlying challenge of the entire industy, because, without focusing on wafer cost, even in good times, a company can enter into what he called “profitless prosperity.” Unfortunately, with the introduction of a new technology node each year, advanced technology costs are rapidly rising.

“Fab cost alone escalates 40 percent year after year,” said Manocha.

To keep wafer costs down, what Manocha believes the industry needs for success is a new foundry model altogether. His model, which he calls Foundry 2.0, hinges on industry collaboration rather than wafer price competition. By encouraging the industry to work together on products and meet the same goals, the industry can see a faster rate of change and tap into global R&D talent.

“The best solutions rarely originate from an insultated team,” he said. “It’s critical that we understand what customers need.”

SEMI recognizes GLOBALFOUNDRIES CEO

Click here for more news from SEMICON West or be sure to follow us on Twitter.

What do you think? Tell us in the comment section below.

SEMI today announced the results of its annual Board of Directors elections. Bertrand Loy, president and CEO of Entegris, Kyu Dong Sung, CEO of EO Technics, and Xinchao Wang, chairman of JCET, were elected as new directors to the SEMI International Board of Directors. The re-election of existing board members was announced, in addition to new leadership appointments. André-Jacques Auberton-Hervé, chairman, CEO and president of Soitec Group, will serve as SEMI chairman and Yong Han Lee, chairman of Wonik, as SEMI vice-chairman.

Auberton-Hervé succeeds Doug Neugold, chairman, CEO and president of ATMI, who served as SEMI chairman for the last two years. The leadership appointments and elected board members’ tenure becomes effective at the annual SEMI membership meeting, to be held Wednesday, July 10, during the SEMICON West 2013 and Intersolar North America expositions in San Francisco, California.

“Our industry congratulates the newly-elected members of the SEMI International Board of Directors,” said Denny McGuirk, president and CEO of SEMI. “We also very much appreciate the continued service of re-elected members and board leadership.”

In accordance with the association’s by-laws, the following five board members were re-elected for a two-year term:  André-Jacques Auberton-Hervé, chairman, CEO and president, Soitec Group;  David B. Miller, president, DuPont Electronics and Communications; Michael R. Splinter, chairman and CEO, Applied Materials Inc.; Ho-Ming Tong, general manager and chief R&D officer, group R&D, ASE Group;  and Kazuo Ushida, managing director, senior executive officer and president of Precision Equipment Co., Nikon Corporation.

SEMI’s 21 voting directors and 11 emeritus directors represent companies from Europe, China, Japan, Korea, North America, and Taiwan, reflecting the global scope of the association’s activities. SEMI directors are elected by the general membership as voting members of the board and can serve a total of four two-year terms.

SEMI forecasts semiconductor equipment sales will reach $43.98 billion in 2014, a 21 percent increase over estimated 2013 equipment spending, according to the mid-year edition of the SEMI Capital Equipment Forecast, released here today at the annual SEMICON West exposition.

Following two years of conservative capital investments by major chip manufacturers, semiconductor equipment spending is forecast to grow to $43.98 billion in 2014, up from $36.29 billion projected this year.  Key drivers for equipment spending are significant NAND Flash fab investments by Samsung in China and Toshiba/Sandisk in Japan, and investments by Intel, including its fabs in Ireland.  Most major regions of the world will see significant equipment spending increases.  Front-end wafer processing equipment will grow 24 percent in 2014 to $35.59 billion, up from $28.70 billion in 2013.  Test equipment and assembly and packaging equipment will also experience growth next year, rising to $3.18 billion (+6 percent) and $2.9 billion (+14 percent), respectively. The forecast indicates that next year will be the second largest spending year ever, surpassed only by $47.7 billion spent in 2000.

"Continued strong demand by consumers for smart phones and tablet computers is driving chip manufacturers to expand capacity for memory, logic and wireless devices,” said Denny McGuirk, president and CEO of SEMI. “To meet the pent-up demand for capacity, particularly for leading-edge devices, we expect capital spending to increase throughout the remainder of this year and continue through 2014 — to post one of the highest rates of global investment for semiconductor manufacturing ever.”

Growth is forecast in China (82 percent), Europe (79 percent), South Korea (31 percent), Japan (21 percent), North America (9 percent), and Taiwan (2 percent). Taiwan will continue to be the world’s largest spender with $10.62 billion estimated for 2014, followed by North America at $8.75 billion and Korea with $8.74 billion. The following results are given in terms of market size in billions of U.S. dollars and percentage growth over the prior year:

 

 

 

 

 

By Equipment Type

 

 

yr-over-yr

 

yr-over-yr

 

2012

2013F

%Chg

2014F

%Chg

Wafer Processing

28.15

28.70

1.9

35.59

24.0

Test

3.55

3.00

-15.5

3.18

6.0

Assembly & Packaging

3.08

2.55

-17.2

2.90

13.7

Other

2.15

2.04

-5.1

2.32

13.7

Total Equipment

36.93

36.29

-1.7

43.98

21.2

 

 

 

 

 

 

By Region

 

 

yr-over-yr

 

yr-over-yr

 

2012

2013F

%Chg

2014F

%Chg

Korea

8.67

6.69

-22.8

8.74

30.6

Taiwan

9.53

10.43

9.4

10.62

1.8

North America

8.15

8.04

-1.3

8.75

8.8

Japan

3.42

3.80

11.1

4.61

21.3

Europe

2.55

2.35

-7.8

4.21

79.1

China

2.50

2.81

12.4

5.11

81.9

Rest of World

2.10

2.17

3.3

1.94

-10.5

Total Equipment

36.93

36.29

-1.7

43.98

21.2

* Totals may not add due to rounding

 

 

 

 

Source: Equipment Market Data Subscription (EMDS), SEMI

 

CEA-Leti said today that its multi-partner programs, IDEAL and IMAGINE, have demonstrated cost-effective solutions that extend 193nm immersion lithography for 1X nodes for critical levels such as contact and via, and for the cut layer, when multi-patterning is used.

Leti and Arkema launched the IDEAL program in 2011 to develop lithography techniques based on nanostructured polymers, using 300mm directed self-assembly (DSA) process and material solutions for 1X nodes. The partners, which include Sokudo, Tokyo Electron, STMicroelectronics and advanced academic laboratories, such as LTM and LCPO, have demonstrated DSA resolution capability down to sub-10nm half-pitch.

“IDEAL is addressing the limits of conventional optical lithography with a technological solution that offers potential cost-reduction opportunities,” said Serge Tedesco, Leti’s lithography program manager. Self-assembly lithography with block copolymer is a highly promising complementary technology due to its low manufacturing costs and its straightforward integration in existing device-manufacturing processes.”

The collaboration also recently completed DSA process integration in Leti’s 300mm pilot line and new specific modules have been implemented in the 300mm Sokudo DUO Track for coating, baking and PMMA removal, one of the key steps in DSA process implementation.

IMAGINE, a multiple electron-beam-lithography R&D program with a dozen partners, is focused on developing maskless lithography (ML2) based on MAPPER Lithography tools for high throughput.

The IMAGINE program this year will interface a 1,300-electron-beam tool (Matrix platform) with the Sokudo 300mm DUO Track, targeting a throughput of one wafer per hour. That will be followed by a 13,000-beam system producing a throughput of 10 wafers per hour in early 2015. The longer-term goal is a cluster of 10 modules allowing a throughput of 100 wph to support 1Xnm logic-nodes production.

Launched as a three-year project in 2009, IMAGINE was extended for four years in 2012. Besides Leti and MAPPER, the program also includes TSMC, STMicroelectronics, Nissan Chemical, TOK, Dow, JSR Micro, Sokudo, TEL, Mentor Graphics and Aselta Nanographics.

“These concrete results clearly show the industry that DSA and ML2 can extend 193nm immersion lithography by providing cost-effective solutions for critical-layer patterning,” Tedesco said. “They also demonstrate the value of combining the broad and deep technological strengths of Leti, MAPPER, Arkema, and all our partners in programs focused on meeting the demands at 1X nodes.”

 

At SEMICON West 2013, Element Six today announced it has expanded its global manufacturing capabilities of microwave chemical vapor deposition (CVD) synthetic diamond by 60 percent compared to last year. Driven by growth in the company’s semiconductor and optical business segments, Element Six has effectively ramped production capacity to meet emerging demand for thermal management solutions including gallium nitride (GaN)-on-diamond substrates and high-power resistant optical windows for Extreme Ultraviolet (EUV) lithography systems.

“Our bookings have seen a 30 percent increase in compound annual growth over the last two years, and we attribute the majority of our expansion to new applications in the semiconductor market,” said Adrian Wilson, head of the technologies division at Element Six. “We are seeing more interest from packaging designers and manufacturers as the industry comes to recognize the numerous properties and benefits of synthetic diamond, which offer our customers a distinct competitive advantage to further differentiate and strengthen their solutions for a greater return on investment.”

Element Six has expanded its high-volume manufacturing capabilities across its facilities in Silicon Valley, California, and Ascot, United Kingdom—the latter already serving as the world’s largest CVD diamond manufacturing site. The three key areas of production supported at the built-out sites include:

  • CVD diamond thermal material—delivering thermal conductivity between 1000 to 2000 W/mK, synthetic diamond is integrated into semiconductor modules to serve as an effective heat spreader—driving to more than a 20 degree temperature decrease to quadruple a device’s lifetime.
  • Synthetic diamond optical windows—an enabler for Laser Produced Plasma (LPP) EUV lithography system, Element Six’s large CVD synthetic diamond optical windows (71-80mm in diameter) withstand the power levels necessary to produce EUV light—reducing system downtime and improving wafer throughput.
  • GaN-on-diamond wafers—one of the world’s most thermally conductive materials, GaN on free standing polycrystalline CVD diamond is up to five times more conductive than copper at room temperature—enabling rapid, efficient and cost-effective heat extraction that lowers operating temperature and overall system level costs, and increases the power of RF devices. GaN-on-diamond technology earned a Compound Semiconductor Industry Award for its ability to achieve up to a three-fold improvement in heat dissipation, while preserving RF functionality.

To further consolidate and strengthen the company’s innovation capabilities, Element Six also opened its new Global Innovation Centre (GIC), based in Harwell, near Oxford, this month. Building on Element Six’s 50 years of R&D heritage, the GIC will enable the company to rapidly design, manufacture and test market-ready solutions in one location.

For those interested in learning more about synthetic diamond’s diverse properties, semiconductor applications, and the company’s research and development efforts, please visit Element Six’s booth #5750 at SEMICON West.

 

Dow Corning announced Monday that it is among the newest member organizations to join imec, a leading research center for the advancement of nano-electronics. The announcement signals expanded opportunities for both organizations to combine their expertise toward the development and broader adoption of 3D integrated circuit (IC) packaging technologies, wherein IC chips are stacked in vertical 3D architectures.

“This move is a natural and strategic step for Dow Corning and imec, as we both believe collaborative innovation is as critical to industry leadership as native expertise,” said Andrew Ho, global industry director, Advanced Semiconductor Materials at Dow Corning. “Our access to imec’s world-class resources and expertise will not only help us further refine our unique temporary bonding solution, it will allow imec to leverage that solution to advance integration of the 3D IC packaging process that they’ve been developing for years.”

Yet, before 3D IC fabrication can see broader adoption, it will require innovative advances in materials and processing technologies.

One of the key challenges imec is tackling is the bonding of the device wafer to a carrier wafer, prior to wafer thinning, and the safe debonding of the thin wafer after completion of backside processing. This was Dow Corning’s goal when designing its Temporary Bonding Solution, aims at simple processing using a bi-layer concept comprising an adhesive and release layer. The technology also enables room-temperature bonding and debonding processes based on standard manufacturing methods.

Together with imec, Dow Corning will explore its temporary bonding CMOS-compatible solution for 3D Through-Silicon-Via (TSV) semiconductor packaging. The collaboration will aim to further expand the technology’s ability to achieve simple, cost-effective bonding-debonding techniques compatible with standard manufacturing processes.

“Imec’s precompetitive programs are an essential platform for industry leaders to share the risk and cost of advanced research. As one of the semiconductor industry’s most proven pioneers in advanced silicone-based solutions, Dow Corning brings valuable materials and processing expertise to imec’s global network of innovators – as well as a key enabling technology for TSV fabrication,” said Eric Beyne, program director 3D System Integration at imec. “We look forward to collaborating closely with our newest member organization as we drive the next stage of 3D integration, and help ensure compatiblity of the proposed thin wafer carrier solution with advanced, sub-10-nanometer CMOS device technologies.”

Imec exhibits at SEMICON West, July 9-11, 2013 at booth 1741, South hall.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has achieved strong revenue growth and expanded its headcount for the first half of 2013.  The company attributes this success to continuing demand for its flexible process solutions designed to address high-volume manufacturing (HVM) needs across multiple markets–including 3D-ICs, MEMS, power devices and compound semiconductors.  EVG’s latest technology innovations that address these and other markets will be showcased this week at SEMICON West 2013 at the Moscone Convention Center in San Francisco.  In addition to unveiling a series of new solutions, EVG also reports that it continues to expand its wafer processing services and process development consultation capabilities worldwide as part of the company’s long-term growth strategy. 

"2013 has been a strong year for EV Group as we continue to invest in new technologies and capabilities to support our customers’ ability to ramp next-generation devices to volume production quickly and cost-effectively at high yields," said Dave Kirsch, vice president and general manager of EV Group North America.  "This requires not only leading-edge process equipment but also world-class global support and process development services. EVG’s local teams work hand in hand with our corporate headquarters to provide increased flexibility and capability for our customers.  That includes our ability to offer small-scale and pilot-production services at our global applications labs, which is a key differentiator for us and a key value proposition for customers."

Expanding sales growth and global customer support operations

During the first half of 2013, EVG achieved approximately 10 percent growth in sales and more than 10 percent increase in employees. To support its customers’ roadmaps, EVG continues to invest aggressively in research and development–approximately 20 percent of sales–in several key efforts, including 450-mm tool development. Among these efforts, EVG has invested in new state-of-the art cleanrooms and application labs with in-house process demo capability on fully automated systems at its corporate headquarters in Austria, as well as its regional headquarters in Japan and North America. 

VLSIresearch recently recognized EVG’s customer service and support, ranking it at one of the 10 Best Focused Suppliers in Chip Making Equipment. EVG was also ranked in first place in the "Other Silicon Wafer Fab Equipment" category for the company’s wafer bonding solutions. 

Leadership in wafer bonding

Already a leading supplier of HVM wafer bonding solutions, EVG recently unveiled several new platform developments in both fusion bonding and temporary bonding/debonding applications.  Yesterday, EVG unveiled the latest version of its EVG 40NT automated measurement system, which features improved specifications to achieve the highest wafer-to-wafer alignment accuracies needed for the production of next-generation 3-D integrated image sensors and stacked memory devices.  The EVG40NT is seamlessly integrated with EVG’s GEMINI FB automated production fusion bonding system to enable a closed-loop control system that facilitates customers’ ramp to volume production across multiple markets and applications.  Last week, EVG also introduced its LowTemp debonding platform, which features three high-volume-production room-temperature debonding process types and is supported by a supply chain of seven qualified adhesive suppliers to enable greater manufacturing flexibility.

Expertise in lithography and resist processing

Building upon the company’s expertise in lithography, EVG also recently unveiled the EVG120 automated resist processing system, which integrates spin/spray coating and wet processing to provide a highly flexible system that maximizes productivity and cost of ownership.  The EVG120 is ideally suited for a wide variety of markets and applications, including high-topography coating and spray coating for MEMS, thick-film resists and bumping for advanced packaging.  It is also suited for passivation, dielectrics and thick-film processing for compound semiconductor devices.

Rounding out EVG’s latest developments in wafer surface preparation, the company also recently announced the CoatsClean wafer cleaning solution, which combines process, equipment and formulation technology to deliver an innovative, low-cost-of-ownership approach to single-wafer photoresist and residue removal.  Co-developed with Dynaloy, CoatsClean is designed to address thick films and difficult-to-remove material layers for the 3D-IC/through-silicon via (TSV), advanced packaging, MEMS and compound semiconductor markets.

Presentations at SEMICON West 2013

Attendees interested in learning more about the company and its latest developments are invited to visit EVG’s booth #819 in the Moscone South Hall at SEMICON West as well as attend the company’s presentations during the show’s technical program.  Markus Wimplinger, corporate technology development and IP director of EVG, will present "High Resolution In-line Metrology Module for High-Volume Temporary Bonding Applications at the SEMATECH Workshop on 3D Interconnect Metrology on Wednesday, July 10 from 11:20 – 11:40 a.m. at the Marriott Marquis in San Francisco. In addition, Dr. Thorsten Matthias, business development director at EV Group, will present "From Sensor Fusion to System Fusion" at the TechXPOT session "MEMS and Sensor Packaging for the Internet of Things" on Thursday, July 11 from 12:10 – 12:30 p.m. in the Moscone North Hall.