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Executive Overview
The opportunities that nanotechnology presents to our industry are many, and a short article cannot come close to covering the breadth implied by this title! However, following a general introductory discussion, a few selected examples will help build an understanding of basic concepts behind some of the latest nanoelectronics research efforts. Most of the examples are taken from university research on potential "beyond-CMOS" device technologies funded by an industry-government partnership. References to more detailed publications on these projects are included to serve as a "pointer to the literature" on some of today’s most significant nanodevice research.
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Robert Doering, Texas Instruments, Dallas, Texas, USA
In common usage, "nanotechnology" refers to structures (i.e., devices) and materials (and processes to fabricate them) that exhibit useful properties resulting from sub-100nm features. Note, however, that a somewhat vague restriction to "qualitatively new" is also usually included. For example, 90nm (or even 30nm) gate-length MOSFETs are not considered "nanotechnology" in many circles.
This point is even better illustrated via an informal poll of materials scientists and chemists at a meeting a few years ago, which indicated substantial agreement that nylon would be called a "nanotechnology" material if it had been invented "last week" rather than in 1935! Of course, this is just one of many examples from chemical synthesis illustrating the difficulty in creating a simple definition of "nanotechnology."
The current common usage of "nanotechnology" also usually implies something revolutionary rather than evolutionary. With respect to semiconductor product manufacturing, this criterion generally encourages focus on examples that are typically a decade or more from potential implementation.
Volume manufacturing
In the relatively near term, it appears that most of the opportunities for nanotechnologies in volume manufacturing involve nanomaterials as replacements for traditional materials. Note that the distinction between "nanomaterials/particles" and "conventional materials/particles" is often characterized, not just by structure size, but also by the degree to which they are "engineered" for specific combinations of properties.
In current research, the "hot topic" nanomaterial for potential electronic applications is graphene, the subject of the 2010 Nobel Prize in Physics. Graphene is a single atomic layer of graphite (an allotrope of carbon), in various shapes (e.g., "nanoribbons") and orientations. Graphene has amazing properties, in part, stemming from a band structure that exhibits linear, rather than the usual quadratic, dependence of energy on momentum (i.e., like a "relativistic" particle). Its potential uses include ultracapacitors [2], transparent conductive electrodes for PV (replacement for expensive indium tin oxide) [3, 4], various forms of transistors, and many more. Although cost reduction would be the major benefit of using a nanomaterial in some cases, enhancement of material properties is generally the primary objective. Another electronics-industry example of the latter is improving the electrical and thermal conductivity of bonding materials, such as in packaging applications [5].
As we move to the "device level," there are often a greater number of nano-material/structure properties that must be simultaneously optimized, and, of course, the device manufacturing is typically more sensitive to contamination. However, as for packaging, the most straight-forward device opportunities for the introduction of nanotechnology are also in the form of materials replacements or additives. A long-pursued example is the use of nanoparticles in nonvolatile memory [6]. There are many others, but the remainder of this article is devoted to highlighting a few of the potential device nanotechnologies that are currently being explored as possible alternatives to CMOS transistors in future semiconductor manufacturing.
History of nanoelectronics development
In 2003, the Semiconductor Industry Association (SIA) formed a Nanoelectronics Working Group, which recommended that industry and government partner to sponsor increased university research in two related areas: (1) novel nanodevices targeted at density, power efficiency, and speed beyond estimated ultimate limits for scaled CMOS, and (2) a novel form of nanomanufacturing that would allow the industry to dramatically depart from the increasing capital and operating cost trends that are so familiar in the traditional "deposit/pattern/etch" (a.k.a, thin-film "planar process") paradigm of the last half century.
These recommendations were presented both to the President’s Council of Advisors on Science and Technology (in 2003) [7] and to the SIA Board of Directors. In March of 2005, six of the SIA member companies, AMD, Freescale, IBM, Intel, Micron, and Texas Instruments, responded by forming the Nanoelectronics Research Initiative (NRI), a consortium activity that funds university research as a part of the Semiconductor Research Corporation (SRC). In 2010, the corporate members of NRI are AMD/Global Foundries, IBM, Intel, Micron, and Texas Instruments. NRI is also currently supported by the National Institute of Standards and Technology (NIST), the National Science Foundation (NSF), and several state and local governments.
Thus far, the NRI research has identified quite a few possible approaches to "beyond CMOS" devices, which are currently at various stages of theoretical and experimental evaluation. A first pass has also been made at estimating their performance against a consensus "ultimate CMOS," which is currently equated to what is popularly called "the 15nm technology node." Details of this initial comparison have been submitted for publication [8].
The remainder of this article provides very brief descriptions of just a few of the NRI device concepts currently under study and encourages interested readers to consult specific references for detailed accounts of the research completed to date.
Exploring new switching devices
The biggest challenge in replacing the basic field-effect transistor (FET) as a switch is that it is already extremely good and further scalable! As long as its materials properties can be improved and the manufacturing technology/cost is up to the feature-scaling task, the conventional FET theoretically approaches performance and energy efficiency close to physical limits imposed by the uncertainty principal, equilibrium thermodynamics, and electrodynamics, at least for devices based on individual charged-particle (e.g., electron) behavior.
The history of studying these limits goes back to Von Neumann and was well summarized by Meindl a decade ago [9]. This recognition has prompted much of the early NRI research to focus on information state variables that are alternative to "the amount of electrical charge on FET gates" employed by CMOS logic. It has also encouraged some study of non-equilibrium operation and "thermal-phonon engineering."
Despite the just-mentioned excellence of scaled/materials-enhanced FETs, NRI research indicates that several forms of tunnel FETs (TFETs) may use less power at a given speed. An enabler for such TFETs could be graphene-nanoribbon channels [10]. In fact, many of the currently-studied NRI switches are based on using graphene in some part of the nanostructure. Thus, it’s possible that "carbon nanoelectronics" may at least augment silicon CMOS at some point in the future. Of course, we are a long-way from volume manufacturing of integrated circuits with graphene. However, NRI process/materials research has already produced a promising breakthrough in CVD of large-area graphene layers [11], which could have many uses, including the manufacturing of TFETs and more-exotic devices, as well as the previously-mentioned transparent-electrode application.
Another graphene-based switch being studied in NRI is the Veselago device [12], which is designed to manipulate electron wave functions as if they were electromagnetic waves (i.e., analogously to optics). Such devices take advantage of the focusing properties of p-n junctions in graphene and have been estimated to have the potential for very high speed.
Note that the devices previously discussed all still use "quantity of electric charge" as the logic state variable. Of course, in hard-disk and some other memories, atomic-spin orientation has long been used to represent information. So far, commercial spin-based memories have all employed spin in the form of magnetic domain orientation.
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Figure 1. Magnetic force micrograph of a one-bit full adder constructed with permalloy nanomagnets. The arrows indicate the in-plane magnetic field polarity. The individual nanomagnets in the circuit are 60x90nm, with a thickness of 30nm deposited on oxidized silicon. SOURCE: Courtesy of Edit Varga, Nanomagnet Logic Group, and Alan Seabaugh and Wolfgang Porod, NRI Midwest Institute for Nanoelectronics Discovery, University of Notre Dame.
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NRI research has shown that magnetic states can also be used to perform "nanomagnet logic" (NML) [13], as demonstrated in Fig. 1. Like most of the NRI spin-based devices studied thus far, NML seems to fit best with applications requiring very low power at modest speed. NRI also conducts research on devices based on electron-spin transport [14]. In some devices, the spin-state information can be moved between logic elements without transporting any electric charge, an obvious advantage for low-power operation. A general challenge for the spin-based devices is that they do not tend to have intrinsic gain and, thus, need occasional logic-level boosts.
Exploring collective "pseudospin"
One of the most exciting approaches to alternative logic state variables is the potential exploitation of collective quantum phenomena as opposed to single-particle states. Perhaps the most exotic state variable explored thus far in the NRI program is collective "pseudospin."
Actually, several different phenomena are labeled as pseudospin in modern physics. All share the simple Pauli mathematics of two-state quantum systems originally developed for description of the "ordinary spin" (i.e., intrinsic angular momentum) of spin-1/2 particles. The form of pseudospin most studied in NRI corresponds to the discrete "which-layer?" degree of freedom for the location of an electron in a bilayer graphene system. Note that "top/bottom layer" is analogous to "up/down spin."
The really exciting aspect of this form of pseudospin is the theoretical prediction that the ground state of a suitable graphene bilayer may be an above-room-temperature Bose-Einstein condensate corresponding to a coherent superposition of excitons, each consisting of an electron on one layer and a hole on the other [15]. If this prediction is correct, such a condensate would be the first room-temperature superfluid.
A simple way of understanding why this might be possible is to recognize that the binding between electron and hole in each exciton is due to their relatively strong mutual electrostatic attraction – much stronger than the lattice-distortion attraction between the Cooper pairs of electrons in the condensate corresponding to standard superconductivity. Of course, the weakly-bound Cooper pairs "fall apart" far below room temperature.
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Figure 2. Current path in a bilayer-pseudospin field-effect transistor (BiSFET) as modulated by gate control of Bose-Einstein exciton condensate formation. SOURCE: Courtesy of Seyoung Kim, Emanuel Tutuc, and Sanjay K. Banerjee, NRI Southwest Academy of Nanoelectronics, University of Texas at Austin.
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One of the criteria for formation of the bilayer exciton condensate is optimum spacing (perhaps via an intervening dielectric) of the graphene layers. Other criteria are related to the quality of the graphene layers and their mutual alignment. An NRI logic device based on such a superfluid condensate of excitons is the bilayer pseudospin FET (BiSFET) [16], which controls the presence or absence of the condensate via applied gate voltages. BiSFET operation is schematically illustrated in Fig. 2.
Fostering collaboration
One of the strengths of NRI is the interdisciplinary collaboration that it fosters between electrical engineers, physicists, materials scientists, et al. The potential room-temperature Bose-Einstein condensate just discussed is of obvious interest to physicists and material scientists even as "merely" a new solid-state phenomenon – one which could lead to future Nobel Prizes! However, turning this phenomenon, if it exists at room temperature, into a logic building block, such as a BiSFET, also requires investigation at the circuit level, led by the electrical engineers, but still in need of broad collaboration.
For example, in communicating with each other, such devices may need sophisticated clocking schemes, which could dilute their power-delay-product advantage over ultimate CMOS if ordinary FET clocks were needed as part of a hybrid circuit. This is analogous to the aforementioned limitation of the electron-spin devices in needing periodic logic-level boosts from devices with gain (most likely conventional FETs). In fact, a general issue at the circuit level for many of the NRI devices is an efficient mechanism for rapidly transporting the logic state from device to device. Note that this might be accomplished via an "information token" (the form in which logic state is transported) that is distinct from the logic-state variable itself.
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Figure 3. Schematic view of spin wave majority-gate logic. A bit of information is encoded into the phase of the propagating spin wave (e.g., relative phases 0 and "pi" correspond to logic states 0 and 1, respectively). The phase of the output spin wave is determined by interference as the majority of phases of the input signals. SOURCE: Courtesy of Kang L. Wang, Alex Khitun, and Ming Bao, NRI Western Institute of Nanoelectronics, University of California at Los Angeles.
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One approach is to use electromagnetic waves (from RF to light) to transport electric-charge-state information from one circuit to another. However, this requires emission/detection conversion processes, which generally compromise overall power efficiency. Thus, NRI has also explored a related option in which surface plasmons rather than photons are the information tokens [17]. Surface plasmons are quasiparticles representing correlated electron-photon states, and they negotiate sharp turns more efficiently than "stand-alone" photons. Overall, the transport or "interconnect" problem is often just as large a challenge as the "switch" problem. Therefore, some of the NRI devices, such as the NML, "spinwave" [18] and Veselago devices, intrinsically integrate information transport into the basic concept. Spinwave logic is depicted in Fig. 3.
Conclusion
In summary, the NRI results to date generally offer more encouragement for surpassing the capabilities of CMOS in achieving lower-power operation (at a given speed) rather than far higher ultimate speeds [6]. At this point, the NRI program has not yet identified any single, most-promising candidate for a beyond CMOS nanotechnology. However, if we are fortunate, there may eventually be several.
References
1. M. S. Fuhrer, C. N. Lau, A. H. MacDonald, "Graphene: Materially Better Carbon," MRS Bulletin, vol. 35, pp. 289-295, April, 2010.
2. M. D. Stoller, S. Park, Y. Zhu, J. An, R. S. Ruoff , "Graphene-Based Ultracapacitors," Nano Letters, vol. 9, no. 10, pp. 3498-3502, Sept. 13, 2008.
3. M. Wilson, "Graphene Production Goes Industrial," Physics Today, vol. 63, no. 8, pp. 15-16, August, 2010.
4. S. Bae, et al., "Roll-to-roll Production of 30-inch Graphene Films for Transparent Electrodes," Nature Nanotechnology, vol. 5, pp. 574-578, June, 2010.
5. D. Wakuda, K.-S. Kim, K. Suganuma, "Ag Nanoparticle Paste Synthesis for Room Temperature Bonding," IEEE Trans. on Comp. and Packaging Tech., vol. 33, no. 2, pp. 437-442, June, 2010.
6. D. Tsoukalas, "From Silicon to Organic Nanoparticle Memory Devices," Philosophical Trans. of the Royal Society, A28, vol. 367, no. 1905, pp. 4169-4179, Oct., 2009.
7. R. Doering, "Nanotechnology Research Recommendations," public meeting of the President’s Council of Advisors on Science and Technology, Washington, D.C., Dec. 2, 2003.
8. K. Bernstein, R. Cavin, W. Porod, A. Seabaugh, J. Welser, "Device and Architecture Outlook for Beyond-CMOS Switches," to be published in Proc. of the IEEE, submitted in January, 2010.
9. J. D. Meindl, Q. Chen, J. A. Davis, "Limits on Silicon Nanoelectronics for Terascale Integration," Science 14, vol. 293. no. 5537, pp. 2044 – 2049, Sept., 2001.
10. Q. Zhang, T. Fang, H. Xing, A. Seabaugh, D. Jena, "Graphene Nanoribbon Tunnel Transistors," IEEE Electron Device Lett., vol. 29, pp. 1344-1346, 2008.
11. X. Li, W. Cai, E. Tutuc, S.K. Banerjee, L. Colombo, R. S. Ruoff, et al., "Large-Area Synthesis of High-Quality and Uniform Graphene Films on Copper Foils," Science 5, vol. 324. no. 5932, pp. 1312 – 1314, June, 2009.
12. V. V. Cheianov, V. Fal’ko, B. L. Altshuler, "The Focusing of Electron Flow and a Veselago Lens in Graphene p-n Junctions," Science 2, vol. 315. no. 5816, pp. 1252 – 1255, March, 2007.
13. M. Alam, G. H. Bernstein, J. Bokor, D. Carlton, X. S. Hu, S. Kurtz, et al., "Experimental Progress of and Prospects for Nanomagnet Logic (NML),"Technical Digest of the 2010 IEEE Symposia on VLSI Technology and Circuits, Honolulu, HI, June, 2010.
14. B. Behin-Aein, D. Datta, S. Salahuddin, S. Datta, "Proposal for an All-spin Logic Device with Built-in Memory," Nature Nanotechnology 5, pp. 266 – 270, Feb., 2010.
15. H. Min, R. Bistritzer, J.-J. Su, A. H. MacDonald, "Room-temperature Superfluidity in Graphene Bilayers," Phys. Review B, vol. 78, 121401, Sept., 2008.
16. D. Reddy, L. F. Register, E. Tutuc, S. K. Banerjee, "Bilayer PseudoSpin Field-Effect Transistor: Applications to Boolean Logic," IEEE Trans. on Electron Devices, vol. 57, no. 4, p. 755, April, 2010.
17. A. Hosseini, H. Nejati, Y. Massoud, "Design of a Maximally Flat Optical Low-pass Filter Using Plasmonic Nanostrip Waveguides," Optics Express, vol. 15, no. 23, 1528112, Nov., 2007.
18. A. Khitun, M. Bao, Y. Wu, J.-Y. Kim, A. Hong, A. P. Jacob, et al., "Logic Devices with Spin Wave Buses – an Approach to Scalable Magneto-Electric Circuitry," MRS Symp. Proc., vol. 1067, B01-04, 2008.
Biography
Robert Doering is a Sr. Fellow and Research Strategy Manager at Texas Instruments, P.O. Box 650311, MS 367, Dallas, Texas 75265; ph.: 972-995-2405; email: [email protected].
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