Category Archives: LEDs

(November 1, 2010 – BUSINESS WIRE) — The IEEE Standards Association (IEEE-SA) signed four new Memorandums of Understanding (MOUs) with standards organizations in Korea, Japan and the Middle East. The agreements establish that the IEEE and the organizations will share knowledge of each group’s standards development activities, facilitate technical cooperation, and seek opportunities for future collaboration or cooperation.

The first agreement between IEEE-SA and the Telecommunications Technology Association (TTA), located in Seongnam-city, Korea, was signed earlier this year and a signing ceremony was held on 19 July. TTA focuses on standards development in the information and communication technologies sectors. South Korea’s exports, led by chips, are expected to increase nearly 24% in Q3 2010.

Another agreement, signed on 20 July, is with the Korea Electronics Association (KEA), located in Seoul, Korea. A non-profit institution, the KEA represents approximately 1,000 Korean electronics companies, and has been developing standards in Korea since 1993.

An agreement between IEEE-SA and the Telecommunications Technology Committee (TTC) was signed on 23 July 2010 in Tokyo, Japan. TTC is a non-profit standards development organization focused on information and communication technologies.

The fourth agreement, between IEEE-SA and the Arab Information and Communication Technologies Organization (AICTO), was signed on 7 July, following a visit of IEEE-SA leadership to Tunis, Tunisia, earlier this year. AICTO is an Arab governmental organization working under the aegis of the league of Arab States, and is focused on developing ICT standards in the Arab region, covering the Middle East and North Africa.

All four agreements are in effect for two years. "These new relationships, and the cooperation between IEEE-SA and these four organizations, will help local technologists to broaden their standards-based activities in Japan, Korea and the Middle East," said Judith Gorman, Managing Director, IEEE Standards Association. "This is an excellent opportunity to expand the usage of IEEE standards in these countries and to improve opportunities for companies to build and market interoperable products and services that can compete in the global marketplace."

The IEEE Standards Association, a globally recognized standards-setting body within the IEEE, develops consensus standards through an open process that engages industry and brings together a broad stakeholder community. For information on the IEEE-SA, see: http://standards.ieee.org.

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(November 1, 2010 – BUSINESS WIRE) — To increase the performance and service life of light emitting diodes (LEDs) and LED assemblies, Momentive Performance Materials has introduced a new line of thermally conductive silicones to be considered for use in LED manufacturing and assembly. Available as the TIA series of curable thermal gels and adhesives and TIS series of curable thermal compounds, the new products may help LED lighting manufacturers solve the ongoing challenges of heat transfer and dissipation in LED lighting assemblies.

Momentive’s TIA thermal gels are liquid-dispensed materials for heat dissipation, available in a variety of thermal conductivity levels, viscosities and curing profiles to meet a wide range of design needs. The new gels, which include TIA221G and TIA216G, may extend the service life of LED light bulbs by helping manage the heat generated by drivers used to regulate voltage. Since drivers are 3D and typically housed inside a light bulb fixture, a liquid-dispensed thermal material that can conform to the assembly’s design and flow into the cavity, creating a heat path from the driver to the fixture, is generally required. The TIA series can fill gaps between the driver and surrounding fixture and cure at room temperature or by accelerated heat cure to create a soft elastomer. This creates a thermal path while providing the added benefit of absorbing thermal stress due to its softness.

For designs requiring mechanical adhesion, the TIA thermal adhesives, which include the TIA250R and TIA600R products, are available in room-temperature and heat-accelerated cure formulations that adhere well to various substrates. Thermal adhesive TIA0220, for example, offers corrosion-free adhesion to most metals (including copper), plastics, ceramics, glass and other surfaces without the use of primers.

The TIS series of thermal compounds, which includes TIS380C, cures at room temperature and can be considered for use in minimizing thermal resistance in LED lighting assemblies. As soft thermal interface materials (TIMs), these thermally conductive compounds can help provide stress relief for delicate components as well as extremely low oil bleed and volatile contents, attributes that contribute to stability in high-temperature environments.

Momentive’s TIA thermal gels, adhesives and compounds can be considered for use to create a thermal path between the LED board and heatsink, which helps protect the LED from heat emission. The TIA products are all liquid-dispensed, allowing for an exact amount of material to be applied to precise locations and assembled to create a thin bond line. This contributes to overall efficiency in heat transfer. The new products are available in thermal conductivities ranging from 1 ? 6 Watt/m.K, and depending on the grade, they can be applied by dispensing or screen/stencil printing.

Momentive Performance Materials Inc. provides silicones and advanced materials. Momentive Performance Materials Holdings LLC is the ultimate parent company of Momentive Performance Materials Inc. and Momentive Specialty Chemicals Inc. (collectively, the "new Momentive"). Additional information is available at www.momentive.com.

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Executive Overview

New materials complicate the process integration in high-volume manufacturing of high-k metal-gate (HKMG) CMOS transistors. The gate-last HKMG process requires two new CMP processes, both requiring extreme control over final gate height and topography. Because the gate stack is at the heart of the active device, it is far more sensitive to dimensions compared to passive interconnect and isolation structures. The poly-open CMP process has been tuned to handle new selectivity challenges. A new family of aluminum CMP slurries has been developed to provide <10nm dishing regardless of the layout. The methodical tuning of slurry additives provides for the successful integration of both poly-open and Al CMP into HKMG process flows.

Paul Feeney, CMP Fellow, Cabot Microelectronics Corp., Aurora, Illinois, USA

For over twenty years of IC manufacturing, the creation of planar device structures has required the use of technologies to reduce topographic variation. Chemical-mechanical planarization (CMP)—pressing wafers into rotating pads in the presence of special slurry blends to produce removal through chemically amplified nano-scale abrasion— has become a critical part of modern IC fabrication.

The initial application of CMP technology was to planarize silica dielectrics for interconnects. This early use of CMP was driven by the need for basic planarity. It reduced the depth-of-focus requirement for the microlithography used to pattern the dielectric and metal layers. However, in part due to the empirical nature of original CMP process development, the technology had historically suffered from poor process control. A technology ecosystem of users, OEM’s, specialty materials suppliers, and academics recognized the challenge and worked together to ensure that CMP can meet the evolving needs of the state-of-the-art in IC fabrication. This led to the adoption of CMP for a wider variety of uses.

The first metal CMP application in manufacturing was for tungsten (W) plug formation prior to the 0.35µm node. CMP processes for polysilicon (poly), shallow trench isolation (STI), and copper (Cu) were developed and deployed to solve problems in the quest for continued scaling. Also, as the requirements for CMP have become more difficult, it is now typical for the overall material removal in a CMP process to be broken into multiple specialized steps, often with unique consumables.

Scaling and planarization of materials

CMOS scaling has led to transistor devices with critical structures approaching a few atoms in size. New materials and new structures of existing materials have been found to optimize device size and performance.

Figure 1. Starting from the 0.25µm node, about four new CMP steps have been added with each new CMOS technology generation.

Many of these changes in IC device structures and materials have driven new planarization requirements. Figure 1 shows that since the era of 1 micron minimum features, a net average of four CMP steps have been, or are being added, with each new CMOS manufacturing technology node [1].

The replacement of traditional materials for the gate dielectric and gate conductor has recently been a major focus for our industry. Traditional CMOS transistors are made with silicon-oxide/nitride (SiON) gate dielectrics and polysilicon gate conductors. The dielectric begins to suffer worse leakage as the dielectric thickness gets into the single-digit range of atoms. More exotic dielectrics are needed to resist leakage while managing other fundamental device parameters.

High-k metal-gate (HKMG) transistors were first implemented with 45nm technology. The dielectrics are based on oxides of hafnium, which can maintain low electrical leakage levels. The polysilicon conductors also need to be replaced because they do not work well with the new dielectrics. The NMOS and PMOS transistors require independently optimized complex stacks of thin work-function metals topped by a bulk conductor layer.

There are different flows under development for 32nm node processing, depending upon whether the metal-gate is formed before or after the source and drain regions. The source and drain formation includes high-temperature steps such as implants and anneals, so forming the gate first restricts the choices of conductors that can be successfully integrated. In contrast, forming the gate last—also known as the replacement metal gate (RMG) process flow—allows for the use of aluminum (Al) as the bulk conductor and has gained momentum. There is also the possibility of a hybrid approach where NMOS transistors are formed gate-first while PMOS transistors are formed gate-last.

As the device structures have become more complex, so have the manufacturing processes needed to form them. The gate-last (RMG) HKMG process flow is initially almost identical to that used to form traditional SiON/poly gates. Only after all of the high-temperature process steps are complete are the poly gates etched out and replaced by metal. The essential flow is as follows [2]:

  1. STI, implants for wells and VT control,
  2. ALD of high-k gate dielectric and poly deposition,
  3. Lithography and gate etch,
  4. S/D extensions, spacer, Si recess and SiGe deposition,
  5. S/D formation, Ni salicidation, ILD0 deposition,
  6. Poly open CMP, poly etch,
  7. PMOS work-function metal deposition,
  8. Metal gate lithography and etch,
  9. NMOS work-function metal deposition, and
  10. Al metal gate fill and CMP.

CMP for gate-last HKMG

Since the gate is essentially at the heart of the transistor, extreme control is needed over all gate processing steps to ensure proper device function. Control is made even more challenging by the atomic-scale dimensions in advanced devices. Variation in gate height of just a few atomic layers now leads to measurable transistor performance variability [3].

Figure 2. Cross-sectional schematics of "gate-last" CMOS transistors before (left) and after (right) the "poly-open planarization" (POP) CMP process, showing that this step controls the height of the sacrificial-poly gate.

CMP is central to the above integrated gate-last process flow, being used in two challenging processes to form the active device. The new dielectric process—referred to as poly open planarization (POP) CMP —has several additional challenges compared to the oxide polish utilized for making standard devices. Figure 2 shows that the transistor structure includes a combination of oxide, nitride and polysilicon films instead of just oxide.

A preferred way to address the total removal is to first polish the oxide back to the nitride in a step that is very similar to what is done in STI CMP today. Then, a final step is used to expose the tops of the polysilicon features. The process in this final step must remove the correct amount of each film while preventing local topography from being generated due to the film differences. Compared to a traditional ILD0 CMP step, even tighter thickness control is required in order to manage the height, and thus resistivity, of the gate conductor.

After the STI-like step, the nitride will be raised versus the oxide, so it is desirable for planarization to have the nitride removal rate above the oxide rate. Typical Silica-based slurries for the planarization of oxides have nitride to oxide selectivity well below 1 and have material removal rates too high for easy control.

New ways were found to produce a moderate nitride removal rate. The nitride removal mechanism is dependent on hydrolysis of the Si3N4 to Si-OH and NH3 [4]. This reaction is pH dependent, with low pH being faster. At very low pH, silica is less anionic and is not as attracted to the nitride surface, which leads to a lower removal rate.

Figure 3. A range of blanket removal rates are possible through the use of additives to suppress poly removal and pH to accelerate oxide removal in the iDiel N3100 slurry family.

A new slurry platform, iDiel N3100, was produced. The silica particles in this slurry are uniquely charged to boost attraction to the to the dielectric. In this system, the oxide removal rate is controlled by pH (Fig.3). The oxide removal rate is affected by the presence of the nitride, so the removal rate on patterned wafers starts higher and then slows as the nitride being removed decreases. This results in the prevention of local step heights. The polysilicon removal rate is driven down by additives (Fig.3). Having a low polysilicon rate and a slowing oxide rate improves the ability of the process to stop at the desired thickness target.

RMG Al CMP

The new metal CMP process—referred to as the replacement metal gate (RMG) aluminum CMP step for this gate-last flow—also has significant challenges compared to that used for W contacts. The process must planarize Al and the complex stack of work-function metals. It also must do so while stopping well on oxide and minimizing recess, both of which contribute to the gate conductor final height.

The Novus A7100 series of slurries was designed with alumina particles that provide the ability to remove Al and the work-function metals selective to the oxide underneath. As in the polishing of other metals, oxidizers and chelators play a role in creating passivation and ion-complex formation, but the mechanisms employed are unique in this system.

There are significant ways in which Al CMP is different than other metals. In W CMP, oxides of W are formed that are softer than the bulk metal and are removed more easily. Oxidation of Al creates a surface that is harder than the bulk film. This aluminum oxide surface is critical in slowing removal after clearing the bulk film in order to minimize recess. CMP using the series slurry noted above roughly follows Preston’s Law—removal rate is a linear result of pressure and velocity—demonstrating the mechanically limited nature of removal.

This passivation and removal mechanism leads to other differences. In CMP of Cu, a technique called a soft landing—where pressure is decreased during clearing to slow removal—is a common approach for minimizing recess at the expense of process time. In the Al system, higher pressure actually improves recess.

Too much mechanical energy has, however, a unique downside here. As the nano-abrasion from the particles increases, it can overcome the kinetics of passivation. The result is abrasion of the soft bulk Al that leads to a buildup of "black debris" on the polishing pad [4]. This debris is comprised of small Al particles that remain dark in color for a short amount of time until they become fully oxidized. At the onset of black debris, removal rate and defectivity both change significantly.

Figure 4. Within-die non-uniformity (WIDNU) data from Al CMP using A7100 slurry on a D100 pad, showing good control across a wide range of feature densities (95% Cl for the mean).

The optimal Al CMP process balances rate and recess (Fig.4) versus debris and defects. Recess levels are below 10nm across a wide range of feature sizes and densities after the aluminum CMP step. This recess can be further reduced by an optional buff step that removes a very controlled amount of dielectric.

Conclusion

As CMP technology has matured, it has become a more attractive option for wafer processing. In addition, CMOS device scaling has led to a steady increase in the number of CMP steps, due to both an increase in the number of layers, as well as a need to create novel structures with exotic materials.

The advent of replacement metal gate (RMG or gate-last) HKMG process flows for 45nm node and below CMOS manufacturing has led to a significant amount of development going into the new dielectric and metal CMP steps. The needs are now being met with processes using consumables designed specifically for these steps.

Acknowledgments

Many thanks to scores of people across Cabot Microelectronics and our industry for their contributions to these technologies. Novus, iDiel, and Epic are trademarks of Cabot Microelectronics Corp.

References

1. P. Feeney, et al., "The Increasing Needs and New Solutions in CMP," ICPT 2008.

2. K. Mistry et al., "A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging, IEDM Tech. Dig., p.247 (2007).

3. J. Steigerwald, "CMP Technologies for 45nm and Beyond," ICPT 2009,

4. J. Dysard, et al., "CMP Solutions for the Integration of High-k Devices," ECS 2010.

Biography

Paul Feeney received degrees in engineering from the U. of Illinois and from Rensselaer Polytechnic Institute. He is CMP Fellow at Cabot Microelectronics Corp., 870 North Commons Drive, Aurora, IL 60504 USA; ph.: 630-375-5592; email  [email protected].

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(October 27, 2010) — The barriers and potential for voltage and density scaling of different memory devices beyond the 22nm is one of hot topics for current memory R&D. While speculation abounds about what will be the next generation of memories and their applications, CNRS, a French government-funded research organization, has 4 new concepts of memories in 2010. The organization is actively recruiting collaborators on RE-RAM, A-RAM, MS-DRAM, and MELRAM memory technologies.

RE-RAM researchers include Marie-Paule Besland and Laurent Cario from IMN (Institut des Matériaux Jean Rouxel CNRS). RE-RAM is a based on a new family of compound. Non-volatile reversible electric-pulse-induced resistive switching were indeed recently uncovered on AM4X8 (A = Ga, Ge ; M = V, Nb, Mo, Ta ; X = S, Se) single crystals at the IMN (Institut des Matériaux Jean Rouxel CNRS). In these chalcogenide compounds, 500ns voltage pulses (<10kV/cm) applied at Room temperature on a simple MIM device (Metal/AM4X8/Metal), yielding a non-volatile resistive switching between a high and a low resistance state. This effect was also demonstrated on GaV4S8 polycrystalline thin films that exhibit a reversible resistive switching at room temperature with writing/erasing times lower than 10µs and ΔR/R values higher than 25%. The resistive switching observed in the AM4X8 system corresponds neither to a phase change nor to any of the phenomena (thermal, electronic injection or ionic diffusion) proposed so far to explain the resistive switching effect in materials envisioned for RE-RAM applications. This memory based on Mott transition insulators offers Write Time (Twr) to 10µs at 1V, Access Time (Tacc) to <50ns at 0.4V and retention time > 1 year. Current density in write operation is better than the best RRAM solution (<3.103 A.cm-2).

A-RAM is a new type of capacitor-less 1T-DRAM. This memory introduces a totally novel 1T-DRAM device based on the coupling of majority and minority carriers in highly-scaled Fully Depleted SOI transistors (FD-SOI), but also compatible with bulk substrates. A-RAM is compatible with single-gate SOI, double-gate, FinFETs and multiple-gate FETs (MuFETs) and is believed a promising candidate for scaled memory applications. The team, A-RAM researchers Francisco Gamiz, Noel Rodriguez and Sorin Cristoloveanu, have developed an absolute original concept of architecture/design/operation which enables the physical separation of majority and minority carriers. Easy to control, State ‘1’ is defined by the presence of majority carriers which leads, via electrostatic coupling, to the formation of a minority carrier channel. State ’0’ corresponds to the absence of such a channel. Deep scaling compatible, the strengths of the A-RAM memory are: single-gate operation (no mandatory need for back gate biasing), high read margin (over a factor of 100) and low power consumption. In addition, A-RAM can be combined with double/multiple-gate FETs, introducing a new paradigm in DRAM technology: multiple bit memory in a single transistor. The A-RAM architecture has been developed in collaboration between the University of Granada (Spain) and the IMEP-LAHC laboratory (Grenoble, France).

MS-DRAM is an innovative memory cell based on the Meta-Stable Dip (MSD) effect. Meta-Stable DRAM was developed at the UCL and investigated in collaboration with the IMEP CNRS laboratory (INPG, France). Current CNRS researchers include Maryline Bawedin and Sorin Cristoloveanu. The MSDRAM is dedicated to multiple-gate SOI technology. MSDRAM takes advantage of the double-gate operation in fully depleted SOI. One gate is used to adjust the body potential and the other gate reads the corresponding current values in ‘0’ and ‘1’ states. The MSDRAM displays improved performances such as the retention time and Ioff current level. Furthermore, with this specific memory array configuration and operation, the programming time and voltage are competitive leading to significant reduction in power consumption. This device is aggressively scalable as demonstrated by numerical simulations down to 30nm gate length. In comparison with other memories using only one transistor, the MSDRAM exploits the full depletion and double-gate action (for enhanced scaling capability). This results in very long retention time up to 20sec at room temperature, high Ion/Ioff (103 with I1=20μA/μm and I0=10nA/μm), and low-power consumption.

The International laboratory LEMAC, part of the IEMN (UMR CNRS 8520), led by Nicolas Tiercelin, proposed a concept for a non-volatile magneto-electric memory, or MELRAM, based on the effect of an anisotropic piezoelectric stress on the magnetization of a giant magnetostrictive material embedded in a piezoelectric matrix (patent pending). Thanks to an internal biasing field, the magnetization of the magnetic element has two quasi-perpendicular equilibrium states. A positive voltage across surrounding electrodes leads for instance to a positive stress that sets the magnetization to one of the two states, and a negative voltage sets the magnetization in the other position, regardless of the previous state. For 100nm cell sizes, less than 1V is required to write the information. The writing current should be as low as in the ferroelectric memories, as well as the switching time. The readout can be made via spin-valve or GMR effects, which avoids destruction of stored information. This element could be used for RAM, non-volatile storage as well as in FPGA types components. Given the low energy consumption, this type of memory is a serious contender for 3D integration of memory cells, allowing a dramatic increase of the memory density.

The use of these emerging technologies will change chip design. Non-volatile memories such as magnetic random access memories (MRAMs) will help to overcome the drawbacks of classical programmable logic (as FPGAs) without significant speed penalties. Beyond the obvious advantage of power saving during the standby mode, it also will benefit the configuration time since there is no need to load the configuration data from an external non-volatile memory. Furthermore, during circuit operation, the magnetic tunnelling junction (MTJ) can be written, which allows a dynamic configuration and further increases the flexibility. Instant on/off power is the most important feature allowed by this kind of technology, suitable for many embedded systems from processor architecture to application specific integrated circuits (ASICs). LIRMM laboratory, under Lionel Torres, is currently working on emerging memories applications.

To become involved with any of these CNRS research projects, contact FIST SA, which is responsible for the licensing and the transfer of technologies from CNRS to the commercial sector. Learn more at www.frinnov.fr, e-mail [email protected].

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(October 27, 2010) — The packaged LED market is experiencing tremendous growth with an expected CAGR of 28.2% between 2009 and 2015. Yole Développement and EPIC, both France-based research firms, will publish their new market & technological studies dedicated to LED market and LED manufacturing technologies November 15.

The reports include "Status of the LED industry: SLI 2010, 2008 – 2020 analysis" and "LED Manufacturing Technologies: LED ManTech 2010." This comprehensive survey describes the main market metrics and manufacturing technologies implementing broad adoption of Solid State Lighting. The packaged LED market is experiencing tremendous growth with an expected CAGR of 28.2% between 2009 and 2015. In the analysts’ base scenario, revenues will reach $8.9b in 2010 and grow to $25.7b in 2015 and close to $30b in 2020.

In terms of volume, LED die surface will increase from 6.3b mm2 to 51b mm2 in 2015, a 41.6% CAGR. This will prompt substrate volumes to growth from 12.7M Two Inch Equivalent (TIE) in 2009 to 84.4M TIE in 2015, a 37.1% CAGR (smaller than the die surface increase due to significant manufacturing yield improvements). The equipment market will experiment a dramatic growth cycle with demand driving the installation of close to 1400 reactors in the 2010-2012 period.

“Anticipation of future demand and generous subsidies in China will trigger the installation of another 700-1000 reactors in the same period, leading to a short period of oversupply starting in late 2011. However, this oversupply will mostly affect the low end of the market.”, explains Tom Pearsall, EPIC.

Growth in general lighting applications will be enabled by significant technology and manufacturing efficiency improvements that will help to lower the cost per lumen of packaged LED to be reduced 10-fold between 2010 and 2020: Economies of scale, LED efficiency improvement, including at high power (droop effect), Improved phosphors, Improved packaging technologies, Significant improvements in LED epitaxy cost of ownership through yield and throughput. However, additional breathoughs are needed; Haitz’s Law is not enough. (For nearly three decades from the late 1960s to the end of the 1990s, the light output levels from packaged LED devices have roughly doubled every two years, based on observations and projections by Roland Haitz . Haitz’s Law is similar to Moore’s Law for transistor integration in ICs).

Yole Développement is a market research and strategy consulting firm analyzing emerging applications using silicon and/or micro manufacturing. Learn more at www.yole.fr

EPIC, the European Photonics Industry Consortium, with 80 voting members and over 400 associate members is Europe’s premier photonics industry association. Learn more at www.epic-assoc.com

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(October 22, 2010) — Seeking to capitalize on the fast growth of the tablet market relative to its core PC business, Intel Corp. (INTC) has come off the sidelines with a microprocessor designed specifically for iPad-type devices, according to the market research firm iSuppli Corp.

While growth will be modest during the years to come for PCs — Intel’s traditional bedrock for revenue — expansion is unstoppable in the sizzling tablet market, led by Apple Inc.’s bestselling iPad, iSuppli and other analyst findings show.

A comparison between the relatively limited growth vista for PCs versus the panoramic expansion landscape for tablet devices shows why Intel is serious about getting into the tablet game.

Global PC shipments in 2011 are forecasted to rise by 12.5% from 2010 and by 11.3% in 2012 compared to 2011. Tablets, in comparison, will surge by 197.7% in 2011 and by 57.4% in 2012.

In a market dominated by Apple and its ARM-based A4 microprocessor, Intel’s foray into tablet devices represents a realization by the chip titan that it needs to enter this space to remain competitive. Already, the tablet market is expected to heat up, with big names like Samsung Electronics, Toshiba Corp. and Dell Inc. announcing tablet devices of their own to go head-to-head with the iPad.

With Oak Trail, Intel hopes to make some much-needed headway into the tablet market, even though the microprocessor is not scheduled to begin shipping until early 2011.

First announced by Intel in June 2010 — two months after Apple launched the iPad — Oak Trail is a System On a Chip (SOC) solution designed exclusively for tablets. Based on published reports, Oak Trail will consume as much as 50% less power than previous Intel processors and will offer full high-definition video.

More important, Oak Trail will work on three operating system platforms: Android from Google, Windows 7 from Microsoft and MeeGo from Nokia. This inter-compatibility potentially expands the universe of tablet devices in which the Intel processor might be used.

Matt Wilkins, principal analyst for computer platforms at iSuppli, believes Oak Trail’s compatibility with the various operating systems stemmed out of Intel’s frustration at seeing the iPad selling millions of units—figures that any company, Intel included, would have welcomed gladly.

“Intel is smart,” Wilkins said. “The company knows perfectly well that the media tablet market is being defined right now. And if the company doesn’t become a player immediately, its prospects of getting into the market in the future will only grow dimmer."

For now, without Intel’s presence in the sector, each sale of a tablet device means a blow to the Intel processor in terms of evaporated revenue. It also could represent a missed sale in a PC that likely included an Intel-based processor.

Intel’s Atom processor revenues were down 4% sequentially in the third-quarter, which many construe as a sign of cannibalization by tablets. 

iSuppli’s market research reports help deliver vital information on the status of the entire electronics value chain. Learn more at www.isuppli.com

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(October 21, 2010) — DEK has teamed up with Irisys, infrared products supplier, to develop a robust fine-pitch isotropic conductive adhesive (ICA) interconnection process designed to drive Irisys’ latest generation of advanced infrared sensor products. The project led to the development of an optimized process for the assembly of pyroelectric thermal sensing arrays.

A leading designer and manufacturer of intelligent infrared products in the areas of thermal imaging, people counting, queue management and security solutions, Irisys has been working in partnership with DEK for more than a decade to develop an optimized fine-pitch ICA interconnection process for its range of infrared people counting products. Most recently, the company upgraded its screen printing technology to DEK’s high-speed, high accuracy Europa platform in order to meet the requirements of its latest product generation.

The project required DEK to deliver stencil support to extend Irisys’ fine-pitch process yield. In addition to printer alignment accuracy, stencil design considerations were also central to the fine pitch interconnect process optimization. Having designed and manufactured an electroformed Nickel stencil to meet the precise demands of the process, DEK then worked with Irisys to refine performance further.

Improvements included a new stencil surface texture, modifying aperture design from 200µm towards 85µm bumps to incur an increase of aperture total density in excess of 540,000 bumps per wafer. Heightening a combined complexity of controlling pitch over full array from 500 to 170µm, processes were successfully implemented to control stretch, repeatedly at micron level. Apertures were further developed towards vertical, while the team also devised smoother sidewalls to optimize ICA roll. Process optimization also involved managing common electroforming defects, such as nodules, debris, stress and stretch. The result was significantly enhanced release of the ICA.

This particular project has seen us develop a reliable 47 × 47 array assembly process based on 170µm pitch for sophisticated people-counting applications. The detailed yield engineering contributed to a stable platform for shrinking to finer pitch, Irisys’ Dr Alan Butler explained. 

DEK is a global provider of advanced materials deposition technologies and support solutions including printing equipment platforms, stencils, precision screens and mass imaging processes. For more information, visit DEK at www.dek.com.
 
Irisys was founded on the belief that advanced infrared technologies developed for military and aerospace could be applied to transform the effectiveness and viability of many everyday applications. Learn more at http://www.irisys.co.uk/

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(October 19, 2010 – BUSINESS WIRE) — Scientists at the Naval Research Laboratory (NRL) in conjunction with the Scripps Research Institute in La Jolla, CA, recently reported a detailed study of the interactions of water-soluble semiconductor quantum dots (QDs) with the electro-active neuro-transmitter dopamine. These biocompatible QD-dopamine nano-assemblies may be used as the active component for sensors that are used to detect a wide variety of target analytes ranging from sugars to peroxides.

According to NRL’s Dr. Michael Stewart, a member of the research team, "The nature of the QD-dopamine interaction has been the subject of more than 25 recent research papers that attempted to uncover and exploit the exact nature of how the QDs interact with these small electro-active chemicals during the sensing process. Until now, it remained unclear as to whether dopamine acted as an electron acceptor or as an electron donor to quench luminescence from the QD."

"The chemical state of dopamine changes from a protonated hydroquinone in acidic media to an oxidized quinone in basic environments. A series of carefully designed experiments allowed the research team to establish that only the quinone form is capable of acting as an electron acceptor resulting in quenching of the QD emission. The rate of quinone formation and hence QD quenching is directly proportional to pH and can therefore be used to detect changes in the pH of solutions. Using this nano-scale sensor, the research team was able to demonstrate pH sensing in solution and even visualize changes inside cells as cell cultures underwent drug-induced alkalosis," explained Dr. Scott Trammell. Read more about nanotechnology in the medical sciences.

The interdisciplinary group of scientists involved in this project from NRL include: Dr. Michael Stewart and Dr. Kimihiro Susumu of NRL’s Optical Sciences Division, and Dr. Igor Medintz, Dr. Scott Trammell, and Dr. James Delehanty from NRL’s Center for Bio/Molecular Science and Engineering, along with Professor Phillip Dawson and Dr. Juan B. Blanco-Canosa of the Scripps Research Institute.

This research was supported by NRL’s Nanoscience Institute and the Defense Threat Reduction Agency (DTRA), and is focused on areas tasked to the Department of Defense under the President’s National Nanotechnology Initiative. The research was published in the August 2010 issue of Nature Materials.

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by James Montgomery, news editor

October 5, 2010 – Just two months after beefing up its semiconductor sales forecast because of the sector’s "roid rage," iSuppli has put those numbers on a cooldown rep, citing concern over end-user demand vs. inventories.

Like others, the firm had bounced up its forecast from initial mid-20s to >30% growth, and its August update hiked that number to 35%. But now iSuppli SVP Dale Ford sees "a significant slowdown" in consumer demand for some electronic devices, including market bellwether PCs, even as inventories build throughout the supply chain. The end result is a slight decline (-0.3%) in semiconductor revenue growth in 4Q10, and 2H10 vs. 1H10 semiconductor revenue growth of 7.8%, down from the 10.7% in 1H10 vs. 2H09.

Global quarterly semiconductor revenue forecast. (Source: iSuppli)

In terms of hot end markets, data processing will remain tops (38.6% in 2010), led by PCs and specifically mobile PCs including tablets. Also soaring are wireless communications (30%) thanks to smart phones. Lowest-growth markets will still have some demand: wired communications (25%) and consumer electronics (26%). In terms of device technology, DRAM leads the pack with 87%. Voltage regulators, LEDs, programmable logic devices, and data converters will all exceed 43% growth on the year.

That expectation of slowing growth doesn’t mean the market has peaked and is heading down, Ford noted. Visibility is poor and uncertainty high due to unstable economic conditions and market reports, which has led to handwringing about a possible "double-dip" scenario for electronics and the overall economy. Instead, Ford sees a "soft landing in 2011" and not "the kind of dramatic downturn seen in 2009." He currently projects 5.1% growth in 2011 (vs. 7% in the previous forecast), with quarterly data points returning to more normal seasonal patterns: decline in 1Q, improvements in 2Q and a peak in 3Q.

Semiconductor revenue by application market. (Source: iSuppli)

Chinese suppliers, distro houses battle

Also keeping the market hot in 2010: China, where sales from both distributors and suppliers will surge 30% this year to $33.1B, says iSuppli’s Horse Liu, manager for China research. This market is interesting as it approaches a threshold where supplier sales will soon outweigh those from distributors.

Chinese chip distributors focused on memory, logic, and analog components in 2009, and added sensor components in industrial electronics and surveillance. Suppliers, meanwhile, focused on direct-sales in core chip markets such as microprocessors (MPU) and digital signal processors (DSP). As suppliers cement their strategies to reduce reliance on distributors — and as distributors seek to solve their own problems of component shortages, lengthening lead times, rising product costs, and complex market conditions — look for the balance to shift in favor of suppliers taking the majority of regional sales in the 2012 timeframe, Liu predicts

M&A has played a big role in company-specific growth, Liu notes, with Taiwanese distributor World Peace Group vaulting "to a dominant position" not only in China but Asia overall, helped by its March purchase of compatriot Yosun Industrial Group. It has pulled nearly even with US firm Arrow Electronics in worldwide electronic component sales ($9.75B to $9.57B), with US-based Avnet in third with $9.18B; in China, WPG is first, followed by Avnet and Arrow.

Local Chinese distributors have so far exhibited "healthy growth and excellent product resources," and this makes them attractive M&A candidates for global distributors, Liu notes. He notes Texas Instruments has tapped Beijing-based SEED Electronic Technology as its local DSP distributor.

Silicon shipments still chugging

Revenues might be a tad softer than hoped, but silicon shipments are still racing out the doors — nearly 24% growth in 2010 to 8.9B total sq. in (BSI), eventually topping 12.4 BSI by 2014.

Chipmakers hunkered down in early 2010 to undo the damage done in 2009, and although visibility is still a bit murky, they should have enough orders in hand to carry them through the holiday ramp-up (3Q10) and season (4Q10), says Len Jelinek, iSuppli director and chief analyst for semiconductor manufacturing and supply. 2011 should carry over some of that demand too, with next year’s shipments rising about 13%.

300mm wafers are still the driver of silicon shipments and will continue through 2014, and expansions will be necessary to meet demand, he says. To that end, look for continued and increased emphasis on shifting to 300mm platform manufacturing, particularly for mixed-signal and analog technology, sectors that can benefit from 300mm production tools that are deemed no longer cost-effective for leading-edge device manufacturing.

Whither 450mm? Don’t look for it anytime before 2014, Jelinek suggests; even if the technology was ready to support production volumes it likely would be cost-prohibitive. A few companies and consortia continue to mull 450mm improvements, but equipment costs continue to "loom as the final hurdle toward adoption."

 

Global forecast of total sq. in. of silicon by wafer type. (Source: iSuppli)

 

(September 29, 2010 – BUSINESS WIRE) — GEO Semiconductor Inc., provider of high-performance, programmable video and geometry pixel processor ICs for LED-backlit LCD displays and smartphone cameras (optics through sensor), raised $2 million in additional funding comprised of venture debt and equity.

Montage Capital led the venture debt portion of the funding with participation from Harris & Harris Group. The equity portion of the funding was secured from existing shareholders and management.

GEO plans to utilize the proceeds from this funding to support its multiple new design wins for applications in LED backlighting for LCD flat panel displays, smartphone cameras, video conferencing, surveillance, laser 3D TV, digital cinemas and 2D/3D projection. In addition, this financing will be used for business development activities, while also providing additional working capital as IC shipments begin to ramp.

GEO Semiconductor chairman and CEO Paul Russo welcomed the expansion capital with new investors Montage Capital and Harris & Harris Group, as well as existing financiers. "This financing will enable us to further penetrate key high volume growth opportunities that include correcting color & brightness uniformity issues in LED-backlit LCD displays as well as correcting optical anomalies and sensor pixel non-uniformity issues in smartphones," he said.

Series B funding will be used for development of next-generation eWarp geometry processing silicon in the fourth quarter of this year, Russo added.

GEO Semiconductor (GEO) provides programmable, high-performance, video and geometry pixel processor ICs for multiple markets and types of sub-pixel streams. Learn more at www.geosemi.com

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