(September 7, 2010) — The World Fab Forecast released at the end of August indicates a 133% increase in equipment spending for front-end fabs this year and about 18% growth in 2011. Worldwide installed wafer fab capacity (without Discretes) is expected to grow by 7% in 2010 and another 8% in 2011. Fab construction spending will increase by 125% in 2010 and an additional 22% in 2011. The data reveals that for both 2010 and 2011, over 150 fab projects will contribute an estimated $83 billion in spending. The projects tracked include construction projects and equipment spending for high volume, smaller capacity, MEMS, and Discrete, including LED, fabs.

Robust semiconductor equipment spending continues

Most of the current investments in construction assure additional capacity for the future. The World Fab Forecast has identified a total of 54 construction projects underway in 2010 and the result is about $4.5 billion in construction spending. About half of these projects are for LED facilities (mostly in China). In 2011, fewer but larger fabs will carry higher construction costs, about $5.5 billion. 

Spending on equipping fabs will increase by 133% in 2010 to an estimated $34 billion. This is a record growth rate, off of the historic low of 2009, where wafer fab equipment spending struggled to $16 billion, a 10-year low. Compared to 2008 spending, 2010 total equipment spending will be only 27% higher. Compared to 2007, 2010 spending will be 11% lower. The World Fab Forecast report predicts spending in 2011 to increase 18%, bringing total spending to $39B, finally surpassing 2007 spending levels.

SEMI’s World Fab Forecast also provides details of facilities beginning operations in 2010 and 2011. By the end of 2010, about 22 facilities will begin operations. Analyzed by sector, half of these are LED, six are Foundries, three are Analog and two are Logic. No new Memory fabs will begin operation in 2010. In 2011, another 28 facilities are expected to begin operations, including four Memory fabs.

More wafer fab capacity expected

Worldwide installed fab capacity (without Discretes) is expected to grow by 7% by the end of 2010 to 14.4 million 200mm equivalent wafers per month (wpm), and by another 8% in 2011 to 15.8 million wpm. The Memory sector accounts for the largest share of worldwide installed capacity, about 41% in both 2010 and 2011. Foundry capacity follows having grown their market share from 24% in 2009 to 26% in 2011.

SEMI’s World Fab Database reports continue to track individual fab projects very closely. Updates and more information on the reports can be found at www.semi.org/fabs. The SEMI World Fab Forecast report provides high-level summaries and graphs, in-depth analyses of capital expenditure, capacity, technology and products, down to the detail of each fab, and forecasts for the next 18 months by quarter.

SEMI is the global industry association serving the manufacturing supply chains for the microelectronic, display and photovoltaic industries. For more information, visit www.semi.org

For historical data, read Fab spending still a "wild ride" in 2009 by Christian Gregor Dieseldorff, SEMI
SEMI’s World Fab Forecast tracks money spent on frontend semiconductor fabs that are equipping, including R&D and pilot fabs, fab construction projects, and capacity investments per fab. Unlike the SEMI Worldwide Semiconductor Equipment Market Subscription (WWSEMS) data, the World Fab Forecast and its related Fab Database reports track any equipment needed to ramp the fab, upgrade, expand, or change its wafer size regardless if it is new equipment, used equipment, or transferred equipment, while WWSEMS tracks only new equipment.

by Michael A. Fury, Techcet Group

August 16, 2010 – The 3^rd and final half-day of the 15^th Annual Clarkson CAMP CMP Symposium progressed with a sustaining attendance that belies the significance of the content value of this meeting. It was gratifying to see a quite respectable audience size even for the final talk.

Lieve Teugels of IMEC woke us up with horrifying pictures of "fangs" — those nasty copper chemical mechanical planarization (CMP) galvanic corrosion artifacts at the copper-barrier interface. Electrochemical studies were conducted with BTA and another commercial surfactant in development, and Ta barrier with other barrier metals to come.

Srini Raghavan of the U. of Arizona showed how to use sonoluminescence to study the role of dissolved gases in megasonic cleaning, with an eye toward optimizing PCMP and other wafer cleaning. Dissolved CO₂ may function as a free radical scavenger that extends the lifetime of ozone in water.

Len Borucki described a joint effort between Araca joint with Entrepix: a slurry injector that rests on the pad, serving a dual purpose of distributing fresh slurry immediately ahead of the wafer carrier and forming a bow wave to divert the used slurry coming around on the platen to the platen edge. Slurry flow was reduced 36% while maintaining removal rate. Under optimized conditions, there is a minimal slurry bow wave at the wafer carrier as slurry flows in a thin film, reducing slurry waste.

Deepak Mahulikar of Planar Solutions talked about the requirements for ultrapure colloidal silica for Cu slurry. Chemical contaminants in the silica have been implicated in corrosion, scratching & fangs in Cu CMP. Planar is producing a colloidal silica using fumed silica as a source material.

James Kelly of IBM Research discussed the correlation of Cu plating levelers with CMP planarization results. Rather than optimizing the leveler to reduce the load on CMP, the motivation for the work was to simplify to copper plating bath in order to rely more heavily on CMP for excess Cu removal. Even though the post-CMP topography showed <10nm difference between leveler and no leveler, the difference in electrical serpentine shorts was almost 100×. Yield results could be made comparable by adding a 20sec touch-up polish to the no-leveler wafers. The conclusion, however, is that if you want to maintain a low Cu plating overburden, the leveler should not be eliminated.

Takeshi Nogami, representing IBM’s Interconnect Group at Albany Nanotech, presented work on CVD Co as a Cu barrier and the resulting CMP implications. Co is an effective barrier for Cu, but not for O₂ and H₂O. To eliminate Cu oxidation, a PVD TaN/CVD Co/PVD Cu seed scheme was evaluated. Corrosion fangs post-CMP were worse with TaN/Co than with TaN/Ta. Co is not ruled out for 22nm, but additional work is required.

David Merricks from Ferro showed work on sapphire polishing with alumina abrasive for HB-LED applications. Samsung, TSMC, UMC, Micron, and others are entering the LED foundry market to utilize 150mm and 200mm excess capacity. Sapphire single-crystal wafers can be grown and processed like Si up to 200mm. The Ferro alumina slurry replaces a diamond slurry, and delivers ~8μm/hr removal and a final 0.2nm R_a. The alumina process is true chemical-mechanical, whereas diamond is all-mechanical.

The use of combinatorial methods for developing PCMP cleaning chemistries was presented by Steve Bilodeau, reporting on joint work involving ATMI, Intermolecular and IBM (Albany). Complex chemical processes are often highly non-linear, making multivariant techniques not only more effective but essential. Key variables included pH, solvating agent, passivator, corrosion inhibitor, and surfactant at two levels each. Measured responses included data scatter, passivation layer thickness, Cu loss and slurry cleaning. Minimum corrosion inhibitor provided the best cleaning, while pH could be modulated to minimize the passivation layer thickness.

In addition to the many fine papers presented at the Clarkson CAMP CMP Symposium, there were 14 poster papers presented by the students and faculty at Clarkson. The poster titles & professor are provided here; for further information, contact the professor at Clarkson directly.

1. Effect of polishing pad on tunable removal rates of polysilicon, SiO₂ and SiN_x films (Babu).
2. CMP of black diamond films (Babu).
3. Role of ionic strength, hydroxyl ions & radicals, & abrasives on Ge CMP in H₂O₂-based slurries (Babu).
4. A high removal rate Cu slurry for TSV applications (Li, with BASF).
5. Particle agglomeration in the CMP process (Li).
6. Development of an amine-free Cu PCMP cleaner (Li).
7. Electrochemical impedance studies of surface reactions for chemically enhanced CMP of Ta using oxalic acid as a complexing agent (Roy & Babu).
8. Chemical mechanisms of CMP of Cu & Ta in tartaric acid-based slurries investigated with electrochemical techniques (Roy & Babu).
9. Study of mechanical properties of polymer pads with AFM & nanoindentation techniques (Sokolov).
10. Studies on preparation of polymer core — ceria shell particles for CMP evaluation (Partch).
11. Effects of electrostatic & capillary forces on particle detachment with surface deformation in turbulent flows (Ahmadi).
12. Particle adhesion & removal mechanisms by hydrodynamic force in CMP cleaning processes (Ahmadi & Ferro).
13. Electrochemical methods for testing Ta CMP slurries (Suni & Li).
14. Fundamental studies of Cu ECMP electrolytes (Suni & Li, with Air Liquide).

My attendance at this meeting was motivated by the fact that it was the 15^th anniversary of this symposium. Prof. Babu thought it would be nice for me to give a dinner talk on Tuesday evening about the early days of CMP, as I am the individual held most responsible for instigating the CMP programs at Clarkson. I was honored to do so — and I express my thanks to Prof. Babu and his colleagues at Clarkson for developing and sustaining a program that has grown far beyond my expectations.

I also decided to have a little fun with my time on the podium in the relaxed environment at Lake Placid, NY. The lyrics to my ode to chip development can be found online, but interested performers will have to supply their own karaoke music and stage support.

Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected].

by Michael A. Fury, Techcet Group

August 13, 2010 – Day 2 of the 15^th Annual Clarkson CAMP CMP Symposium was led by Manabu Tsujimura, corporate CTO at Ebara, who spoke on surviving the Ice age as we transition from 45nm to 20nm. While some are talking about going back to aluminum interconnects when copper reaches its electron scattering limits, Tsujimura is content to leave it marked "unknown," though he cites tungsten as one additional option. His overall message is that equipment manufacturers need their own paradigm shift for process tools if they intend to survive the upcoming node transitions.

Hiroyuki Tano from JSR Research presented some characterization work on JSR pad polymer compositions, which contain water soluble poromers that create pad "porosity on demand" as they are exposed by pad conditioning. Effective surface hardness is engineered to deliver an acceptable trade-off between planarity and defects.

Fred Sun of Cabot Microelectronics spoke about system-level optimization in CMP to concurrently maximize performance and CoO. Specific interactions between pad and conditioner were quantified against performance results, confirming that the industry’s current process is well into the regime in which 2^nd– and 3^rd-order interactions are significant. He says the demands of advanced CMP system optimization are like solving Rubik’s Cube — whereas addressing single components is more like Whack-A-Mole.

Keiichi Kimura from the Kyushu Institute of Technology described their early attempts to analyze the conditioned pad surface and material removal mechanism using FFT topography and spatial frequency analysis. Differences in spatial wavelength were observed as a function of conditioner abrasive design pattern and diamond grit diameter. This is believed to be related to slurry flow stability between the wafer and pad.

Taewook Hwang of Saint-Gobain Abrasives talked about controlling the conditioner cut rate characteristics as a function of diamond shape. A systematic correlation of pad texture with diamond shape was produced for several different kinds of pads. While IC1000 is the standard pad for such studies historically, the Cabot D100 has played a prominent role in this study and several others in this symposium.

The evolution of CMP process control led into an introduction of Applied Materials’ latest techniques designed specifically for Cu processing. Jimin Zhang described how incoming film thickness and uniformity measurements are used to compute a set of custom process conditions for each wafer. However, real time process control is still required to consistently achieve ever-tightening specs.

Bastian Noller of BASF introduced their latest approaches for dealing with CMP for through-silicon vias (TSV), as well as a new (to me) acronym: BFEOL, which means "before FEOL." (Someone needs to come up with a "final BEOL" process to complete the set — FEOL, BEOL, BFEOL, FBEOL — but I digress.) Their optimization of a TSV Cu slurry hinges on a dual crosslinking inhibitor and frangible polymer abrasive particles.

Samsung’s Jongwon Lee described the use of a sacrificial polymer layer to boost planarization efficiency of SiO₂ polishing. Photoresist is routinely used experimentally, but is too expensive to use in volume production. Their CFSP (CMP-friendly sacrificial polymer) is essentially a hardened photoresist resin without the expensive photo-active compounds.

Haedo Jeong from Pusan National U. used bare Si wafers to analyze changes in friction in process phenomena associated with CMP. This early work focused on pad conditioning and break-in, and may prove to be a useful framework for future study.

Andreas Klipp of BASF walked us through the systematic approach that was used to develop their Planapur R-P0D cleaning product for Cu PCMP. This work highlights the amount and variety of experimental data that is required to commercialize products for volume chip production. Complete removal of BTA and restoration of low-k dielectric constant are among the key design criteria that were successfully met.

Chintan Patel from Entegris spoke about their modified charge, ultra-clean PVA brushes. The essential trick is formulating the brush materials with a negative zeta potential to minimize the accumulation of particles in the brush while still effectively removing them from the wafer surface. Modified features at both ends of the brush are shown to improve the wafer edge cleaning.

Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected].