Category Archives: Packaging

Silex Microsystems, the world’s largest pure-play MEMS foundry, and BroadPak, a provider of ultra-high performance 2.5D silicon interposer and 3D integration technologies, today announced the immediate availability of their jointly developed silicon interposer solution in high-volume manufacturing. Leveraging the advanced interposer co-design methodology and system integration expertise of BroadPak with the proven interposer manufacturing capabilities of Silex, this new solution delivers a cost-effective, ultra-high performance, reliable and high-yield silicon interposer that will enable a broader market to realize the benefits of 2.5D packaging. 

 While market analyst firm Yole Dévelopement expects the market for interposers to grow by 88 percent annually through 2017, Silex and BroadPak believe their partnership can accelerate this market adoption by overcoming the cost, engineering, reliability and supply chain bottlenecks.  3D-IC designs are widely recognized as the next step towards meeting the growing performance requirements such as increased bandwidth, reduced latency, and lower power.  2.5D silicon interposers, which are double-sided die used to stack chips side-by-side, have emerged as the most effective way to accelerate the adoption of 3D-IC, but these solutions are costly and complex, which presents significant design, integration, reliability and supply chain challenges. Recognizing these bottlenecks, Silex and BroadPak believe their new 2.5D silicon interposer product solves these hurdles that have prevented many companies from participating in this space.

“This partnership is a critical step in enabling companies to benefit from silicon interposers because most companies don’t have the integration techniques and methodologies to even start a 2.5D IC design and the current solutions have been too costly and high-risk to implement,” said Peter Himes, Vice President of Marketing and Strategic Alliances for Silex Microsystems.  “The combined Silex/BroadPak solution opens up this market to a very large portion of customers that have been unable to compete in this space due to overwhelming cost, engineering and integration challenges.”

“BroadPak and Silex have created a technical solution and the supply chain infrastructure that the industry has been waiting for,” said Farhang Yazdani, President and CEO of BroadPak. “To date, silicon interposer technology has been limited to a very small number of companies. We are now enabling the mass adoption of silicon interposer by lowering the cost and providing the co-design, heterogeneous integration and the required supply chain infrastructure in a complete package.”

 The Silex/Broadpak finished product consists of a robust interposer for 2.5D packaging, which has been designed and characterized for thermal-stress and signal integrity performance by BroadPak and also optimized for manufacturing by Silex. The unique challenges of 2.5D/3D-IC packaging require special engineering expertise to deliver cost effective solutions to meet the reliability, warpage and signal/power integrity requirements of the packaged components as well as an optimized and robust manufacturing process.

Cadence Design Systems, Inc. today announced an ongoing multi-year agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET technology, targeting advanced node designs for mobile, networking, servers and FPGA applications. The deep collaboration, beginning earlier in the design process than usual, will effectively address the design challenges specific to FinFETs — from design analysis through signoff — and will deliver the infrastructure necessary to enable ultra low-power, high-performance chips.

FinFETs help deliver the power, performance, and area (PPA) advantages that are needed to develop highly differentiated SoC designs at 16 nanometers and smaller process technologies. Unlike a planar FET, the FinFET employs a vertical fin-like structure protruding from the substrate with the gate wrapping around the sides and top of the fin, thereby producing transistors with low leakage currents and fast switching performance. This extended Cadence-TSMC collaboration will produce the design infrastructure that chip designers need for accurate electrical characteristics and parasitic models required for advanced FinFET designs for mobile and enterprise applications.

"The FinFET device requires greater accuracy, from analysis through signoff, and that is why TSMC is teaming with Cadence on this project," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "This collaboration will enable designers to use the new process technology with confidence earlier than ever before, allowing our mutual customers to meet their power, performance and time-to-market goals."

"Producing the design infrastructure necessary for these types of complex, groundbreaking processes requires close collaboration between foundries and EDA technology innovators," said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. "In joining with TSMC, a leader in FinFET technology, Cadence brings unique technology innovations and expertise that will provide designers with the FinFET design capabilities they need to bring high-performance, power-efficient products to market."

Solid State Technology is excited to announce that Mark Thirsk, managing partner at Linx Consulting, will be discussing the cost and technology needed to implement next-generation device technology at The ConFab 2013. Thirsk has over 20 years of experience in the chemical industry, working with a variety of materials and processes utilized in wafer fabrication.

“Planar CMOS logic and DRAM and NAND Flash memories are all facing major challenges for future scaling,” writes Thirsk, in his abstract. “This presentation will discuss the new fully depleted transistors, such as FDSOI and FinFETs that are now entering production for logic devices. New memory technologies such as MRAM, PCRAM and FeRAM are beginning to enter production for memory as well.”

Thirsk plans to review forecasts of implementation timing for the new technologies, scaling, equipment and materials requirements, and wafer costs. Additionally, he will review the cost and process complexity implications due to the delayed migration to EUV, the introduction of 450mm wafers, the migration of deposition to vapor phase processes, and novel cleaning and CMP processes.

Having been on both sides of the fence as a user and seller of materials and equipment, as well as being intimately involved with major materials manufacturers, Thirsk is well placed to bring clarity and insight into understanding markets from both a technical and commercial perspective. Previous to Linx, Mark was Senior Marketing Manager at Rohm and Haas Electronic Materials where he was responsible for strategic planning and new business development. Additionally, Mark has served in the SEMI Chemicals and Gases Manufacturers Group (CGMG) since 1999, acting as Chairman from 2001 to 2003.

For more information or to register for The ConFab 2013, visit The ConFab section of our website.

Fulfilling the promise of performance and power scaling at 16nm, ARM and Cadence today announced details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16nm FinFET manufacturing process. The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros.

The Cortex-A57 processor is ARM’s highest-performing processor to date, and is based on the new ARMv8 architecture, designed for computing, networking and mobile applications that require high performance at a low-power budget. TSMC’s 16nm FinFET technology is a significant breakthrough that enables continued scaling of process technology to feature sizes below 20nm. This test chip, developed with Cadence’s custom, digital and signoff solutions for FinFET process technology, was a collaboration that resulted in several innovations and co-optimizations between manufacturing process, design IP, and design tools.

"More than ever, success at the leading edge of innovation requires deep collaboration. When designing SoCs incorporating advanced processors, like the Cortex-A57, and optimizing the implementation using physical IP created for FinFET processes, the expertise of our partners is needed," said Tom Cronk, executive vice president and general manager, Processor Division at ARM. "Our joint innovations will enable our customers to accelerate their product development cycles and take advantage of leading-edge processes and IP."

The 16nm process using FinFET technology presented new challenges that required significant new development in the design tools. New design rules, RC extraction for 3D transistors, increased complexity of resistance models for interconnect and vias, quantized cell libraries, library characterization that supports new transistor models and double patterning across more layers are some of the challenges that have been addressed in Cadence’s custom, digital and signoff products.

"This major milestone was challenging on all fronts, requiring engineers from ARM, Cadence and TSMC to work as a unified team," said Dr. Chi-Ping Hsu, senior vice president of R&D for the Silicon Realization Group at Cadence.

University of Manchester graphene researchers have been awarded a £3.5 million (or approximately US$5 million) funding boost that could bring desalination plants, safer food packaging and enhanced disease detection closer to reality.

Funded by the Engineering and Physical Sciences Research Council (EPSRC), the research focuses on membranes that could provide solutions to worldwide problems: from stopping power stations releasing carbon dioxide into the atmosphere, to detecting the chemical signals produced by agricultural pests.

The latest research grant comes just months after The University of Manchester was awarded £2.2 million (or approximately US$3 million) to lead research into graphene batteries and supercapacitors for energy storage.

No molecules can get through a perfect sheet of graphene and when platelets of graphene are built into more complex structures, highly selective membranes can be generated.  The aim is, together with industrial partners, to produce working membranes for applications related to sustainability, energy, health, defense and food security.

Wonder material graphene was first isolated in 2004 at The University of Manchester by Professor Andre Geim and Professor Kostya Novoselov. Their work earned them the 2010 Nobel prize for Physics.

Graphene is the world’s thinnest, strongest and most conductive material, and has the potential to revolutionize a huge number of diverse applications; from smartphones and ultrafast broadband to drug delivery and computer chips.

The membrane program builds on ground-breaking research at the University. Previous research showed that graphene oxide membranes are highly permeable to water, while being completely impermeable to gases and organic liquids when dry.

These membranes will be developed for a variety of applications, such as the removal of water when making biofuels by fermentation, and as components of fuel cells.

The research is led by Professor Peter Budd, of the School of Chemistry. He said: “We have also invented a range of polymers – called Polymers of Intrinsic Microporosity (PIMs) – which form membranes that are very good for separating gases and organic liquids.

“These are of interest, for example, for removing carbon dioxide from power station flue gases, or for removing organic compounds from water.  By combining PIMs with graphene, we expect to produce membranes with even better performance under long-term conditions of use.

“We will also be looking at practical ways of using the ability of graphene to act as a perfect barrier in, for example, food packaging, and we will be building graphene into sensors for detecting human diseases and agricultural pests.”

It’s no secret that Samsung is up against Apple in many ways, in products, sales and innovation. However, even in the face of Apple’s patent infringement lawsuits, Samsung is still climbing the charts. The electronics giant sold approximately $53 billion in revenue in the last quarter of 2012, in comparison to Apple’s $36 billion in revenue, though the profit margins both companies are seeing were relatively similar. And while Bloomberg is predicting Apple will post its lowest sales increase since 2009, Samsung is reportedly poised for big growth in a number of sectors.  

Samsung grabs No. 3 foundry spot

Samsung jumped into the foundry scene in mid-2010, and quickly became one of the anticipated long-term leaders in the sector. It’s now easily the biggest IDM foundry operation, with sales nearly 10 times that of IBM, IC Insights noted in January. IC Insights’ August update projected Samsung finishing in fourth place just behind UMC, separated by about $400 million, but anticipated Samsung surpassing the Taiwan rival in 2013.

Samsung followed a sparkling 82 percent growth in 2011 by nearly doubling sales again to $4.33 billion, putting it just shy of GLOBALFOUNDRIES which grew sales a solid 31 percent last year to $4.56B. In fact IC Insights believes Samsung will challenge GLOBALFOUNDRIES for the No.2 spot before 2013 is done, leveraging its leading-edge capacity and huge capital spending budget. With dedicated IC foundry capacity reaching 150,000 300mm wafers/month by 4Q12, and an average revenue/wafer of $3000, Samsung’s IC foundry capacity could pull down $5.4B in annual sales, the analyst firm calculates.

How did Samsung get so big so fast in the foundry business? It supplied chips to nearly half of the industry’s 750 million smartphones shipped in 2012 — application processors for the 220 million of its own handsets in 2012, plus the 133 million iPhones Apple shipped.

Thanks to the Galaxy S4, Samsung has 99% of the AMOLED market

Samsung has invested a considerable amount into the AMOLED market, which is now poised for steady growth, thanks to a growing demand for high-end smartphones and tablets. According to Forbes contributor Haydn Shaughnessy, Samsung now holds 99% of the AMOLED market.

AMOLED display shipments for mobile handset applications are expected to grow to 447.7 million units in 2017, up from 195.1 million units in 2013, according to insights from the IHS iSuppli Emerging Displays Service at information and analytics provider IHS. Within the mobile handset display market, the market share for AMOLED displays is forecast to grow from 7.9% in 2013 to 15.2 percent in 2017, as presented in the figure below. AMOLED’s market share for 4-inch or larger handset displays employed in smartphones is set to increase to 24.4% in 2017, up from 23.0% in 2013.

“Because of their use in marquee products like the Galaxy S4, high-quality AMOLEDs are growing in popularity and gaining share at the expense of liquid crystal display (LCD) screens,” said Vinita Jakhanwal, director for mobile & emerging displays and technology at IHS. “These attractive AMOLEDs are part of a growing trend of large-sized, high-resolution displays used in mobile devices. With the S4 representing the first time that a full high-definition (HD) AMOLED has been used in mobile handsets, Samsung continues to raise the profile of this display technology.”

Samsung anticipates MEMS pressure sensor market boom

Samsung has been ahead of its time in its adoption of MEMS pressure sensors, anticipating the state of the market and getting a jump on the competition.

Global shipments of MEMS pressure sensors in cellphones are set to rise to 681 million units in 2016, up more than eightfold from 82 million in 2012, according to the IHS iSuppli MEMS & Sensors Service at information and analytics provider IHS. Shipments this year are expected to double to 162 million units, as presented in the attached figure, primarily due to Samsung’s usage of pressure sensors in the Galaxy S4 and other smartphone models.

“Samsung is the only major original equipment manufacturer (OEM) now using pressure sensors in all its flagship smartphone models,” said Jérémie Bouchaud, director and senior principal analyst for MEMS and sensors at IHS. “The pressure device represents just one component among a wealth of different sensors used in the S4.”

Besides Samsung, few other OEMs have been using pressure sensors in smartphones. The only other smartphone OEMs to use pressure sensors in their products are Sony Mobile in a couple of models in 2012, and a few Chinese vendors, like Xiaomi.

Apple, which pioneered the use of MEMS sensors in smartphones, does not employ pressure sensors at the moment in the iPhone. However, IHS expects Apple will start them in 2014, which will contribute to another doubling of the market in 2014 to 325 million units.

But what about the patent infringement suit?

Six months after Samsung was ordered to pay an unprecedented $1.05 billion to Apple in the notorious patent infringement suit, Judge Lucy Koh, the federal judge presiding over two Apple v. Samsung cases in California, entered an order striking $450 million from the damages award determined by a jury in August 2012. This corresponds to 14 of the 28 Samsung products in question in the initial lawsuit. Koh disagreed with the notice date provided by Apple concerning its patents-in-suit, and, as a result, a new damages trial must be held, most likely after the appellate proceedings, which were sought by both parties.

The new trial could mean good news or bad news for Samsung. There is the possibility that the court could rule in favor of a reduction of damages to be paid. However, it is also just as likely that the court could rule Samsung owe Apple even more than the original $1.05 billion ordered in August.

Some analysts have speculated that, if the suit holds, consumers could see a jump in prices of Samsung, Google and Android devices. Only time will tell if will a price that the masses will be willing to pay. If it is, don’t expect to see Samsung slowing down any time soon.

The second Cleanzone on October 22 and 23, 2013 in Frankfurt am Main is off to a promising start with a stronger profile. Last year, the trade fair and congress made a successful debut as the new international industry meeting point for cleanroom technology. It is targeted towards all companies and sectors in which industrial production is taking place under cleanroom conditions today and tomorrow.

2013 the trade fair will therefore be focusing even more precisely on visitors coming from two important industrial sectors: “Technology & Micro-Technology,” which is targeted towards the micro-electronics, micro-system technology, semi-conductors, aerospace technology, optical and laser technology, automotive, electronics and precision engineering markets. The other main focus comprises “Life Sciences,” with the markets of pharmaceuticals, cosmetics, sterile production of food, medical research, pharmacies and biotechnology. Overlaps can be found in the areas of medical technology and packaging solutions.

"With the stronger profile we are underlining the interdisciplinary character of Cleanzone. At the same time, we directly address those industries that are relatively new to this fascinating and future-oriented cross-sectional technology,” says Johannes Schmid-Wiedersheim, Director New Events at Messe Frankfurt Exhibition.

Cleanzone in Frankfurt

Cleanzone is the new international cross-sector meeting place for cleanroom technology. It is organized by Messe Frankfurt and supported by its marketing and content partner ReinraumAkademie Leipzig. Participants from 13 countries made their way to Frankfurt for the debut in October 2012, and both the trade fair and congress earned top marks: 89 percent of visitors and 84 percent of exhibitors were “satisfied” or “very satisfied” with the event’s debut, 46 percent of visitors were from top management, and 88 percent stated that they were able to influence purchasing and procurement decisions in their companies. Both the international scope and thematic range of the trade fair and congress are to be expanded in their second year.

Nitronex, a designer and manufacturer of gallium nitride (GaN) based RF solutions for high performance applications, has named David W. Runton as its new Vice President of Engineering. Runton has almost 20 years of RF power semiconductor experience with six years in GaN specific product development, including design, assembly, qualification and packaging.

“I’m looking forward to working with the engineering team to develop many new successful GaN products. Nitronex has very compelling technology that I feel has advantages for numerous market applications,” said Runton. “I am joining Nitronex at an exciting time with a new owner, management team, and significant growth plans for the future.”

Runton most recently served as director of High Power Engineering for RFMD, where he led an engineering product release team and developed long term product strategy. He has also held engineering leadership positions at Freescale and Motorola Semiconductor.

“David is an excellent addition to our management team and I’m confident he will help us leverage our core technology in the RF power market. He has an extensive background developing LDMOS and GaN power devices and a proven track record leading engineering teams to develop new products and technologies,” said Greg Baker, President and CEO.

Runton holds both a Bachelor Degree and a Master of Science degree in Electrical Engineering from the Georgia Institute of Technology as well as a Masters in Business Administration, High Technology Program from Arizona State University.

Swiss specialty chemicals group Clariant International AG acquired the nano-silver ink technology platform developed under the trademark Bayink from Bayer Group, Germany. The transaction comprises all patents, know-how and materials related to Bayer’s nano-silver ink technology. Clariant will continue to work closely with existing customers and cooperation partners to further develop nano-silver inks and its applications.

“The acquisition will strengthen our portfolio of new materials for the electronics and energy markets,” said Christian Kohlpaintner, member of the Executive Committee.

Nano silver inks are printable on various substrates like polymers, glas, or silicon. They are applicable in a wide variety of emerging applications for printed electronics, e.g., printed circuit boards, radio frequency identification devices (RFID) or photovoltaic panels. Nano-silver inks provide excellent conductivity by spending fewer amounts of precious metal using advanced printing technologies such as ink-jet or aerosol printing.

“Nano silver inks are an important step to develop a sustainable innovation platform for functional inks in addition to our product portfolio for printing inks which will provide unique solutions to our customers using our core competencies in surfactants and formulation technology”, said Frank Küber, Head of New Business Development at Clariant.

printed electronics
Nano-silver inks allow Clariant to enter the fast growing markets for printed electronics. (Photo: istockphoto)

GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, N.Y., the company has demonstrated its first functional 20nm silicon wafers with integrated Through-Silicon Vias (TSVs). Manufactured using GLOBALFOUNDRIES’ leading-edge 20nm-LPM process technology, the TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding performance, power, and bandwidth requirements of today’s electronic devices.

TSVs are vertical vias etched in a silicon wafer that are filled with a conducting material, enabling communication between vertically stacked integrated circuits. The adoption of three-dimensional (3D) chip stacking is increasingly being viewed as an alternative to traditional technology node scaling at the transistor level. However, TSVs present a number of new challenges to semiconductor manufacturers.

GLOBALFOUNDRIES utilizes a “via-middle” approach to TSV integration, inserting the TSVs into the silicon after the wafers have completed the Front End of the Line (FEOL) flow and prior to starting the Back End of the Line (BEOL) process. This approach avoids the high temperatures of the FEOL manufacturing process, allowing the use of copper as the TSV fill material. To overcome the challenges associated with the migration of TSV technology from 28nm to 20nm, GLOBALFOUNDRIES engineers have developed a proprietary contact protection scheme. This scheme enabled the company to integrate the TSVs with minimal disruption to the 20nm-LPM platform technology, demonstrating SRAM functionality with critical device characteristics in line with those of standard 20nm-LPM silicon.

“Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality,” said David McCann, vice president of packaging R&D at GLOBALFOUNDRIES. “Our next step is to leverage Fab 8’s advanced TSV capabilities in conjunction with our OSAT partners to assemble and qualify 3D test vehicles for our open supply chain model, providing customers with the flexibility to choose their preferred back-end supply chain.”

As the fabless-foundry business model evolves to address the realities of today’s dynamic market, foundries are taking on increasing responsibility for managing the supply chain to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs. To help address these challenges, GLOBALFOUNDRIES is engaging early with partners to jointly develop solutions that will enable the next wave of innovation in the industry. This open and collaborative approach will give customers maximum choice and flexibility, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies.