Category Archives: Semicon West

July 22, 2011 — ASM International’s Bob Hollands, director of technical marketing, thermal products, discussed the challenges of making FinFET structures using both epitaxial and high-k/metal gate (HKMG) atomic layer deposition (ALD) processes, speaking with Solid State Technology during SEMICON West 2011. "With epi, the challenges on the fin itself will be getting conformal coverage," explained Hollands. Epitaxial deposition is more of a challenge with the vertical structure, "since you’re depositing on the sidewall, its majority orientation is (110), which requires reengineering of the epi process to make it successful in terms of the performance requirements." To accommodate the overall reduction in thermal budget, the company is working on new precursors that operate at lower temperatures to control the very thin layers that are needed for these structures.



Hollands explained that as the industry moves to 15nm and beyond, there will be other issues with the HK gate stack. As the layers require higher-k materials, the material will get thinner noted Hollands. "We may still be using a basic hafnium oxide material — but adding a higher-k cap layer that would be very thin — on the order of several Angstroms, instead of the 15-20? (that is used now)." The requirements on conformality will be even more critical and will drive ALD reqs, he said.

The bigger transition with the FinFET structure will be the metal gates; the work function depends on the material’s thickness. "It’s critical to get conformality around the entire fin using ALD," explained Hollands. "If you don’t get the same thickness around the fin, and fin to fin, across the device, then you will have variations in performance."    

ASM International N.V. (NASDAQ:ASMI and Euronext Exchange in Amsterdam: ASM) design and manufacture equipment and materials used to produce semiconductor devices. For more information, visit ASMI’s website at www.asm.com.

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July 21, 2011 — Steve Lerner, CEO of Alchimer, discusses the company’s latest suite of through silicon via (TSV) technologies in a podcast interview at SEMICON West 2011.

Earlier this year, Alchimer announced a new wet-deposition process, AquiVantage (see figure), that grows interconnect layers for interposer redistribution layers (RDLs) and enhances via-last backside wafer interconnects. The new process provides concurrent wet deposition of TSV and front-side isolation, barrier, and copper fill/RDL, while eliminating chemical mechanical polishing (CMP) and dry deposition steps. It also supports smaller vias with higher aspect ratios. On the backside, the process allows selective maskless growth of the on-silicon isolation layer, completely eliminating an entire expose/develop/etch/clean lithography-process cycle. Lerner discusses how the new technology reduces costs. "It’s an agnostic platform that can be transferred to existing assets rather than constructing new equipment," said Lerner.

Figure. Top part of a SEM cross-section highlighting the concurrent growth of TSV and RDL isolation and barrier, as well as the concurrent TSV Cu fill and RDL Cu seed deposition. The SEM inlens method used for this photo shows a high contrast between the polymer isolation and the metallic materials.

According to company, overall, interposer cost savings of more than 50% are achievable with the new process. The technology also accommodates thicker wafers, eliminating the need for wafer carriers and allows for highly scalloped via structures and faster etching times.

July 21, 2011 — In a podcast interview at SEMICON West 2011, Tony McKie, GM of MEMSSTAR, tackled the question of how to make micro electro mechanical systems (MEMS) truly manufacturable. "Nobody builds a MEMS manufacturing line anymore," said McKie. Instead, what people do is take a CMOS line (either an outdated one or a 6" or 8" line) and revitalize it and make it into a MEMS production line, which is fine for about 70% of the processes required for MEMS. But for the remaining 30% MEMS-specific processes, one has to integrate technologies into the rest of the line with a good level of productivity, he said.

"In the past, MEMS processes have been more R&D type [processes] and few companies have made the leap from R&D to manufacturing," noted McKie. He explained that what one ends up with is 70% well-understood equipment and processes, but the 30% remaining may result in lower productivity, less reliability, and slower throughput. The challenge for both MEMS manufacturers and their equipment suppliers is to raise the standard of performance that is expected of any silicon manufacturer, whether CMOS or MEMS. "Everyone now expects 95% uptime, a level of throughput, a level of productivity — it all comes back to [return on investment] ROI," he said. "MEMS processes need to come to the level of ROI that CMOS manufacturers have enjoyed for the last 20 years."

On the topic of standardization of MEMS processes, McKie is hopeful, but realistic. "MEMS is very IP-protected — everybody is doing their own thing and nobody wants to share what they’re doing with anyone else," said McKie. But he believes that MEMS will have to go the way of standardization just as the CMOS industry did. "As more and more MEMS devices come to market and as the quantity of MEMS that is manufactured increases, the larger MEMS manufacturers will have to be willing to share their technology."

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by Serge Tedesco and Didier Louis, CEA-Leti

July 20, 2011 – The Sokudo lithography forum, held on Wednesday (July 13) of the SEMICON West 2011 show, reflected the evolution, the challenges and the development needs that lithography has to address for the 2xnm node. Following are some of the highlights of this event:

GlobalFoundries announced it has chosen 193nm immersion lithography with double patterning for the 20 nm node. It highlighted the difficulties of controlling CD and CDU for bright field masks, and proposed the introduction of negative tone development (NTD) to provide better control.

Nikon pointed out the scalability potential of 193nm high-NA immersion scanners using a double-patterning strategy as its choice for lithography extension. Indeed, 1.35NA scanners with new overlay, focus, heat management and lens aberration improvements will be able to address sub-22nm nodes with the pitch-division strategy by using spacer deposition. EUV is still on Nikon’s roadmap for the 16nm node, even if Nikon claimed that ArFi extension is its first choice.

An alternative option explored during the forum was maskless lithography. Mapper Lithography, a company based in the Netherlands, presented a status update of its development program. Two of its platforms have been shipped and installed in industrial clean rooms at TSMC (Taiwan) and CEA-Leti (France). The work around this second platform is shared within the IMAGINE program, launched in 2009 and led by CEA-Leti. The objective is to develop a cluster of 10 modules with 15.4m2 footprint allowing 100 wafers/hour (WPH) throughput.

ASML highlighted EUV lithography tool development and progress on its second-generation NXE platform, with overlay down to 4nm already achieved. Three different EUV sources are under evaluation from Cymer, Gigaphoton, and Ushio. ASML anticipates achieving a throughput of 125 WPH with 15mJ/cm2 resist sensitivity.

XTREME Technologies built a discharge produced plasma (DPP) source from a technology developed in 1997 by Fraunhofer ILT. The source principles have been highlighted. Complete integration with the EUV scanner has been demonstrated. No data on power has been provided, however.

SEMATECH highlighted the necessity of setting up strong collaborations between consortia and industry to overcome the remaining EUV challenges.

Serge Tedesco joined CEA-Leti in Grenoble to take charge of e-Beam lithography, and consequently all advanced lithography activities. Since 2003 he has managed CEA-Leti’s lithography strategy and programs as lithography program manager. Dr. Tedesco has authored or co-authored more than 110 papers in the field of lithography and is a program committee member of the major International lithography conferences. He has been involved in numerous European projects, both as project leader and expert.

Since joining CEA-Leti in 1985, Didier Louis has held a variety of positions in microelectronics research. In 2000, he served as the manager of the etching and stripping R&D laboratory, and from 2004 through 2007, he was deputy manager of the organization’s back-end-of-line (BEOL) laboratory. In 2008, he was named deputy manager of Leti’s Materials and Advanced Modules Laboratory, and public relations manager of the Nano-Electronic Division. Didier was named Leti’s international communications manager in 2010.

July 19, 2011 — Franklin Kalk, executive vice president of technology and CTO, Toppan Photomasks, covers the major lithography demands of distinct semiconductor device architectures: Logic, Flash, and DRAM. He also updates us on fabless/foundry relationships, and the supply chain in Japan in this video interview from SEMICON West 2011.

Kalk chats about his SEMICON West panel discussion about taking small fabless companies and ramping up to work with large foundries. A number of R&D foundries exist, and there are ways to minimize cost to bring projects before the large foundries.

Kalk also discusses logic, flash, and DRAM lithography. With logic, argon fluoride (ArF) and its many variants will be used through 14nm. Extreme ultraviolet (EUV) layers will probably be used at 14nm. EUV may also be inserted at 20nm, if everything goes according to plan in EUV lithography readiness, Kalk forecasts.

Flash is "a different story," with a very tight pitch but simple geometries. Pitch relaxation can be used almost indefinitely. Nanoimprint lithography (NIL) has the greatest chance of adoption in Flash, Kalk asserts.

DRAM needs EUV now, says Kalk. DRAM makers are active in consortia and tool development on the EUV side. EUV light sources still need more work on reliability, and cost-effective power. The EUV mask readiness is encouraging, says Kalk, with tooling infrastructure progressing well. True manufacturing issues, such as how to ship a mask safely, are now under investigation.

Finally, Kalk brings up concerns for Japan, as it continues recovery from the March 11 earthquake and tsunami. While the "orange flag" has gone down on materials supply worries, equipment suppliers were more impacted.

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July 19, 2011 – Management of mechanical stresses is one of the key enablers for the successful implementation of 3D integrated circuits using through-silicon vias (TSVs). The stress-related impact of the processing done at the various companies in the manufacturing supply chain needs to be characterized and shared, and designers need a DFM-like solution for managing stress.

In conjunction with SEMICON West, SEMATECH and Fraunhofer IZFP hosted "Stress management for 3D ICs using through silicon vias: Product-level reliability workshop" to address product level considerations for dealing with stress-driven reliability mechanisms of the via-middle through-silicon-via (TSV) 3D stacking technologies. On Thursday, July 14, technologists and technology managers from various companies and institutions in the US, Asia, and Europe gathered to examine what is required at the product level to managing stress in 3D interconnects, and to drive consensus and support for these techniques across the industry.

In a series of invited talks, speakers discussed the following:

  • Keynote presenter Mark Nakamoto of Qualcomm shared a high-level perspective of product reliability and new risks associated with the use of new features: TSVs and microbumps, new materials and processes, and new chip package interactions using thinned die and hard microbumps.

  • Eric Beyne of IMEC presented on failure analysis challenges and techniques including X-ray tomography, magnetic current imaging, time domain reflectometry, photon emission microscopy, SAM, lock-in thermography, IR, and SAW based techniques.

  • Ron Huemoeller of Amkor discussed some of the new failure mechanisms that might not be addressed by traditional package qualification tests, and concluded that a paradigm shift in engineering for reliability is needed.

  • TSV intrinsic reliability and reliability qualification challenges was presented by You-Wen Yau of Qualcomm CDMA Technologies.

  • Suresh Ramalingam of Xilinx discussed the current status of reliability testing, stress simulations, and failure mode analysis for his company’s Stacked Silicon Interconnect Technology.

In the afternoon, a working session focused on discussing failure mechanisms, test structures, material characteristics, measurement techniques, and modeling techniques.

On Wednesday, October 12, in conjunction with SEMICON Europa, a sixth workshop, hosted by Fraunhofer IZFP in collaboration with SEMATECH, will focus on reliability-limiting degradation kinetics.

SEMATECH is hosting a 3D Interconnect wiki site to provide a forum to the community to discuss the issues raised in these workshops.

July 19, 2011 — Matthew Taylor became CEO of Edwards about one year ago. He speaks about the business and the industry’s ramp up over 2010-2011.

2010 was a record year for Edwards, with another half-year record so far in 2011. Margins and delivery times are improving, and new products are entering the market.

Each market in which Edwards is a supplier — semiconductors, flat panel, photovoltaics, LEDs, has its own cycles and technology requirements. Semiconductor remains the largest sector for Edwards, but flat panel display (FPD) and photovoltaics manufacturing are growth areas. Edwards uses a core architecture then specializes it to meet the needs of each sector. AMOLED and latest-gen flat panel display manufacturing present gas delivery/vacuum challenges, which Edwards has found to be exciting and evolving.

Edwards received the 2011 SEMICON West Sustainable Technology Award. The EZENITH integrated vacuum and abatement system was selected by a panel of industry experts, demonstrating the product

July 18, 2011 — During SEMICON West 2011, SEMATECH announced the world’s first 450mm imprinted wafer, accomplished by EV Group (EVG). In a podcast interview, Markus Wimplinger, corporate technology development and IP director at EVG, described the timeline for the 450mm effort and how the company decided to make a strategic move — one that was not so much based on getting a check for the right amount.

Figure 1. 450mm wafer loaded on the EVG770
wafer stage.

The company used its SMS-NIL technology, also known as soft molecular scale nanoimprint lithography, to imprint the wafer. "It was beneficial because it’s very compliant and could also accommodate the limited wafer quality available at 450mm at that point in time," said Wimplinger. "We imprinted 35nm lines and spaces, but this is not the limit that this technology can do. We’ve demonstrated capability down to 12.5nm lines and spaces on smaller substrates."


 

For the company, the effort was a strategic business decision. "We had a 450mm program for quite some time," said Wimplinger. "So when we designed our second generation stepper, the primary focus was on 300mm, but we had already designed some 450mm capability, so we had the system available: we had the platform that could do it. We believe the transition to 450mm will happen in the not too distant future; it was a strategic decision." EVG introduced a wafer bonding system for 450mm at SEMICON West 2011.

Figure 2. 450mm step and repeat imprinted wafer with 35nm features.

Although Wimplinger explained that the timeline for 450mm insertion differs for different players, EVG thinks that the time frame for HVM is 2015-2017. And while nanoimprint is a back-up plan if EUV lithography is not ready, the industry can probably squeeze one more node out of immersion lithography, said Wimplinger.

Figure 3. Metrology of imprinted features.

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Click to EnlargeJuly 15, 2011 – On Wednesday evening, the SEMI folks had a nice appreciation reception for the many volunteers who serve on planning committees and standards groups and provide other services to the SEMI organization and to the industry. Well, you’re welcome, SEMI. It was nice to be appreciated.

At each SEMICON, there are typically one or two products that attract my attention and possibly even motivate me to some level of excitement. One such catalyst this year was Vantage Technology, a Campbell, CA startup that measures particles in flowing fluids. Ho hum, you say, it’s been done and we know that our CMP slurry is in spec, or that our high-purity lines are clean. Perhaps. And maybe you’ve reached those conclusions fairly because that is what your data has told you to believe — you take your samples periodically, dilute them 1,000

July 15, 2011 – Welcome to our third roundup of observations from SEMICON West 2011; we’ll be looking at LED technology and executive opinions on big-picture industry issues, and adding a few observations about the state of play in the solar market.

SEMICON West 2011
Day 1: SOI vs. FinFET, ReRAM vs. 3D NAND, and lots of video data
Day 2: A lithography-rich day
Day 3: Advancement in LED, exec perspectives, solar observations

LED improvements

The LED session at the TechXPOT venue was, like many of the other TechXPOT sessions, very well attended, with standing-room crowds, drawn by the prospect of an emerging semiconductor market with the potential to generate massive unit sales in the general lighting sector. Before this can happen on a mass scale, however, a steep reduction is needed in cost per lumen through a combination of performance boosts and manufacturing cost reduction. Speakers at the session reported progress in key areas, including efficiency, binning, epitaxy, manufacturing processes, and metrology.

On the performance side, the consensus is that efficiency for warm-light LEDs will increase from 100 lm/W today to 200 lm/W by 2020. An increase in input drive current from 350mA to 2A is one part of this process; it will also facilitate higher-power LEDs.

Unfortunately, nitride LEDs are plagued by the "droop" issue — at high operating currents, efficiency decreases. The origin of droop is still hotly debated, with the two leading hypotheses being carrier leakage and Auger recombination. The solution is tricky, as it requires growth of LEDs along non-polar or semi-polar crystal orientations (an area of active development), or reduction of carrier density in the active region by increasing the thickness of the quantum wells, which is not practical for high-power LEDs.

In the manufacturing cost arena, the primary focus in recent years has been on moving to larger wafers, reducing cost of ownership on front-end epitaxy, and improving overall packaged LED binning yields. The shift to 150mm substrates is expected to happen in under four years, compared to more than a decade for the 50mm-to-100mm transition. Top-tier LED companies are also eyeing larger substrates, but performance and yield remain challenging due to lattice and thermal mismatch between gallium nitride and silicon.

An interesting equipment trend is the race to make bigger, more efficient, MOCVD tools for nitride LEDs. Veeco has introduced the first production cluster tool for LEDs, while Aixtron recently announced a new record for wafer capacity (16 100mm wafers) for its Circus platform. Other approaches to reduce manufacturing cost, such as inline yield management and thin substrate handling during laser lift-off, are also being adopted.

Execs speak: Evolving adoption, favorite innovations

Wednesday afternoon’s Executive Summit, moderated by SEMI’s semiconductor business president Jonathan Davis, provided some interesting perspectives from top-level management.

Several panelists commented on evolving patterns of electronics consumption. Steve Newberry, president and CEO of Lam Research, noted that portable electronics are quickly becoming a necessity and not a luxury; Rick Wallace, his counterpart at KLA-Tencor, said he is bullish about the middle class using much more of its disposable income on electronics, and also about some 2 billion new customers who will want smart phones, music players, and other portable devices. Terry Brewer, founder and president of Brewer Scientific, commented on the importance of better user interfaces in this evolution, with Apple’s growth and success being testimony to this. (Davis had earlier pointed out that Apple recently became the largest IC buyer in the world, to the tune of $17.5 billion annually.)

When the topic turned to favorite innovations of the past year, Doug Neugold, chairman, CEO and president of ATMI, said he is getting a kick out of redeploying technology (such as material selectivity solutions for advanced ICs) towards handling electronic waste issues, like selective removal and recovery of metals from waste PC boards. Williams cited the use of laser-enhanced plasma in EUV illumination sources to create brightness five to ten times that of the sun.

Solar pricing, installation bottleneck, utility-scale concerns

Speaking of solar matters, there’s been at lot of talk on the show floor about plunging prices on solar modules, with reports of $1.20 to $1.30/watt or even less becoming common. While lower prices are in general a good thing, these levels (driven by a combination of declining demand in Europe due to fewer subsidies and a surge in manufacturing) are making life miserable for some in the startup community who had been planning on higher revenues.

Some are speculating that solar prices could become an international trade issue, with concerns that the large number of new producers in China may be dumping products below cost.

Another interesting aspect is that installation has become a bottleneck in the residential and commercial sectors; potential US demand at these lower prices cannot be fully realized given a general shortage of "boots-on-the-ground" experienced marketing and sales personnel generating an order pipeline. In part because of this, installers have not had to lower their prices despite lower module costs, so margins have improved. We talked to one Southern California installer who noted that a few months ago, he couldn’t get his calls returned when he wanted to buy panels; today, panel suppliers are calling him.

Utility-scale installations are a another challenge, however; financing and permitting remain huge issues, and the returns are still not broadly compelling at all-in costs of $3/watt or more when financial costs are included. Bankability is a much greater issue in this end of the market, while efficiency is top-of-mind in residential and commercial.

It will be interesting to see how the solar industry matures and if it evolves in a similar manner to what we have seen in semiconductors.

Overall, it has been another great year for the SEMICON/Intersolar shows!