Category Archives: Semicon West

July 15, 2011 — Test equipment maker Rasco GmbH, a Cohu Inc. (NASDAQ: COHU) subsidiary, added 2 MEMS testers to its product line: Pressure Test Unit (PTU) and the Acoustic Test Unit (ATU).

The test systems are meant to be flexible and run with high parallelism, testing up to 32 MEMS ICs in parallel. They boast a modular design for integration on gravity-feed, test-in-strip, and pick-and-place handlers.

The ATU tests audio devices used in a variety of consumer electronics and automotive applications.

The PTU offers high accuracy testing of integrated pressure sensors used in the automotive market.

Rasco also offers magnetic, optical and temperature sensor device testers.

The MEMS test tools debuted at Semicon West 2011.

Cohu, through its Delta Design and Rasco subsidiaries, is a supplier of test handling, burn-in, thermal subsystems and MEMS test solutions used by the global semiconductor industry. Cohu acquired Rasco in 2008. Learn more at www.cohu.com

See Rasco’s SO7100 Magnetic Test Unit (MTU), SO7200 Pressure Test Unit (PTU), SO7300 Optical Test Unit (OTU), SO7400 Acoustic Test Unit (ATU), and SO7600 Sensor Test Unit (STU) specs at http://www.rasco.de/english/produkte/contactors-mems.htm

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July 15, 2011 — SigmaTech’s UltraMap-TSV system won Best of West at SEMICON West, presented by industry association SEMI and Solid State Technology.

The UltraMap-TSV system from SigmaTech is the world’s first fully automated through silicon via (TSV) and deep-trench metrology system capable of characterizing both TSV and deep-trench features from both the front and back sides of subject wafers, up to 300mm in diameter.

The winner was chosen by a prestigious panel of judges representing a broad spectrum of the microelectronics industry.

Check out all 3 finalists here.

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July 15, 2011 — Lithography light source maker Gigaphoton Inc. verified its original technology for mitigating debris with magnetic fields for laser-produced plasma (LPP) light sources, clearing a hurdle for mass-production use.

Gigaphoton has been developing LPP light sources for EUV lithography since 2002, aiming for higher output and better CoO. Gigaphoton has now proven in production-level light sources that its debris mitigation with magnetic fields technology removes 93% of debris. Also read: The physics behind Gigaphoton’s EUV source

LPP light sources allow radiation by a CO2 laser of the Sn target (droplets) to cause EUV emission. Sn debris, such as Sn fragments and Sn atoms, land on the collector mirror and Sn ions damage the mirror’s multi-layer film, lowering reflectance. The debris mitigation technology with magnetic fields can reduce tin (Sn) deposited on the collector mirror and prevent damage to the mirror’s multi-layer film.

Gigaphoton’s magnetic debris mitigation technology combines the pre-pulse generated by a solid-state laser and the main pulse generated by a CO2 laser to suppress Sn fragment and neutral Sn atom generation, ionizing most of the Sn in each droplet. Ionized Sn is guided to the Sn catcher magnetically and removed.

During the verification experiment, the main pulse of the CO2 laser radiated each 20

July 14, 2011 — Jonathan Davis, SEMI, chats about standards development in 450mm and 3D IC, as well as the importance of collaboration, and how it is happening at SEMICON West.

There are a lot of options to continue semiconductor advancement, but they all require collaboration. Complexity is the word, Davis says. SEMICON West is a key event to bring parts of the industry together, in everything from SEMI standards meetings to exhibit hall meetings.

SEMI recently started a task force for 3D IC. In 450mm standards dev: 5 standards are available, 11 are in the pipeline, and more were discussed at SEMICON West. There is "substantial movement" in 450mm exploration, Davis notes. More specific declarations are coming out now, compared to a year ago, from the suppliers and chipmakers with 450mm on their company roadmaps.

Davis also discusses the semiconductor industry investment forecast, which his colleague Dan Tracy addresses here.

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July 14, 2011 — Sitaram Arkalgud, director of interconnect at SEMATECH, co-moderated a session on 3D perspectives and development of the infrastructure during the 3D TechXPOT session at SEMICON West ("3D in the Deep Submicron Era," July 13 at 1:50PM]).

Arkalgud discusses the high-volume manufacturability issues and gaps in both 2.5D and 3D semiconductor technologies with respect to backside processing and wafer bonding, thinning, and handling. The figure is a summary of SEMATECH’s results from its survey on gaps in the via-mid ecosystem.



In the podcast, Arkalgud reports on the efforts that have gone into developing a kind of "dashboard" for standardization efforts being undertaken by SEMATECH’s 3D Enablement Center, SEMI, and other standards bodies/organizations such as IEEE, JEDEC, and Si2. He also discussed the anticipated timeline for 3D TSV applications and volume manufacturing (see the chart).

Chart. 3D TSV outlook. SOURCE: SEMATECH
– 12 companies surveyed Aug-Sep 2010: IDMs, foundries, fabless, OSATs
– High density via-mid applications including interposers, heterogeneous stacking, logic on logic, memory on memory; 2011-2014 timeframe
– Addresses all aspects of via-mid: wafer processing, assembly, reliability, inspection/metrology, design, test
– Highest priorities for heterogeneous stacking (e.g., wide IO DRAM) shown below

Gaps in Standards and Specifications
EDA Exchange Formats: Partitioning and floorplanning; Logic verification; Power/Signal integrity analysis; Thermal analysis flow; Stress analysis flow; Physical verification; Timing analysis

Reliability: Reliability test methods

Test: DFT test access architecture

Inspection/metrology: TSV voids, defect mapping, microbump inspection and coplanarity

Chip Interface: Stackable memory pin assignment; Stackable memory physical pinout

TSV: Keep out area, fill materials, dimensions

Thin wafer handling: Universal thin wafer carrier

Technology Development and Cost Reduction
Reliability: Criteria; Test methods; ESD

Temporary bond/debond cost reduction: Materials and release mechanisms cost reduction; Equipment cost reduction

TSV: Keep out distance/area

 Microbumping and bonding: Pad metallurgy and layer thickness; Bump metallurgy

Inspection/metrology: Microbump inspection and coplanarity; TSV voids; BWP voids

Test: Probing microbumps cost reduction

SEMATECH has been busy at SEMICON West 2011:

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by Michael A. Fury, Techcet Group

Click to Enlarge July 14, 2011 – Roaming the show floor is always a mix of nostalgia (old friends are still in the business), reassurance that a new generation has taken an interest in the industry, and just a touch of melancholy that great halls that used to have to turn away semiconductor suppliers due to over-subscription are now shared with other industries like MEMS, LEDs and other lighting, displays, and of course the sprawling PV infrastructure (Intersolar this year actually encroached into a section of the North Hall of Moscone, with the West Hall across the way full to bursting.)

Bobbi Rossi and the folks at Spartan Felt are continuing to nudge their product lines from industrial glass closer to the CMP space each year. In addition to hard pads that can compete with IC-1000 and ceria fix abrasive pads, they are producing zirconia and silicon carbide fix abrasive pads for other industries. But given the variety of new materials being using in semiconductor devices, it won’t be long before someone tries these exotic pads for some new CMP application.

SEMICON West 2011
Day 0: Market forecasts, supply-chain dynamics
Day 1: Intersolar wanderings, SEMICON West symposium
Day 2: CMP views, outlooks for breakfast
Day 2.5: Roaming the floor, LEDs, CMP pads, kudos to Napoleon
Day 3: Two eye-catching technologies in CMP slurry, printed electronics

Peter Pozniak of Malema Sensors gave me a guided tour of their Coriolis flow meters that can maintain stable liquid flow readings with 50% air entrainment, far beyond the point at which an ultrasonic flow sensor will give up in despair. The meters work equally well on clear fluids and fully loaded slurries; in the case of slurries, they can even report the density of the materials flowing through. I don’t understand enough of the fundamental operating principles to give away any state secrets, but it is based on an invention attributed to Napoleon (yes, the Bonaparte one), who noticed that cannonballs fired along east-west lines found their targets more reliably than those fired along north-south lines. The rotation of the earth was the culprit, and Napoleon learned how to compensate accurately for this Coriolis effect.

Eric Virey, LED analyst for Yole D

by Michael A. Fury, Techcet Group

Click to Enlarge July 14, 2011 – I am so embarrassed! I had told several of my friends that the week would be in the mid-60s with no rain, so don’t bother to pack an umbrella. As a resident of San Francisco, I understand that the morning wetness on the ground and all over your glasses is just ground fog, the stuff that keeps the coastal redwoods healthy. My visiting friends just think I’m a lousy amateur meteorologist.

Outlooks for breakfast

About 60 of us braved the early morning soup to attend the PennWell breakfast and market outlook. Pete Singer, editor-in-chief of Solid State Technology and several other electronics publications, presented his snapshot of technology status and trends. Perspective matters; Pete stated that the 22nm technology is "pretty much developed," and attention is now turned to 16nm — I wonder how many of the 28nm and 32nm fab process engineers would agree. Over 35 companies are signed up to the ISMI 450mm program, still not enough for a complete pilot line but enough to be a serious trend. Likewise, 3D through-silicon via (TSV) is now a current technology instead of a speculative future technology, although new alternatives continue to emerge.

SEMICON West 2011
Day 0: Market forecasts, supply-chain dynamics
Day 1: Intersolar wanderings, SEMICON West symposium
Day 2: CMP views, outlooks for breakfast
Day 2.5: Roaming the floor, LEDs, CMP pads, kudos to Napoleon
Day 3: Two eye-catching technologies in CMP slurry, printed electronics

Tom Hausken, research director at Strategies Unlimited, provided the 50,000-foot level view of the semiconductor market in a macroeconomic context. Overall, we’re back on track for a 5.7% CAGR that is contiguous with the pre-recession trend. One example he cite was Cymer, which is pure-play in lasers for semiconductor lithography. During the recession, they dropped down to single-digit quarterly shipments, then resumed their volumes very rapidly thereafter. (For years, I have used the following mathematics to characterize the cyclicality of the semiconductor manufacturing supplier community. The materials business behaves like the integral of installed capacity. The equipment business behaves like the first derivative of new capacity. Think about it; it’s not a bad model. Personally, I’ve found it to be a great guide for career decisions.) Aixtron and Veeco have taken the lead positions in supplying equipment for LED manufacturing, demonstrating once again that the pack leaders at one node or technology aren’t necessarily the leaders in the next node or technology. The rapid growth of LED manufacturing volumes has provided some cost reduction benefits to the GaN and SiC power device markets.

CMP meeting

The NCCAVS CMPUG meeting attracted the usual suspects, with a lot of folks preferring to stand in the aisle rather than step into the arena. Having the talks on the show floor is a good enough marketing concept to be attractive, but the interference of the great hall buzz is still a distraction I would prefer to do without. CMPUG presentations will be available in a week or two on

July 14, 2011 –  Wednesday at SEMICON West 2011 was a lithography-rich day, with the Sokudo Lithography Breakfast and some interesting keynote speech comments.

SEMICON West 2011
Day 1: SOI vs. FinFET, ReRAM vs. 3D NAND, and lots of video data
Day 2: A lithography-rich day
Day 3: Advancement in LED, exec perspectives, solar observations

The always-anticipated litho breakfast did not disappoint. Mark Kelling of GlobalFoundries described his company’s approach to the transition from 22 to 20nm, and what this will involve: moving poly pitch from 100 to 80nm, and metal pitch from 80 to 64nm. GlobalFoundries will adopt a unique double-patterning process that utilizes a negative-tone develop resist process, he noted, but did not reveal the materials involved.

The two remaining advanced optical lithography suppliers, Nikon and ASML, both offered roadmap presentations that outlined their expectations for the last generations of 193 and the advent of EUV technology into production. Nikon noted that its upcoming 621D optical system will have a remarkable 2nm/3s overlay spec. These advanced systems will feature scanning tuning exposure control to be able to extend immersion 193nm performance. On the EUV side, their EUV-1 development tool will have an NA of 0.25, with the production-oriented EUV-HVM boosting this to NA=0.4.

For its part, ASML laid out an EUV roadmap going from the developmental NXE3100, also with a 0.25 NA, to the 3300B, which will have specified throughput of 125 wafers/hour, assuming the availability of a source that can deliver 15mJ of energy to the wafer surface. ASML currently has three EUV tools at customer sites running wafers, with a fourth being installed, and plans in place to ship 10 units in 2012. Interestingly, the company has not yet made a final decision on its source supplier.

Another angle on post-optical lithography came from Mapper Lithography, which is developing a multi-beam e-beam direct-write system. Using excellent presentation graphics, Bert Jan Kampherbeek explained that Mapper’s initial machine, the 1.1, will have throughput of 1WPH at 25nm, when shipped to French research agency Leti and Taiwanese foundry TSMC next year. The company plans to use clustering of multiple beam sources to boost throughput to 10WPH and ultimately 100WPH in time for the 16nm process node. Mapper’s value proposition will hinge on throughput per unit investment; they hope to sell machines for

July 14, 2011 – During a 450mm industry briefing held in conjunction with SEMICON West, the International SEMATECH Manufacturing Initiative (ISMI) presented the steps it is taking this year to provide the infrastructure and momentum to enable the 450mm transition. This program plays a critical role in coordinating industry efforts on 450mm wafer supply, standards setting, test wafer generation and equipment demonstration.

Participation in the 450 program has doubled in last 18 months, according to the consortia. Interaction between the consortia and industry is intensifying in pace and breadth.

450mm program strategy and projected scope. (Source: ISMI)

Some progress updates, snipped from the discussions:

Wafers: Requests for 450mm wafer loans are rapidly increasing. ~750 wafers have been loaned to >40 suppliers, up from ~440 to 25 suppliers a year ago.

Equipment: Silicon suppliers have installed 450mm dedicated equipment and are manufacturing developmental test wafers in large volume, improving the wafer quality. 10 tools are operational or on order for the cleanroom, up from three a year ago. Factory infrastructure components to enable safe and secure 450mm operations are being implemented now.

Processes: 450mm readiness is increasing in all areas of the supply chain, and progress is accelerating rapidly. 450mm development is underway for most required capabilities (most from multiple providers) to enable the transition, vs. <10 required capabilities at this time last year. That includes a now-defined patterning strategy. Increased consortium cleanroom operations have resulted in cleaner wafers, blanket films, and improved wafer shipping techniques.

Integration: The 450mm factory integration standards are completed, and testbed scope is finished. Pilot line evaluations show "low risk" for 450mm, ISMI says. The first 450mm stocker is now shipping to the 450mm consortium.

Collaboration will continue to be critical for a cost-effective and timely 450mm transition, ISMI emphasized. Consortia and related groups have historically been effective, and success in 450mm will rely on comprehensive industry-wide collaboration. Benefits checked off by ISMI: it’s cost-effective for a precompetitive environment, it leverages the larger community’s expertise and experience, and aligns participants to common goals and timelines.

More on 450mm:

July 14, 2011 — ESI Inc. (Nasdaq:ESIO), laser-based manufacturing equipment supplier, uncrated the Model 5390 micromachining system for advanced LED via drilling and the AccuScribe 2600 LED wafer scribing system at SEMICON West.

The Model 5390 laser-based micromachining system creates electrical interconnections on LED packages, optimizing via placement accuracy.

It uses ESI’s high-speed compound beam positioner coupled with a high-power CO2 laser, enabling user-definable variable pulse width and pulse repetition frequencies of up to 300kHz. The system can produce more than 100 vias per second in typical single layer dielectric materials.

The first Model 5390 has shipped to an LED manufacturer.

ESI’s AccuScribe 2600 is built for high brightness LED (HB-LED) manufacturing, scribing patterned sapphire substrate (PSS), distributed Bragg reflector (DBR), metal mirror (MM) and other advanced wafers. HB-LEDs change LED architecture and manufacturing processes, said Jonathan Sabol, general manager of ESI’s LED