Category Archives: Semicon West

July 18, 2007 – Carl Zeiss SMT AG announced at SEMICON West today its new optical lithography system for KrF, the Starlith 1000, with a numerical aperture (NA) of 0.93, which will reportedly be the highest NA for 248nm exposure wavelength available in the market.

The high NA is said to provide a more cost-effective solution for patterning of features down to 80nm in volume chip production. The Starlith 1000 system will be part of ASML’s new TWINSCAN XT:1000, which will begin shipping next year.

“Together with our strategic partner ASML, we have investigated customer needs, initiating the development of Starlith 1000. With Starlith 1000, the application range of KrF lithography is further extended,” said Winfried Kaiser, VP, product strategy at Carl Zeiss SMT’s Lithography Optics Division.

by Phil LoPiccolo, Editor-in-Chief, Solid State Technology

While the consumerization of the electronics industry is creating huge demand for semiconductor content, it is also causing enormous stress for chipmakers and equipment suppliers alike, according to representatives from each group speaking at a SEMI Executive Panel on Monday (July 16) at SEMICON West.

“The consumer now represents about 53% of the demand for semiconductors,” including those for game consoles, iPods, and the like, as well as for those portions of the PC and cell phone markets that are for personal use, according to George Scalise, president of the Semiconductor Industry Association. One benefit of consumerization is that the market is being driven much further and faster by the consumer than it has traditionally been driven by enterprise IT over the last several years, he said.

“We expect unit volume growth of 10%-15% per year,” Scalise said, but bit growth will likely grow 55%-60% per year. At the same time, a consequence of having consumers account for the majority of semiconductor sales is that product lifecycles are shorter — down to slightly more than one-year cycles, instead of two- to three-year cycles that the industry has been accustomed to. “Consumers are fickle buyers,” he said. “Once they get their fill of a product, they look for the next one.”

How is this shift affecting the industry? “From a design perspective, the effect of consumerization is enormous,” said Aart de Geus, chairman and CEO of Synopsys. “In the last four or five years, we’ve seen the consumer become the driver for design,” a trend that started with proliferation of the cell phone, and is now continuing thanks in part to the emergence of video, he said. With video, he noted, consumers are demanding an ever greater number of pixels, which will spur manufacturers to build increasingly higher-capacity technologies for data capture, transmission, processing, display, and storage, with no end in sight.

In parallel, the degree of globalization of the end markets will be great, de Geus said, explaining that the next 10 years will see a doubling of the number of consumers of electronics. Unfortunately, most of this new wave will not be at the same economic level as the earlier adopters, so there is tremendous pressure to reduce costs, he said. Moreover, the people who buy cell phones in places such as China, India, or (in the not-too-distant future) Africa, fundamentally want the same capabilities while at the same time demanding better quality, as they will be spending a greater portion of their resources on these products, he said. “From the design perspective, this has increased the stress level enormously, and it has increased the stress level on manufacturing because slight variations in yield directly affect the cost equation.”

Consumerization is also creating stress among equipment suppliers. “We’re finding that consumer products are creating a dramatic compression of market cycles versus IT investments, which are longer with larger peaks and valleys,” said Ed Grady, president and CEO of Brooks Automation. There’s also greater seasonality, with Christmas and summer vacation seasons creating higher demand patterns. In addition, because the market is consumer driven, macroeconomics is having an impact — for example, companies need to consider how sales of products might be affected by, say, a drop in disposable income levels due to rising gas prices, he said.

Also, in the fabs, because the chips are becoming more complex (i.e., in the number of different materials and levels on a chip), all of the process steps (e.g., lithography, PVD, and CVD) are becoming more difficult, and require a greater number and diversity of tools, Grady contended. Moreover, the fabs are being forced to change to remain productive and efficient in a high-product-mix, short-product-lifecycle environment, he said, versus 10 or 15 years ago when you could produce an entire generation of product in a DRAM fab, for instance, and run out your capital investment. — P.L.

(July 18, 2007) SAN FRANCISCO &#151 Visctec Semiconductor Systems GmbH (Weilburg, Germany) will combine its electron beam and lithography business groups to create Vistec Electron Beam Lithography Group, with European and U.S. locations. Jai Hakhu, Ph.D., will lead the business, and realigned global sales, marketing, and service structures will be managed by Maarten Kramer. The newly formed business will present its lithography portfolio at SEMICON West exhibits, July 17–19 in San Francisco.

by Phil LoPiccolo, Editor-in-Chief, Solid State Technology

Delivering the opening keynote address at SEMICON West on Tuesday (July 17), Douglas Grose, AMD’s SVP of technology development, manufacturing, and supply chain, assailed a widely held “faulty belief” in the uniqueness of the semiconductor manufacturing, calling on the industry to adopt highly successful principles and practices of lean manufacturing deployed in other industries.

“There’s an assumption in our industry that the complex and delicate processes of semiconductor fabrication can’t be streamlined,” said Grose, citing worries about risk in tinkering with production lines due to the belief that the relentless technology shrink of transistors and growing wafer sizes are what produce regular productivity enhancements. “But these are faulty beliefs that keep us locked into processes that limit our growth.”

A number of years ago, AMD engineers started thinking about the next step in improving the company’s manufacturing, having already increased output of AMD’s Fab 30 in Dresden, Germany, to levels 50% higher than what the facility was originally designed to produce, according to Grose. They realized they needed to cut rising costs, manage fluctuating profit margins, and deal with other factors that were clearly not limited to chipmaking, and so they began to look for answers beyond the semiconductor industry.

That search led to the automotive industry, “where lean-manufacturing techniques had created kings,” Grose said. Indeed, decades ago, Toyota developed a lean-manufacturing philosophy — credited as largely responsible for the success they enjoy today — that enabled the company to reduce the average development time for a vehicle to 24 months, about half the industry average, he said.

Similarly, when faced with a dire financial picture, Porsche implemented lean practices in an ambitious pursuit of efficiency improvement, Grose added. In five years, the automaker doubled productivity, cut defects in supplier parts by 90%, shortened lead times from six weeks to three days, and cut parts inventory by 90%.

“After we stood back and recognized the significance of the changes that Toyota and Porsche had made,” said Grose, “we sought their advice on how to apply lean manufacturing to AMD’s fab processes.” As a result, the team first looked inside the fab, “where waste lives,” he said.

What AMD found, through industry research and internal data, was that 80% of its cycle time was actually idle time, Grose explained. “Yes, we can always improve the efficiency and throughput of tools and move to bigger wafers,” he said, “but the biggest return on investment is to move to a more streamlined fabrication model.”

Results achieved in 2006 cited by Grose are impressive. By reducing lot sizes at Fab 30 and re-architecting the facility’s transportation and delivery systems, AMD increased production and efficiency, while cutting cycle time, inventory, and overall costs. Wafer starts rose 31%, cycle time/mask layer fell 33%, productivity increased 77%, and overall wafer costs dropped by 26%. “Not only are we better positioned to manage the product mix, we also reduced cost, and increased output,” Grose said. Meanwhile, at its Singapore fab, the chipmaker re-architected backend lines to increase output by 75,000 wafers, shrink the physical footprint of the lines by 25%, and reduce cycle time by 47% — thus gaining the flexibility to expand those operations without acquiring new facilities or adding real estate, he said.

Moving forward, Grose’s goal is to expand lean processes throughout the company’s supply chain and beyond. “This is not a vision only for AMD and its transformation; this is an industry transformation,” he said. “I can tell you that we’re nowhere near close to hitting the wall.” –P.L.

July 17, 2007 – A new system for ultrathin wafer processing developed by Brewer Science Inc. and EV Group aims to provide a temporary wafer bonding technology for reliably processing sub-100-micron thinned wafers.

The jointly developed technology, combining Brewer’s WaferBOND HT series of materials and EV Group’s bonding and debonding equipment platforms (EVG 850TBDB), performs temporary bonding of original-thickness device wafers onto rigid carrier wafers. The WaferBOND HT materials are spin-coated on, baked, and bonded on the EVG system, preparing for thinning and further backside processing steps with the created waferstack, the companies said.

Meanwhile, at SEMICON West, Brewer says it has commercialized its first-generation WaferBOND HT-250 coating, targeting higher-temperature advanced processes for flash memory, image sensors, and power devices. The polymeric spin-on coating enables device substrates to be temporarily bonded to a carrier substrate for thinning and follow-on processes, such as deposition, lithography, etching, plating, annealing and cleaning, to generate through-hole via structures and redistribution layers on the thin device wafer, the company says.

Brewer says the material has processing capability >200 deg.C with “broad” chemical resistance and process capability, low total thickness variation (<0.5-microns at 10nm), "excellent edge protection," <5mins slide-off debonding cycle, and "easy" polar solvent cleanup.

IMAGE CAPTION: Wafer with 0.7

(July 17, 2007) SAN FRANCISCO &#151 SEMICON West hosted a panel discussion between executives from equipment and materials suppliers, a design software firm, and an industry association. Panelists discussed the consumer factor on electronics supply chains, design cycles, and capital equipment and consumables. Stanley T. Myers started off the debate by referencing Apple’s newly released iPhone, and the “killer apps” that consumers seek in the market.

by James Montgomery, News Editor, Solid State Technology

Days before Semicon West, WaferNEWS caught up with Christopher Moore, president/CEO of Advanced Metrology Systems (AMS), nee Philips AMS, to chat about how life is different nine months after taking the private equity route.

The first thing he pointed out is the need to understand the difference between private equity (PE) and venture capital (VC) investments, and why the former was the right play for AMS. While VCs primarily seek out investments with a clear goal of a quick and bountiful return, “private equity’s long-term goal is to grow the business, and they have the patience to let us do that,” recognizing that in the semiconductor industry development-to-production timelines can be two years or more. Former parent Philips also showed patience with the business, he added, but it was always clear (and uneasily so among customers) that AMS wasn’t in the European firm’s long-term core plans.

Moore also indicated that the increasing presence of private equity circling the semiconductor industry looking for deals has changed many companies’ outlooks about their potential exit strategies, particularly in the crowded metrology space. “Before I got into this business, I would have said we’re going to be sold to a bigger player, or go IPO,” he told WaferNEWS, “but now I’m beginning to believe more and more that the exit strategy in this type of business is another private equity round.” Even the sector’s biggest players, which in the past have proven to be consolidators vs. consolidatees, might not be immune to PE interest — “anybody would be much smaller than the deal done with Chrysler, if someone seriously wanted to take a run at them,” Moore pointed out (referring to this May’s $7.4 billion deal for Daimler-Benz selling an 80% stake in the US automaker to Cerberus Capital Management). “If there’s a good opportunity, then there’s private equity willing to do it, whether it’s in semiconductors or something else.”

In addition to a change in exit strategy, Moore also has had a change-of-heart about the well-accepted belief in building “critical mass” to compete in an industry segment. “I subscribed to that for a long time,” he said, noting that in any commodity market critical mass is perhaps the most important strategy to compete. But semiconductor equipment, and particularly metrology, he pointed out, is a specialists’ arena, with application-specific systems and tools geared to do certain things, so critical mass is less important than leveraging specific knowledge. “If you can find a market, not $200 million but maybe $30-$50 million market, that’s a good business if you can string some of them together […] and support tools for those specific applications with specific knowledge.”

AMS’ business is chugging along, expected to repeat the 50% business growth enjoyed last year, even though Moore said he didn’t expect the market’s softness to extend into 2Q07 (>50% of AMS’ business is in DRAM, which has been pummeled so far this year). As a buffer the company now has 10%-15% of its business in power devices, up from zero in 2006. Explaining the differences required to do business in those fields, Moore explained that DRAM lends itself well to consortia efforts, where there’s a universal approach among partners early in the process, although there will be some tweaks and nuances to transfer technologies to the fab levels. Power, though, is largely a collection of individual companies, and much more of a mix of capacity investments vs. technology buys, he noted.

Looking ahead to SEMICON West, Moore is particularly interested in learning what people are thinking about 3D structures, and of course the metrology for chipmakers that are using the third dimension “to actually build things instead of just putting layers on.” He also revealed that there’s been a lot of “serious, pilot-process work” going on behind the scenes in finFETs, and many may not realize just how far this technology has come — he indicated AMS is working two customers (from different industry consortia) who expect to have the capability to put finFETs in production next year, suggesting the 45nm node. “Given what we’ve seen, it’s not ‘yeah we’ll do it at 45nm,’ not a fait accompli,” he told WaferNEWS, “but it certainly looks like it’s doable.” — J.M.

by Bob Haavind, Editorial Director, Solid State Technology

Sharp differences on the need to prepare for a shift to 450mm wafers broke into the open on SEMICON West’s opening day (Monday, July 16).

Speaking for toolmakers, Stan Myers, SEMI CEO, at a morning press briefing, stated that: “Huge benefits remain to be gained by improving 300mm productivity.” This effort is currently underway in the 300mm Prime program, spearheaded by International SEMATECH, a chipmakers’ consortium.

“Only after these gains,” Myers added, “does it make sense to go to a larger wafer size.”

He suggested that the timing for such a shift might be around 2020 or later, making it unnecessary for the industry to begin preparations now. Myers added that, since it appears that it will be increasingly difficult to meet performance targets with silicon as features continue to shrink, it might be necessary to consider some alternate wafer materials in the future. This is another reason to put off preparations for an eventual 450mm shift, he suggested. He also said that chipmakers with a diverse product mix, such as major foundries, might not benefit from a 450mm wafer transition.

A very different view of the need to prepare now for an eventual 450mm transition was presented by Scott Kramer, of International SEMATECH, at a briefing and workshop for some 100 industry representatives, including vendors, on Monday afternoon. Kramer, who directs the International SEMATECH Manufacturing Initiative (ISMI) that has been conducting the 300mm Prime effort, emphasized that it is part of a complementary forward-compatible approach that will transfer lessons learned in the 300mm Prime effort to a 450mm transition within the next few years.

Early work indicates that although 300mm Prime promises to cut processing cycle times by up to 40% (vital for fast-paced consumer product cycles), it offers little chance for needed cost reductions. In fact, without a 450mm wafer transition, the semiconductor industry faces a $150 billion productivity gap by 2013, with a 50% increase in cost/transistor, Kramer suggested.

He said that history indicates that to maintain the pace of Moore’s Law, a wafer size increase is required about every seven years, which would mean a shift at about 2013.

SEMATECH is now conducting fab studies and simulations to determine whether the 450mm transition could “move out to an intermediate timeframe,” or needs to be accelerated, according to Tom Abell, 450mm program manager and Intel assignee to SEMATECH.

Under the 300mm Prime effort, reduction targets of 30% in cost, and 50% in cycle time, were set in 2Q06, Abell explained, which tracks the ITRS projections. Working with a wide range of fabs, the ISMI analysis showed the potential for 40% cycle time reductions, but only 3% cost savings, which might be improved to 10% — still far short of the 30% target.

Unfortunately, process tools for 300mm were designed back in the mid-1990s, before the explosion of foundries, so they are aimed primarily at high-volume, low-mix chip production. Much of the 300mm Prime work, according to Abell, is to improve the performance for the low-volume, high-mix needs of big foundries.

Due to the shortcomings of 300mm Prime, ISMI is initiating a 450mm program, according to Kramer. In 2008, it will pursue availability of 450mm wafers (which may need to be 1mm thick due to sagging at the edges from gravity), 450mm factory guidelines and standards, and creation of a 450mm factory integration testbed.

One problem: the members of ISMI are all chipmakers, representing some 60% of global IC revenues (Samsung, NEC, Panasonic/Matsushita, Spansion, Micron, TSMC, HP, TI, AMD, IBM, Renesas, Intel, Infineon, Qimonda, and NXP), according to Kramer — but no toolmakers. Why then, Kramer was asked, should the toolmakers cooperate with the effort?

“ISMI members are their customers,” he replied.

Stay tuned. — B.H.

by Katherine Derbyshire, Contributing Editor, Solid State Technology

What happens when you put a design software vendor, a chip manufacturer, and a photomask maker all at one table and ask them to talk about yield? Not surprisingly, the software vendor finds himself on the hot seat.

Monday (July 16) at SEMICON West, Synopsys VP Anantha Sethuraman found himself wedged between Dan Armbrust of IBM’s Systems and Technology Group, and Chris Progler, CTO of Photronics. The occasion was a panel discussion on DFM — which the panelists agreed stands for “design for money” — and yield. As Sethuraman put it, “we aren’t chasing dirt anymore.” Process variability and the ability to actually manufacture a given design are now critical to success in the IC industry.

Except it’s not so easy to actually do that. Many approaches to yield improvement focus on identifying process sensitivities, and avoiding those features. Most companies, Progler said, are making more regular, array-like designs, even for logic. Array structures allow NAND flash companies to achieve very high yields, even using aggressive lithography that pushes the theoretical resolution limit. Armbrust reminded the audience, though, that constraining the designers makes a design take longer. A chip that doesn’t yield can’t make money, but neither can a design that doesn’t exist, he pointed out, so software tools must help manufacturers balance these tradeoffs.

And in fact, the software is beginning to do exactly that. Sethuraman claimed that Synopsys software incorporates a good understanding of where variability comes from. For IBM, predicting yield is critical to the success of the company’s foundry business, and also critical for planning launches of integrated systems. Good yield predictions are the foundation of good inventory control.

On the mask side, though, the picture is not so bright, according to Progler. On some designs, he said, only 10%-20% of photomask defects actually matter, while on others, 80%-90% of defects are critical — yet mask acceptance criteria do not differentiate between the two. Though tools can identify defects as noncritical, people clearly don’t trust the results enough to risk their production. A more trustworthy link between inspection results and manufacturing outcomes would be “revolutionary,” giving enormous cost and scheduling improvements, he said. Moreover, as the first physical embodiment of the design, the mask potentially offers an enormous amount of information. Even without a complete process flow, a photomask allows manufacturers to begin to measure actual process outcomes, rather than relying on simulations. Yet so far, this resource remains largely untapped.

Despite their differences, all the panelists agreed that the situation will get worse as the industry moves to 65nm and 45nm features. The shift to 65nm will bring fundamental process changes, including some use of immersion lithography. At 45nm and below, stress fields are more difficult to manage, and new gate stacks begin to appear. Much like this SEMICON West DFM panel, software vendors are likely to find themselves wedged between manufacturers and designers for years to come. –K.D.

July 16, 2007 – Scanimetrics Inc. has debuted at SEMICON West with its first product targeting the test sector: a noncontact “virtual probe” technology for system-in-package testing during assembly that it claims can cut manufacturing costs in half.

The Wi-TAP (wireless test access port) helps SiP chipmakers test and identify defective devices from the beginning of the assembly process, giving them a practical way to test for faulty devices before the multichip SiP package has been made, according to the company. That speeds up the ability to bring to market consumer handheld SiP devices that incorporate more functionality — e.g. cell phone and digital camera capabilities, plus Internet access, and GPS, noted Steven Slupsky, president and CEO of Scanimetrics, in a statement.

Embedding RF transceivers into the circuit to be tested, and a complimentary set of transceivers in the “virtual probe card,” lets Wi-TAP execute proximity testing of SiP devices across the gap between the probe card and the device under test, so companies can test from the onset of SiP assembly and after each new chip is added, the company explained (power is provided by a pair of traditional probe needles). If a bad die is found or a assembly defect detected, the SiP package ca be reworked or eliminated before assembly is completed, saving chip costs and manufacturing time.

The company isn’t yet ready to reveal its productization or customer plans, but claims it is working with “several major manufacturers” to incorporate its Wi-TAP technology into next-generation SiP products, and is working with them “as implementation partners” to develop other products for “specific semiconductor market sectors where we see strong opportunities,” Slupsky added.