July 13, 2012 – BUSINESS WIRE — Plasma processing tool supplier Nordson MARCH uncrated the FasTRAK Plasma System at SEMICON West. The automated, high-throughput vacuum plasma treatment system processes leadframe strips, laminate substrates, and other strip-type microelectronic components.
The tool
July 13, 2012 – BUSINESS WIRE — Bruker Corporation introduced three 450mm X-ray and atomic force microscopy (AFM) semiconductor metrology tools — the InSight-450 3DAFM, the D8 FABLINE X-ray system, and the S8 FABLINE-T X-ray system — during SEMICON West, this week in San Francisco, CA.
Eliminating the need for model setup, and providing TEM-like accuracy in fractions of the time without wafer damage, Bruker’s automated atomic force microscopes (AFMs) enable critical technology development and continued process control in semiconductor production. Based on the production-proven InSight 3DAFM platform for 300mm, the InSight-450 3DAFM suits various roughness, depth and CD applications. Capabilities include bare wafer process validation, roughness characterization and pit/bump/scratch defect metrology; incoming substrate qualification; thin film and epitaxial deposition performance with micro/nano roughness and angstrom-level step height precision; etch depth metrology for process development and control, in-line resist profile measurements of CD, SWA, and LER with full TEM-like profiles; and CMP flatness performance to monitor dishing and erosion. All of these applications are available in a single tool with no modeling required, full NIST traceability and no material or wafer damage, making it the ideal tool to provide early learning in 450mm process development with scalability to 450mm production.
Bruker’s X-ray metrology provides a reliable, accurate and non-contact method of characterizing various essential semi parameters without the need to use a reference. The next-generation D8 FABLINE is equipped with the latest high-brilliance X-ray sources, detector technology and user-friendly software for improved data analysis. The system provides various in-line, thin film X-ray measurements for front end of line (FEOL) and back end of line (BEOL) process monitoring on blank or product wafers. It can be used to determine thickness, composition and strain in SiGe, SiC, SOI, III-V on Si; as well as composition and thickness for metal films and stacks, including ALD layers. New and emerging device processing creates metal contamination control challenges for IC manufacturing. Bruker developed the S8 FABLINE-T TXRF (Total X-ray Reflection Fluorescence) for non-destructive trace metal and light element contamination analysis in semiconductor applications.
“Both X-Ray and high-resolution AFM technologies have been identified by the 2011 International Technology Roadmap as critical for the success of future semiconductor technology nodes,” said Bruker AXS division president Dr. Frank Burgäzy, speaking about the industry transistor from 300mm to 450mm wafers. Also read: The elephant has left the room — 450mm is a go! from blogger Dick James, Chipworks.
Bruker Corporation (NASDAQ:BRKR) provides high-performance scientific instruments and solutions for molecular and materials research, as well as for industrial and applied analysis. For more information about Bruker Corporation, please visit www.bruker.com.
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July 13, 2012 — At SEMICON West 2012, this week in San Francisco, CA, the working groups of the International Technology Roadmap for Semiconductors (ITRS) held 3 sessions (TechXPOTs) outlining 2012 updates to the roadmap. Check out the updates to the front-end, scaling roadmap working groups here.
The ITRS undergoes major revisions on odd-numbered years. 2012 being an even-numbered year, very little change occurred to the Overall Roadmap Technology Characteristics (ORTC). However, within the working groups, some updates were worth noting.
Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano-scaling steal the show
First, the changes to the ORTC, presented at the TechXPOT by Bob Doering. Of interest were changes focused directly or indirectly on 450mm. ITRS has moved the forecast production start date to 2015-2016. The definition of
July 13, 2012 — SEMICON West, this week in San Francisco, CA, hosted 3 TechXPOT sessions on the International Technology Roadmap for Semiconductors (ITRS, http://www.itrs.net/) 2012 update. At the back-end technologies session, roadmapping for More than Moore was addressed as both a philosophical and technical matter.
Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano-scaling steal the show
Introducing the back-end-focused working group presentations, Bob Doering, representing the Overall Roadmap Technology Characteristics (ORTC), said that the Roadmap is not just about scaling anymore. Patrick Cogez, presenting More than Moore, picked up this thread, saying that the long-time focus on semiconductor scaling now has a partner, diversification, in More than Moore process technologies. More than Moore — encompassing advanced wafer-level and 3D packaging, micro electro mechanical systems (MEMS), and related microelectronics technologies — are harder to roadmap than CMOS technologies. Scaling semiconductor nodes has always offered the combined benefits of faster, cheaper, smaller, lower-power chips (Moore
In a session at Semicon West 2012, Intel’s Alan Allan, International Roadmap Committee (IRC) discussed the evolution of the International Technology Roadmap for Semiconductors (ITRS) front-end process section. “The overriding message for 2012 is that the roadmap has been largely stabilized with the significant changes that were input last year in the 2012 publication,” said Allan, who is part of the committee that puts together the Overall Roadmap Technology Characteristics (ORTC) chapter and the Executive Summary. Large changes are 2013, however, are expected. “In the case of logic, a fairly a significant update and presentation of models has resulted in a structure that drives grand challenges and solutions. That was stabilized in the 2008/2009 timeframe and has served us well for the last couple of cycles. That will be evaluated this year for possibilities of adjustment in 2013,” he said.
More from the ITRS updates:
2012 ITRS update: Back-end packaging and MEMS
Roadmapping More than Moore: When the application matters
He noted that, for the most part, the targets for dimensional scaling and the power/performance management of leading devices, are set primarily by gate length in conjunction with equivalent scaling – things like strain, high-k metal gate and now the new multi-gate FET – which work in combination to manage power and performance.
iSimilarly, In the case of dynamic RAM, aggressive changes were made last year to take into account rapid acceleration of technology in DRAM and flash. “We do a survey every year amongst the members to check on the status as well as the long range driver outlook,” Alan said. “This year, the big change in looking out in time has to do with the 3D layers (i.e., 3D NAND). “We’re stacking up chips inside devices, so there’s 3D mechanical stacking that’s occurring in chips today. What we’re looking for in 2016 is actually the layer stacking of manufactured flash layers that will be as many 8-16 layers of those bits that will begin to be stacked in a process at the chip level. In the future, that’s projected to go up to 128 and 256 layers. You can imagine the ability to have a very high equivalent density in storage on a flash device in that timeframe,” he said. Further work on that is in the roadmap now and options are presented, but that will also be examined going forward for possible changes in 2013. “You can imagine the number of masks increase dramatically and the costs associated with that increase dramatically,” Allan said.
The 450mm transition is also being examined, not only in the domestic USA side with the work in Albany, but the work underway in Europe at imec, to do their similar pathway of 450mm. Allan also emphasized the importance of More-than-Moore, showing a “shopping list” of the things that will be worked on this year that will be delivered at the December Hsinchu Taiwan public conference that kicks off the work for the 2013 roadmap.
Overall, expected changes will be based on work in the logic area, but the surveying and updating of memory and the progress of lithography, which Allan described as significant and progressing. He also noted new work to address max on-chip frequency, which has to be addressed with intrinsic transistor modeling. “Work with Purdue University this year to go from static modeling into the realm of dynamic TCAD modeling that will also be represented publicly,” he said.
One notable change in the roadmap relates to how it is determined that a given technology is in volume production. “The whole point (of the ITRS) is to guide the research and development that prepares suppliers to deliver the early tools, early materials, that can get us into the early production level,” Allan said. “Sometimes a company will be ahead of others in a particular advancement, and they’ll be following a different pathway. That has caused us to rethink the requirement for two companies to be out within a couple of months or six months of each other (to defined HVM). A leading company can be in production with significant volume, and we use that now as the timing, even if the fast followers come along a year or two later, because the supply chain can still count on significant manufacturing opportunity sales for those technologies,” Allan said.
July 12, 2012 — SEMI honored six industry leaders for their outstanding accomplishments in developing standards for the microelectronics and related industries, recognizing the recipients at a reception held during SEMICON West 2012.
The 2012 Karel Urbanek Award, the most prestigious award in the SEMI Standards Program, was awarded to Dr. Tzeng-Yow "Victor" Lin of Industrial Technology Research Institute (ITRI), Taiwan, where he is deputy general director of the Center for Measurement Standards. Lin has been active in SEMI Standards since 2004, jointly leading a petition (with members from Korea) to form the FPD Metrology Committee in 2008, and successfully receiving approval from the SEMI International Standards Committee. Under Lin’s strong leadership, the committee developed and successfully published five new FPD Standards, and seven task forces are now working on topics ranging from 3D Display to Touch-Panels to e-paper. In addition to frequently organizing Standards education programs for new Taiwan members, Lin played a key role in the recent formation of the PV and 3DS-IC Committees in Taiwan, and has led the way in showing other new regions how to get activities started in the Standards Program. A true pioneer, Lin has had a profound impact on the SEMI Standards Program.
North American Standards awards:
This year’s Merit Award was presented to David Busing of KLA-Tencor for his leadership and technical expertise as a member of the Metrics Committee. Last fall, SEMI E10 went through an extensive revision and, as the leader of the E10 Revision Task Force (now part of the Equipment RAMP Metrics Task Force), David was instrumental in successfully completing this project. David clearly demonstrated the necessary commitment, dedication and leadership that revising an ‘industry-critical’ standard such as SEMI E10 required.
The Leadership Award was presented to Chris Moore of Semilab for his outstanding leadership in guiding the SEMI Standards Program. Chris has been a member of the program since 2009 and has been an instrumental part of expanding the SEMI PV Standards portfolio. He spearheaded the PV Minority Carrier lifetime Working Group, which was responsible for the development of SEMI PV9, and led the PV Electrical and Optical properties Measurements Task Force, which published SEMI PV28. Most importantly, as co-chair to both the HB-LED committee and 3DS-IC committees, his expertise and leadership have helped the committees become more effective.
The Honor Award recognized Larry Hartsough of UA Associates for his long standing dedication to the advancement of SEMI Standards. As an active participant in the program, Larry has held numerous leadership positions over the years. He has previously served as chair of the PIC Committee and chaired a task force on utilities, which included interconnects. He currently serves as chair of the ISC Audits and Reviews Subcommittee, and is a Member-at-Large in the North America Regional Standards Committee and the ISC Regulations Subcommittee.
This year’s Corporate Device Member Award was presented to Tom Quinn of Intel. The award is presented to an individual from a device manufacturer, who has demonstrated outstanding contributions to the development of SEMI Standards. Tom, who is co-leader of the 450mm North America and 450mm International Task Forces, has been integral in the development of carrier standards for 450mm wafers. His work has ensured that communication between device manufacturers, equipment and component suppliers in the 450mm arena, is both open and productive. Tom’s leadership and contributions have help command the development of the SEMI E159 and SEMI E162 publications.
The Technical Editor Appreciation Award recognized Alan Crockett of KLA-Tencor. With exceptional writing and editing skills, he drafted several 450mm standards under the PIC Committee, which included the development of technical content, schematics, diagrams and document structure. As part of the North American EHS Committee, Alan worked to develop a new Safety Guideline for robots and load ports and his efforts were published as SEMI S28. Alan’s dedication and meticulous attention to detail has aided SEMI in its ability to provide valuable Safety Guidelines to the industry.
SEMI is a global industry association serving the nano- and microelectronics manufacturing supply chains. The SEMI Standards Program, established in 1973, covers all aspects of microelectronics process equipment and materials, from wafer manufacturing to test, assembly and packaging, in addition to the manufacture of photovoltaics, flat panel displays and micro-electromechanical systems (MEMS). Over 3,700 volunteers worldwide participate in the program, which is made up of 23 global technical committees. Visit www.semi.org/standards for more information about SEMI Standards.
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July 12, 2012 — There’s no doubt that fabless semiconductor companies are taking a keen interest in the semiconductor manufacturing supply chain and processes. To that end, SEMICON West’s Day 2 keynote speaker represented a fabless company: Ivo Bolsens, PhD, SVP and CTO of Xilinx presented on how programmable chips and innovative packaging can advance semiconductors.
Check out insights on the Day 1 keynote from Intel here.
There’s nothing new about the goals of semiconductor designers and manufacturers, Bolsens said, sharing some decade-old slides to make his point. Power density, Moore’s Law, and lowering costs have always been important, and innovation in technology and business models has always generated solutions.
The fabless semiconductor company’s goal is to add value to the system-level design. To do this, Xilinx has taken the approach of device flexibility, paired with 3D interconnection for higher performance/lower power/higher reliability. Bolsens notes that the company is collaborating much earlier with the supply chain and in a much broader fashion than ever before to achieve these goals.
Programmable chips offer flexibility, even while they may appear to have a higher cost than dedicated products. The ability to customize a chip for your functions, and use the same chip across various system-level configurations, leads to costs savings, Bolsens said, referring to time savings as a direct benefit. Logic can also be tuned to accelerate some functions, boosting performance. To save energy, FPGAs offer “fine-grain” programmability.
On the 3D and 2.5D packaging front, Bolsens shared the benefits of using multiple smaller die integrated in one package. Interconnect innovations increase the bandwidth/Watt consumed, and chip yields go up compared to fabricating one large die. When small FPGA die replace a large monolithic die, designers can use “best of breed” die for different functions. Isolation of different blocks also improves.
3D integration and other technology answers for the semiconductor industry’s challenges are in place, summarized Bolsens. Now, the supply chain must build up around them, with supporting information like process development kits (PDKs), design for manufacturing (DFM) rules, and other standardization efforts.
Bolsens recommends creating a continuous supply chain feedback loop while in the early ramp-up of a product, harkening back to his earlier points about collaborating early and often with the ecosystem that will enable your chip to reach market.
Check out Ivo Bolsens’ biography here, courtesy of SEMI.
Check out Solid State Technology’s coverage of SEMICON West 2012!
July 12, 2012 — CEA-Leti co-located its research updates presentation with SEMICON West 2012 in San Francisco, CA, this week. After the talks on device architecture, 3D and 2.5 packaging interconnects, large-scale computing and power consumption, and more, CEA-Leti’s researchers joined Solid State Technology’s digital media editor Meredith Courtemanche to talk about their fields of interest.
Also read: Semicon West Day 1: FDSOI and TSV R&D with CEA-Leti by blogger Michael A. Fury, PhD.
Check out the videos for details on the research:
Hughes Metras, VP of strategic partnerships in North America, presented on cost and energy consumption in large-scale computing, and what technical innovations will meet the industry’s needs. Energy efficiency must improve at the circuit, interconnect, and system level, he said.
Silicon photonics waveguides are one way to significantly increase bandwidth in semiconductors. CEA-Leti is migrating to a 300mm Si photonics line in its research work. Laurent Fulbert, Integrated Photonics Program Manager at CEA-Leti, presented on the question of low-cost/low-power computing architectures, and the answers available in photonics.
Maud Vinet, LETI FDSOI Manager, IBM Alliance, shared the benefits of fully depleted silicon on insulator (FDSOI) transistor architecture. The performance? Excellent parasitic capacitance resistance because of the smaller gate length than bulk CMOS. The energy efficiency? Back bias allows tuning of the devices’ threshold voltage to reduce wasted power. (We cover energy efficiency of new transistors/interconnects in more detail here.) The manufacturing parameters? Easier than a FinFET, Vinet says, as the majority of processes are the same as today’s semiconductor fab methods. The one challenge is potential silicon loss, because planar FDSOI uses thin Si films on the order of a few nanometers.
Mark Scannell and Denis Dutoit both lead 3D interconnect operations at CEA-Leti, with Scannell focused on manufacturing and Dutoit on design. Unfortunately, we did not have time to interview Scannell, though his research is summarized here. The interview below is with Dutoit. Leti has both a 200mm and 300mm line for wafer-level 3D packaging research. 2.5D passive interposers and 3D active stacks are “cousins” in device packaging, and you will see both of them used for different purposes for quite some time. While both 3D and 2.5D technologies can appear in the same package, the supply/value chains for each technology are quite different.
What’s in store in this area? “Smart” interposers are being developed with integrated passives on the interposer. 3D partitioning is enabling scaling as you like it — preventing chips from being held back to a larger device node by one of the blocks involved. Also on the horizon is via-last through silicon vias (TSV), an old technology that could now come back to offer continued TSV diameter scaling past what via-middle architectures can provide. The enabling technology here is permanent bonding. Also on CEA-Leti’s agenda is direct bonding, which spreads the stress gradient over the entire copper daisy chain, unlike today’s TSVs, and has a lower contact resistance. Finally, the researchers are considering sequential or monolithic 3D to make 50nm stacked structures on a wafer.
Before the meeting ended, Laurent Malier, CEO of Leti, spoke with Solid State Technology about the research organization’s current goals.
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July 12, 2012 — Barclays Capital is seeing various reasons for a Q3 2012 semiconductor fab order/shipment pull-back, following meetings around SEMICON West 2012 this week.
Barclays expects that TSMC’s pushout of its Fab 14 phase 2 caused Applied Materials to lower its revenue forecast for front-end semiconductor tools. Despite well-known shortages at 28nm for Qualcomm (QCOM), Nvidia (NVDA), AMD, and other chip suppliers, TSMC is likely hesitant to add capacity until it improves its 28nm high-k metal gate (HKMG) yields. Barclays interprets this situation as leaving lithography and process control orders intact, while more capacity driven players would see a delay. Other factors in the Q3 lull include a retrofit at Samsung’s Austin fab and a modest pushout at Fab 16.
Read more analysis on the Q3 dip from Citi here.
The “air-pocket” emphasized by AMAT and other front-end names was largely corroborated by the subsystem players, Barclays reports.
A combination of optimism on increasing capital intensity, foundry competition, and 14nm Intel and 20nm foundry investments are contributing to optimism about Q4 orders, and a solid capex year in 2013, Barclays analysts report. Therefore, the Q3 pause is seen as a typical seasonal — not cyclical — lull.
Read the full report at http://live.barcap.com/PRC/servlets/dv.search?contentPubID=FC1838098&bcllink=decode.
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July 12, 2012 — After meeting with various semiconductor manufacturing tool suppliers — Applied Materials, KLA-Tencor, Lam Research, Tokyo Electron, Teradyne and Cymer — at SEMICON West, Terence Whalen, semiconductor equipment sector analyst, Citi and colleagues share impressions on foundry spending plans and tool choices.
Whalen observes that Applied Materials (AMAT) expects a large ($500 million) H2 2012 foundry pushback, lowering its Q3 guidance to the bottom of its range, while other tool suppliers report virtually no change to their foundry customers’ plans. There is no change to TSMC’s aggregate 2012 capacity plan that Citi’s taiwan semiconductor analyst Roland Shu could find, though minor shifts in critical layer configurations could (at least partially) explain how AMAT could see weakness not experienced by other vendors.
Speculation has been “markedly negative” on H2 2012 semiconductor demand, Citi says, including talk of NAND capitulation, skepticism that foundry might weaken, and questions on whether Intel might reduce its blockbuster capex. Meetings at SEMICON West are largely confirming tool suppliers’ suspicions that there will be weak orders in Q3, picking up in Q4. Part of 3Q’s weakness may be amplified by heightened seasonality that arises given higher customer concentration, Whalen says. However, Citi accepts the potential for improving semiconductor demand into Q3, which might strengthen capex in Q4.
Foundry orders will rebound sooner in H2 2012 than NAND, which see increases in H1 2013, Citi predicts. Based on its interviews with Lam Research and others, Citi expects flat or slightly better foundry capex in 2013, driven by steady 28nm deployments.
Some notes on equipment trends:
Read more from Whalen at http://ir.citi.com/%2BnkGI0K%2BGgl2DqdhefgsTRHbYsIMp6NZjGciK%2FrzUDc%3D
Check out Solid State Technology’s coverage of SEMICON West 2012!