Category Archives: Semicon West

July 12, 2012 — Day 2 of Semicon West 2012 began a bit earlier than usual with the Sokudo Lithography Breakfast Forum, which focused on directed self-assembly (DSA). The first question was anticipated by Atsushi Yasue, emcee and CTO of Sokudo, who opened his remarks with “Is DSA just an interesting science project?” Given that Sokudo is introducing its Duo dual track product for DSA, I suspect he believes it is more than that.

Michael Garner, chairman of the ITRS emerging nanotechnology group, opened the technical sessions with the ITRS view of DSA. DSA was first identified as a potential lithography extension in 2007; in 2011, SPIE conferences included several presentations on evidence of DSA defect reduction. Progress has been made, though defects are still unacceptable at the 100ppm level. A brainstorming session at SPIE 2012 recommended specific topics for university and consortium pre-competitive research activity.

Yoshi Hishiro of JSR Micro has been working on DSA polymer blends and applications for several years already, both block copolymers and polymer blend systems. One specific application is contact hold shrink, which includes one method that can be used in combination with EUV. Contact hole repair, making features uniform and round, is another activity with strong customer pull. A patterning doubling method allows extension of a rectilinear grid of contact holes to a staggered grid with twice the density. Clearly, design objectives are constrained to a menu of what DSA is capable of delivering.

Serge Tedesco of CEA Leti described the IDeAL program at Leti, opening his presentation that included the characterization of DSA for microelectronics using block copolymers as an “easy process” with “low cost.” The number of SPIE DSA papers grew from 5 to 25 to 55 in 2010-2011-2012. The Leti 300mm pilot line has demonstrated 100nm contact hole shrink to 15nm, but CD and defect metrology is a challenge. He believes DSA could be inserted as a complementary lithography technique as early as the 14nm node.

Steve Renwick of the Imaging Solutions Technology Development group at Nikon gave a hardware perspective on DSA with 193nm immersion lithography. From his world view, these DSA materials actually want to do what we want them to do, irrespective of the hardware optics. Rather than a competitor, DSA is a high potential complement to 193i litho. Demonstrations have been executed showing that DSA is capable of healing print defects in the pattern, because DSA wants to form the target structures. Because of the commercial implementation of double patterning, litho tools are already capable of meeting the overlay requirements of 2-3 nm required for some DSA applications. Given the successes already demonstrated, he believes DSA will indeed fly as a complement to 193i.

Charles Pieczulewski of Sokudo spoke on the path to defect free manufacturing with DSA. Pilot development activity began five years ago on the existing RF3 track, and has evolved to the new Duo track that is designed specifically for DSA. Development studies included work to determine the pre-pattern CD range that was required to reduce the DSA defect density, those defects ranging from single dislocations to gross pattern randomization. One study on defect characterization for a contact hole shrink application encompassed 550,000,000 vias; this is why we have graduate students. They found 22 missing vias, 8 due to particle contamination and only 14 due to poor DSA phase separation. The student’s leopard hallucinations are subsiding. Additional DSA tracks will move into pilot production now through 2013, with HVM tools to start shipping in 2014.

Linda He Yi of Stanford U (student of H.-S. Phillip Wong) opened her remarks with the observation that long-range order is not required for chip manufacturing. Rather, the objective can be altered to place specific patterns in specific locations of limited area. One can create a template for each individual feature to be created with DSA; or in this approach, multiple DSA features can be fabricated with a library of templates that can be used repeatedly to generate, in effect, ‘random’ design features. The benefit of such a library is a relaxation of resolution requirements for the template patterning. Once again, DSA is found to heal defects in the litho patterns. By the way, Linda is the lucky grad student who got to inspect the 550,000,000 vias cited above.

The NCCAVS CMPUG staged its 5th annual meeting concurrent with Semicon West, this year returning to a separate room rather than being held on the show floor where the seats are too few and the decibels are too many. As always, the CMPUG presentations will be posted on the NCCAVS CMPUG website in the coming week or so.

The first speaker was yours truly, Michael Fury of the Techcet Group, providing the annual CMP consumables market update. Pad & Slurry revenues are up 3% over 2010, with a 2012 forecast up 5.7% to $1.73B. Combined with pad conditioners, PCMP cleaners, PVA brushes and slurry filters, the CMP consumables business achieved a $2.04B milestone in 2011.

Iqbal Ali of SEMATECH @ Albany updated us on the status of CMP’s role in 3D TSV activities there. The TSV story remains primarily a copper CMP market from this group’s perspective, but the demands for removal rate of thick copper, planarity of large features (compared to on-chip interconnects), and selectivity to different materials demands unique CMP products and processes if TSV is to be successful in HVM. SEMATECH has been working with Cabot Micro and Air Products to develop a working backside reveal process for copper CMP and alkaline post-clean (CP98-D) that keeps cross-contamination of the exposed silicon under control, as quantified by the Qcept ChemetriQ tool.

Paul Feeney of Axus Technology took us back to the future with a discussion of polishing non-uniformity, beginning with the use of multi-wafer templates by the Cro-Magnon. Polishing heads are currently being designed with 8 zone control and ≤2mm edge exclusion. Migration to 450mm will exacerbate the center-to-edge depletion of slurry reactants and the temperature differential between the wafer leading and trailing edge, which drives reaction kinetics. The 54nm Cu line widths scheduled for production in 2013 will struggle with Cu losses due to the combined effects of non-uniformity, imperfect selectivity, and edge roll-off. Polishing head upgrades for 200mm and even 150mm wafer polishers are still in demand by smaller fabs and research labs for achieving state-of-the-art performance on retro platforms. You know, the kind found in cave drawings.

Mike Corbett of Linx Consulting talked about the impact of the now-inevitable 450mm conversion on CMP consumables. CMOS wafer starts drive the CMP market, and this segment is lagging the overall chip market. The Linx slurry & pad market estimate is $1.615B for 2011. The supplier consolidation index used by the US Department of Justice indicates that confirms the expectation that tungsten slurry is highly consolidated, though not to the extent of monopoly, while the other slurry segments are well diversified with a balance between suppliers from the US and Japan. Fab projections foretell a peak in 300mm wafer production in 2021, with 450mm starting to scale to high volume production in 2018. By 2025, the MSI (millions of square inches) of silicon processed in 450mm will cross over and exceed the 300mm production. Slurry & pad costs are projected to increase 35-50% per wafer, depending on the actual increase in slurry flow rate (used 1.2x to 1.5x) needed to achieve process specs.

Michael Fury, speaking this time as Vantage Technology, presented several tales from the sub-fab, describing the kinds of anomalies that have been observed in customer slurry distribution lines around the world using the continuous monitoring capability of the SlurryScope. Monitoring large particle counts for post-mortem diagnosis of wafer scratching incidents is useful for understanding and for future-looking corrective actions, but that is only part of the story. Monitoring particle behavior continuously teaches the patterns of drifts and spikes in the slurry supply, making it possible to learn the special causes associated with each type of behavior observed, eliminate those causes, and actually prevent slurry-induced scratching incidents with stable line performance.

Bruce Kellerman of MEMC talked about the 450mm transition from the wafer manufacturers’ point of view. The arguments supporting the 450mm transition parallel those for the 300mm transition, though the number of players that are both able and willing to afford it is dwindling. Siltronic, Sumco and MEMC have all announced workforce and facility reductions in the past 8 months. From over 20 wafer producers at 150mm, we are down to 6 suppliers at 300mm; Bruce used “?” for the count at 450mm, but all presently have active 450mm programs in place. That doesn’t mean all will remain viable, especially given the small number of fab customers. Intel, Samsung and TSMC are pretty much guaranteed customers, but even they have divergent specs. To get costs in line, a greater degree of standardization across fab customers is required.

While I do appreciate the relative quiet and sanity of holding this CMPUG meeting in a separate room away from the show floor, I realize now that the penalty we paid is that we had no access to the Happy Hour that started on the show floor two hours before we concluded our business. When people talk about CMP placing unreasonable demands on people, this is what they’re talking about.

Michael A. Fury is director and senior technology analyst, Techcet Group and a regular contributor to Solid State Technology. Read his reports from the Gartner/SEMI forecast meetings, and from CEA-Leti’s research presentations.

July 11, 2012 — Solid State Technology and SEMI announced the Best of West Award winner — Jordan Valley Semiconductor — during SEMICON West today. Jordan Valley Semiconductor’s QC-TT defect inspection system garnered the award for its ability to predict breakage in 450mm wafers, which are subject to more handling steps and more thermal stresses due to their larger size.

The award recognizes important product and technology developments in the microelectronics supply chain and is presented to a qualifying exhibitor at SEMICON West, the largest and most influential microelectronics exposition in North America. Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

Jordan Valley Semiconductor’s QC-TT predicts damage on 450mm wafers in the semiconductor manufacturing environment, and can identify slip and other crystalline defects in wafers. These defects can contribute to lower yields.

Best of West is determined by a prestigious panel of judges representing a broad spectrum of the microelectronics industry.

450mm is a major topic at the show, with Intel and ASML announcing an investment relationship to fund 450mm/EUV lithography development, as well as a host of new products. Also read: The elephant has left the room — 450mm is a go!

SEMI is a global industry association serving the nano- and microelectronic manufacturing supply chains. For more information, visit http://www.semi.org.

PennWell Corporation is a diversified business-to-business media and information company that provides quality content and integrated marketing solutions for diverse industries, including Solid State Technology for the microelectronics manufacturing sector. Learn more at www.solid-state.com.

Check out Solid State Technology’s coverage of SEMICON West 2012!

July 11, 2012 — At the opening keynote of SEMICON West, Shekhar Borkar, Intel Fellow and director of extreme electronics for the company, presented on ubiquitous computing and the link from ultra high performance computing to handheld devices. He shared developments on power and energy reductions, coupled with increasing semiconductor performance.

In this video interview, Borkar shares some key topics from his presentation: Near-threshold voltage transistor designs, 3D integration for DRAM, unconventional interconnect, and more. Borkar speaks with digital media editor Meredith Courtemanche.

Get deeper into Borkar’s presentation topic in Courtemanche’s blog from the event, The energy behind energy at SEMICON West

 

 

Check out Solid State Technology

July 11, 2012 — Citi analysts surveyed the light-emitting diode (LED) manufacturing market and LED demand at SEMICON West 2012, taking place this week at the Moscone Center in San Francisco, CA.

Demand for general lighting applications remains robust for LEDs, though the LED oversupply remains significant. This could explain why orders for metal organic chemical vapor deposition (MOCVD) tools have ticked slightly higher, but primarily limited to Epistar and some small China orders.

From a chip perspective, discussions suggest Cree (NASDAQ:CREE) stepped on some large customers toes when it acquired Ruud Lighting in August 2011. Ruud makes outdoor lighting fixtures based on LEDs. This has had greater than expected negative impact on chip demand, Citi says. The downstream acquisition for the LED maker is viewed by some customers as directly competitive with their businesses.

View Citi’s full report at http://ir.citi.com/uyRtd8u%2B6M2pDF7aCZQyUr4RBK2BMqjLd6ziy8f56t2Ci20uJjgV%2Bg%3D%3D

Visit the LED Manufacturing Channel on Solid State Technology and subscribe to the LED Manufacturing News monthly e-newsletter!

July 11, 2012 — Barclays Capital analysts share observations from meetings with semiconductor manufacturing tool suppliers at SEMICON West, noting the enthusiasm and concrete deals around extreme ultraviolet (EUV) lithography and transitioning to the 450mm wafer size.

The focus for the long-term industry outlook was on EUVL and 450mm, with Intel clearly all about 450mm and everyone else in the industry intent on making EUV litho work, Barclays reports.

The R&D funds to be given to ASML for EUV development will not accelerate the roadmap between now and 2015, which points to more focus on the next generation of tools. ASML remains in the catbird seat in terms of the key drivers behind staying on Moore’s Law: EUV lithography and 450mm wafers. Also read: The Elephant Has Left the Room — 450 mm is a Go! by blogger Dick James, Chipworks.

Barclays also noted that Cymer’s (CYMI) leadership in the lithography light source sector is becoming increasingly more entrenched.

Read Barclay’s full Day 1, SEMICON West, report at http://live.barcap.com/PRC/servlets/dv.search?contentPubID=FC1837768&bcllink=decode

Check out Solid State Technology’s coverage of SEMICON West 2012!

July 11, 2012 — Day 1 of Semicon West 2012 opened under brighter skies than we had yesterday, when speakers at the SEMI/Gartner market symposium from Portland, of all places, made fun of the gloomy skies over my beloved San Francisco. I don’t think our skies will ever compare to Portland — and I mean that in a good way (for San Francisco…). The Semicon show floor is more spacious than it was a decade ago, with wider aisles, more presentation stages, and fewer pieces of large equipment. And for the first time in several years, Novellus is not doing its own thing in the Yerba Buena Center for the Arts, which still sports its permanent (so far…) Novellus Theater sign.

CEA Leti sponsored an early evening symposium at the W Hotel for almost 200 attendees. Among the fastest computers in the world is an installation in Berkeley that runs up to 16 PFLOPS/sec, requiring 8MW of power. Linear projections for a 1 EFLOP/sec system in the planning phase would require an unmanageable 600MW. Power management is becoming an industry in its own right. Several global data centers have been announced in Scandinavia to allow the climate to contribute to the cooling effort. I anticipate a shift for Santa from toys to virtual games in cloud computing.

Maud Vinet, one of Leti’s resident researchers at U Albany, gave the current status of their work in fully depleted SOI (FDSOI) device architecture, in which they have been engaged for 15 years since the spin out of SOITEC. This is being extended below 20nm, still in a planar device configuration.

A pair of talks reviewed Leti’s involvement in TSV and related 2.5D and 3D integration. One slide was shown with Leti’s first TSV demonstration in 1988, suggesting once again that nothing is new if you know who has the original photographs. While via-middle processing is the current norm, Leti believes that via-last with permanent bonding can be used to bring via diameter down to 3µm, though it may be limited to IDMs and memory applications due to its interdependence with design.

Integration of photonics on chip is another focus area for Leti, motivated by the fact that as much as 80% of the bottlenecks that the zettabytes (zetta = 1021) of data encounter every year occur within the data centers themselves. Since we’re expected to be into the yottabyte (1024) range by 2020, replacing electrons and copper with photons is an idea whose time is too close for comfort. We’re also going to need more prefixes for 1027 and beyond. The world runs on a lot of data, though I maintain that Fox News remains a notable exception.

The presentations were followed by hors d’oeuvres and a champagne bar stocked with — and this is the ironic part — California champagne. I sense a lost branding opportunity for our colleagues from Grenoble.

Best Semicon show give away ever: my sole nominee in this category is the Schott Glass shot glass, a very stylish piece of barware with a generous 2 ounce pour. Kudos!!

Michael A. Fury is a contributing blogger for Solid State Technology and director and senior technology analyst, Techcet Group.

Read his report from SEMI’s press conference and the SEMI/Gartner Market Symposium.

Read more about CEA-Leti’s talks in digital media editor Meredith Courtemanche’s The energy behind energy at SEMICON West

July 10, 2012 — Imec Technology Forum (ITF) took place just before SEMICON West 2012 opened in San Francisco, CA. ITF, held at the Marriott Marquis, focused on advanced semiconductor architectures and process technologies, with an additional impetus placed on the healthcare/medical industry.

Luc Van den hove, president and CEO, imec, spoke with Solid State Technology’s digital media editor, Meredith Courtemanche, covering imec’s major announcements and research presentations to take place during SEMICON West 2012. Summaries of imec’s presentations follow the video.

 

 

Logic

To enhance the advanced metal-high-k gate stack for next-generation logic devices, imec successfully demonstrated higher-k dielectric with Replacement Metal Gate (Metal-Gate-Last) transistors that achieved 200-1000x reduction in gate leakage relative to leading-edge logic devices in the industry with HfO2 high-k gate dielectric. To address the process control and scalability of the replacement metal gate for nano-scale devices, imec achieved tight electrical distribution down to 20nm gate length through detailed process optimizations. By providing fundamental insights into work-function influences due to metal intermixing in aggressively-scaled metal gates, imec’s research addresses an important source of variability in advanced transistors.

Imec has also invested significant effort in the development of 3D FinFET devices and high-k metal gate over the last 10 years.  In the 14nm platform, these features will be combined with the next generation of stress engineering. For the next node — 10nm — we will replace the silicon channel in the FinFET devices with high-mobility materials. And for the nodes beyond 10nm, we are evaluating two possible device routes: tunnelFETs and junction-less nanowires.

 

Memory

In NAND Flash memory, imec further develops hybrid floating gate architecture, scaling this architecture to 15nm and beyond. Beyond 10nm, the main emerging technology is resistive RAM (RRAM). We’ve made significant progress on RRAM: imec recently announced 10nm functional RRAM, made significant improvements in performance and reliability of RRAM cells by process improvements and clever stack-engineering, and increased fundamental understanding of RRAM process technology. 

In DRAM memory, imec is helping to scale MIMcap technology with a focus on materials. Beyond MIMcap, SST-MRAM is the leading candidate on the industry’s emerging DRAM roadmaps. Therefore, in November 2011, imec launched a program on SST-MRAM, for stand-alone DRAM as well as replacement of embedded SRAM.

 

Advanced lithography

To enable further scaling, imec is focusing on the extreme ultraviolet (EUV) lithography pre-production readiness and on extending immersion lithography using advanced patterning integration schemes. To further push the limits of 193nm immersion lithography and overcome some of the critical concerns for EUV lithography, imec implemented 300mm fab-compatible Directed Self-Assembly (DSA) process line all-under-one-roof in imec’s 300mm cleanroom fab. Imec’s DSA collaboration aims to address the critical hurdles to take DSA from the academic lab-scale environment into high-volume manufacturing.

 

Interconnects

The focus of imec’s nano-interconnect program is technology scaling including materials, process, integration, reliability and system aspects.

Imec is investigating half pitch (hp) multiple patterning techniques in combination with immersion lithography, and EUV lithography with single or double patterning techniques.

To improve the mechanical stability and low-damage patterning and integration schemes to reduce the k value, imec studies post-deposition techniques and the impact on performance and reliability.

To avoid wire resistance increase, imec explores metallization using new barrier and seed materials as well as novel deposition and filling techniques such as manganese and ruthenium based metallization, atomic layer deposition and chemical vapor deposition techniques.

 

3D integration

3D integration enables system scaling through 3D chip stacking with through-silicon-vias. Imec’s 3D integration processes are completely executed on 300mm. All processes and flows are tested on functional circuit demonstration vehicles. As part of the INSITE program, imec proposes flows for modeling, simulation, design and testing of 3D systems.

 

14nm, FinFETs

Imec’s early-version PDK (process development kit) for 14nm logic chips is the industry’s first to address the 14nm technology node. It targets the introduction of a number of new key technologies, such as FinFET technology and EUV lithography. With this PDK release, imec leads the way to an industry-standard 14nm PDK. In addition, the PDK anticipates the introduction of a number of new technologies at the 14nm node. The main example is the use of FinFET transistors, which have a larger drive per unit footprint and higher performance at low supply voltages compared to the traditional planar technologies. Evolutions of this PDK will gradually also introduce the use of high-mobility channel materials. The PDK includes elements of both immersion- and EUV lithography, opening the way for a gradual transition from 193nm immersion to EUV lithography.

 

Optical I/O

Future systems will become increasingly dependent on a high input/output bandwidth. Not only between systems, but also between the chips in a system, or even between the cores on a chip.

With optical components, it is possible to build interconnects that have the required bandwidth without consuming more power. Silicon photonics allows fabricating optical components with state-of-the-art semiconductor equipment, using the same processes and tools as for the fabrication of state-of-the-art chips.

At Semicon West, imec will announce the first important results of its industrial affiliation program (IIAP) on high-bandwidth optical input/output. This program is working towards a manufacturable solution for achieving high-bandwidth communication by modeling and engineering optical solutions for high-bandwidth communication between CMOS chips.

Check out Solid State Technology’s coverage of SEMICON West 2012!

July 10, 2012 – GLOBE NEWSWIRE — ATMI, Inc. (Nasdaq:ATMI) introduced BrightPak, its next-generation liquid containment and delivery system for high-value liquid material transfers during advanced photolithography processes in semiconductor, flat panel display (FPD), and light-emitting diode (LED) manufacturing.

BrightPak bottle systems are created first as a small plastic pre-form that includes both an external overpack and an internal ‘hard’ or rigid liner. It is then blow-molded into a larger bottle form with a capacity of just under five liters. The final product is a double-containment bottle system with a rigid, yet collapsible, interior liner. With its advanced design, the BrightPak bottle system offers approximately 21% additional volume compared to the typical one-gallon glass bottle used in lithography applications today. In fact, BrightPak bottles allow this higher fill volume without impacting the customer’s labeling surface, the handle location or the physical dimension of the chemical cabinet.

From filling and shipping to storing and dispensing, the system’s double-containment design and materials of construction deliver exceptional chemical protection from environmental factors, as well as accidents and operator errors. Unlike glass bottles, BrightPak bottles are made from shatterproof materials and will not easily break if dropped, especially when filled. The ergonomic design of the bottle and handle allows for easy and safe operator handling. The bottle shape, connectors and diptube were designed together for superior material delivery with an optimum utilization.

"We are offering the industry much-improved benefits with our new BrightPak systems and we’re working to make the transition as easy as possible," commented Garth Su, ATMI’s senior director of the packaging business group and global product marketing. "All BrightPak systems work with connectors for widely used glass bottle systems, as well as existing ATMI connectors and caps. Of course, that includes our misconnect prevention capability to eliminate human connection errors."

BrightPak systems are cleanroom-manufactured, particle certified and provide superior chemical protection from UV light exposure. Moreover, the wetted surface is made of high-purity, chemical-resistant materials. BrightPak systems also offer improved flexibility for customers looking for both pump-enabled and pressure-dispense solutions. The rigid, collapsible liner provides improved isolation of drive gas when pressure is applied between the liner and overpack. This creates a safer environment for the materials that can help reduce the formation of micro-bubbles and other defects. BrightPak systems are also cost-effective, providing utilization rates of up to 99.9% of filled product which minimizes product waste. In addition, the system’s small footprint can help free-up facility space and its light weight can reduce shipping costs. BrightPak overpacks are recyclable and the interior rigid liners are more disposable-friendly, yielding a much smaller carbon footprint than glass bottles.

ATMI is exhibiting at SEMICON West, July 10-12 in San Francisco, Moscone Center, South Hall, Booth 2446.

ATMI Inc. provides specialty semiconductor materials, and safe, high-purity materials handling and delivery solutions designed to increase process efficiencies for the worldwide semiconductor, flat panel, and life sciences industries. For more information, please visit http://www.atmi.com.

Check out Solid State Technology’s coverage of SEMICON West 2012!