August 12, 2011 — Laurent Malier, CEO of Leti, described the research group’s work and the outlook on fully depleted silicon on insulator (FDSOI), 3D packaging technologies, and integrated photonics on silicon (Si photonics), in a video interview at SEMICON West 2011.
Malier says performance data at 22nm shows FDSOI is comparable to FinFET with respect to the speed gain and low power performance. FDSOI technology is also easily manufactured and it’s ready for scale down to 11nm, Malier notes.
August 11, 2011 – At SEMICON West 2011, Henkel announced a silver sintering material that requires no pressure. The technology enables high-volume production of modem power packages. "Without having to do the pressure and heat process, you can change your units per hour from 30 up to 6000," said Doug Dixon, global marketing communications director at Henkel, in a video interview at the conference. The company has designed this new process into its Ablestik SSP2000, a high-reliability die attach material well-suited for use with power modules such as IGBTs and high power LED products.
Also at SEMICON West, Henkel announced jointly with STMicroelectonics, that the performance of Henkel’s conductive die attach films (Ablestik C100) was validated for production of very small package configurations in a process called ScalPack, which incorporates die with extremely small dimensions. The company commercialized these materials in early 2011.
The new process eliminates the die fillet, and as such, it enables greater design latitude and process capability, noted Dixon in the video interview. A lower bond line thickness is the result and without the fillet, "the die can be the exact same size as the die pad, so the design capabilities are limitless," said Dixon.
August 11, 2011 — In these 2 video interviews from SEMICON West 2011, ESI technologists John Sabol and Vernon Cooke discuss what LED chips require on the back-end manufacturing line, starting at wafer scribing and moving on through test. LEDs differ from semiconductor chips — high light extraction is a major goal, for example — though some goals — high yields and low costs — remain universal.
Wafer scribing for brighter LEDs
John Sabol of ESI talks about wafer scribing for LEDs. The LED industry is working on increasing quantum well efficiencies and light extraction. ESI focused on the latter in developing tools for scribing patterned sapphire wafers and distributed Bragg and metal mirrors.
LED scribing cuts LED wafers into die, going through layers of gold, sapphire, GaN, and other materials. By paying attention to sidewall construction during this cut, ESI was able to integrate a laser cutting technology that keeps light output high.
Handling LED packages for better throughput and yields
Vernon Cooke, ESI, covers the company’s new light emitting diode (LED) manufacturing technologies, focusing on advanced packaging test tools and handling systems. "The back-end process of packaged LEDs equates to about 60% of the total cost of LED manufacturing," Cooke notes.
ESI sees lowering the cost of handling, testing, and binning LEDs as a major goal. Multi-track handling doubles throughput for LED testing. Handling without device damage is also important. Ceramic packages with delicate lenses require different handling methods than standard chips. A nested carrier brings the LED through processes in a protected manner. Equipment toolsets for LEDs must be flexible, Cooke adds, seeing many package sizes and designs for LEDs.
Standardization should occur in the end-product luminaire, Cooke believes, which he says will push standardization back up the manufacturing and interconnect chain.
August 11, 2011 – Qcept Technologies’ non-visual defect (NVD) inspection technology is being used by advanced logic, memory, and analog IC manufacturers. In a video interview at SEMICON West 2011, Qcept EVP Robert Newcomb discussed the differing end user needs with respect to inspection challenges. There are two types of customers, explained Newcomb, those on the leading edge where the focus is on new materials, yield and how they can drive yield improvements from ramp up to high-volume production. And then there are the mainstream fabs (i.e., traditional 200mm fabs and mainstream 300mm fabs) that are yielding at high rates, and though they are always looking to improve yield, these fabs are looking for ways to reduce costs, have more eco-friendly processes, and getting a better overall mix of yield/cost benefit as they generate analog products on older processes.
As the industry goes from 22nm and below, Newcomb noted that defectivity issues are being driven by low-k dielectrics getting thinner, high-k/metal gate processes, and immersion lithography. "NVDs are impacting integration schemes and yield programs," said Newcomb, "and these will become even more prevalent at 22nm, especially with advanced architectures." Amid the challenges, Qcept Technologies as a company believes that it has to find creative ways to partner with both equipment suppliers and device manufacturers.
August 11, 2011 – Scott Zafiropoulo, VP of marketing at Ultratech, explains the company’s business and positioning strategies in an interview at SEMICON West 2011. With laser annealing tools (40nm and below), and lithography systems for advanced packaging and LED development (2-in. up to 8in.), the company’s markets are not in the same cyclicality of the industry, noted Zafiropoulo. "We are able to weather the storms a little better," he said, "and being in multiple markets has allowed the company to balance itself better." The company believes its strategy is paying off as evidenced by it revenue growth and acceptance of its technology on the part of leading-edge users.
Going forward, Zafiropoulo expressed confidence in the company’s ability to meet the challenge of 450mm wafer manufacturing — a mechanical task involving the scanning stage of litho equipment.
August 10, 2011 – Ron Huemoeller, SVP of advanced 3D interconnects at Amkor, participated in two panels at SEMICON West 2011: 2.5D silicon interposer packaging technologies and supply chain, and 3D packaging technology and the ecosystem. He shared his thoughts on the panel topics during a video interview at the show.
Among the issues Huemoeller sought to emphasize via the 2.5D panel is the importance of silicon interposers, the timeline with respect to their integration, and the assembly and supply constraint challenges. With respect to the latter, he said the industry is suffering from a lack of supply on the part of interposers, which could negatively impact the industry with respect to product timing and the release of products. Furthermore, there are hand-off issues that take place from the interposer side to assemblers (e.g., chip/package interactions).
In going from 2.5D to 3D packaging technology, Huemoeller explained that the industry needs to have the right design tools in place, i.e., EDA tool sets and the software. Still another challenge is the thermal issues that emerge when stacking die. "The 3D sector has not addressed these thermal issues," he said, whereas, "the 2.5D sector has addressed these nicely." A second problem is how cost will affect the dovetailing of products into one to meet customer timing requirements. He anticipates that 2.5D technology will remain in play for a long period of time. 3D technology should start to come into play with the smart phone sector, followed by larger die sector/higher power applications in the latter part of this decade. "[3D] probably won’t be fully adopted until 2019/2010, primarily because of the software issues," he said.
August 10, 2011 – Post-22nm and below, the industry is going to fully depleted structures, either FinFETs or fully-depleted planar SOI (FDSOI), explained Steve Longoria, SVP, global strategic business development at Soitec, in an interview at SEMICON West 2011. Although Soitec supplies wafers for both structures, the company has introduced a new wafer — extreme SOI — with a thin buried oxide that is used for planar FDSOI. According to an IC Knowledge paper cited by Longoria during the interview, the new technology delivers superior power performance and is cost-competitive with bulk technology. All the major fabless companies and foundries have initiated programs to evaluate the technology, he noted, which Soitec believes is an alternative for 22nm and below.
In a partnership with IBM and ARM, the company was able to demonstrate two different variants: a 30% performance advantage at the same voltage, or a 40% power savings at the same performance. The company leveraged its Smart Cut technology to build the thin buried oxide, and is working with its partners to develop the transistor on top of it. According to Longoria, the development is straightforward because it’s a continuation of a planar transistor. "So it’s evolutionary and straightforward from both a process design standpoint and a manufacturing standpoint," he said. "It’s a much lower risk in the industry for both the designer and the manufacturers than the alternatives."
The company is producing prototypes of extreme SOI now, and providing manufacturing samples on the order of thousands of wafers a month to all the development facilities. "We are in position [between the company’s factories in Singapore and France] to be fully qualified by the end of this year, and our close partnership with SEH in Japan will enable millions of wafers to be supplied over the next couple years," reported Longoria. He said the company is well positioned to meet both the quality and specifications and the volume manufacturing with FDSOI or extreme SOI going forward. "Research suggests we can thin the buried oxide down even more and have scalability well below 14nm, maybe even 11nm — enabling scaling of a planar device, which is going to put the industry in a position to move even faster."
August 10, 2011 – Gigaphoton expects to deliver an EUV source to ASML at the beginning of 2012. In the meantime, the company is focusing on throughput, conversion efficiency, and debris mitigation with its EUV source. Phil Alibrandi, director of sales at the company, summarized the activities taking place to support these efforts in a video interview at SEMICON West 2011.
For example, by using superconducting magnets, ions can be moved away from the collector mirror, thereby avoiding mirror damage. The goal is to make the mirror last a year. The company has also been able to achieve a removal of ~92% of ions from the collector mirror, leaving only about 7% of ions to be swept away by the etch gas used to keep the collector mirror clean in the EUV source. With a conversion efficiency above 3, "this is perhaps some of the best results seen to date," said Alibrandi. "But the industry’s target is 5 and everyone has a long way to go." The company considers that its pre-pulse, debris mitigation and other improvements, could make this a very economical option in a couple of years.
In the interview, Alibrandi also discussed the status of the company’s DUV technology milestones. Smart diagnostics (where the laser self-corrects its own parameters) and focused drilling (a way to get better yield at the contact layer) are improvements that, with others, can extend the technology another generation until EUV is ready to go, he said.
August 9, 2011 – As IC manufacturers go from 28nm to more advanced nodes, they also become more aggressive with strain engineering, explains Jeff Hebb, VP of laser product marketing at Ultratech, in a video interview with Solid State Technology at SEMICON West 2011. SiGe, for example, is introduced into the channel of PMOS transistors to get better performance as the industry goes from 28nm, to 20nm and then to 14nm.
"For millisecond annealing to be compatible with aggressive strain engineering, you cannot introduce extra wafer warpage," said Hebb, "because this introduces photolithography overlay errors." The company’s new LSA system (LSA101) uses shorter dwell times so that dislocations in the wafer do not have time to form and nucleate. On a macro scale, this means the wafer warps much less at the shorter dwell times so it is possible to maintain higher temperatures during millisecond laser annealing. The company’s LSA101 system, with a reduced dwell time of 200
August 9, 2011 – Doug Anberg, VP of advanced stepper technology at Ultratech, discussed the physics behind cost-of-ownership (CoO) improvements in the company’s new Sapphire 100E HB-LED tool in a video interview at SEMICON West 2011. With a low NA, good DoF, and the resolution required for HBLED applications, the 1X projection lithography tool eliminates the consumable costs (for masks) associated with contact aligners because the masks don’t contact the wafer.
Anberg noted that the company is seeing good acceptance of the new tool for layers called patterned sapphire substrates (PSS), and for the pad layer associated with the current spreading finger area (see figure below). The current spreading finger area needs reduced feature sizes to achieve good CD control and good lithographic performance, said Anberg. These attributes are key to obtaining more light output from the LED, especially for high-power devices used in solid-state lighting applications.
Performance considerations for HB-LED applications. (Source: Ultratech)
