Category Archives: Semiconductors

Solid State Technology and SEMI announced the recipient of the 2013 “Best of West” Award — Mentor Graphics — for its Tessent TestKompress with Cell-Aware ATPG.  The award recognizes important product and technology developments in the microelectronics supply chain. Held in conjunction with SEMICON West, the largest and most influential microelectronics exposition in North America, the Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

The Mentor Graphics Tessent TestKompress with Cell-Aware ATPG significantly improves on the standard process for testing digital integrated circuits and reduces failure escape rate by detecting defects at the transistor level that are missed by traditional automatic test pattern generation (ATPG) techniques. The Mentor Graphics booth is in the North Hall, Booth #6243. Their winning entry was entered in the “Silicon Test Solutions, Facilities & Software” category.

The Best of West Award winner was announced during SEMICON West on Wednesday, July 10, 2013 at 1:00pm.

Leaders of research consortia from around the world sat down to share updates and insights with SEMICON West attendees on Wednesday morning. In a panel led by SEMI President Karen Sevala, four executives from SEMATECH, CNSE, CEA-Leti and imec discussed their companies’ focus and progress on lithography, 3D stacking and ICs, memory and logic and more.

Lithography was a huge project and priority to three out of the four consortia represented and was the first topic brought to the panel by Sevala.

“Lithography is one of the highest priorities of our industry,” said Luc Van den hove, CEO of imec.

Van den hove said that he was very positive about EUV, confident that it was going to be available very soon. Daniel Armbrust of SEMATECH echoed Van den hove’s sentiments, reinforcing the importance of EUV’s availability for the continuation of Moore’s law.

“EUV must happen,” Armbrust emphasized to the crowd. SEMATECH’s EUV program, he said, has been focused on taking the manufacturing technology and making sure it’s ready for high volume production.

“The technology is in relatively decent shape,” Armbrust said. The challenge, he explained, is defect performance.

3D stacking and TSVs were also a hot topic. Michael Liehr of CNSE said, while important, 3D has been slower to take off than expected.

“The cost and implementation are still a lot more extensive than typical packaging solutions,” Liehr said. “We hope that this technology will lead to a leap in performance.”

Van den hove shared that imec believes that 3D stacking and ICs are very important technologies, and that the consortia started their programs about ten years ago.

“One of the biggest challenges with this technology is that we have two worlds that need to meet,” said Van den hove, in an effort to encourage industry collaboration.

Concerning memory and logic, Armbrust said that SEMATECH has been moving to 3D structures and focusing on the 7nm node, which has inevitably led to changes in device structure.

“The most promising candidate,” said Armbrust, “is replacing silicon with a material that provides III-V compounds.”

 

Battered by the nonstop onslaught of media tablets, the mobile PC market in 2013 delivered the worst second-quarter performance in 11 years, according to preliminary data provided by a PC Dynamics Market Brief from information and analytics provider IHS (NYSE: IHS).

Worldwide mobile PC shipments in the second quarter shrank a steep 6.9 percent compared to the first three months of the year, based on initial findings. This represented the first time the industry experienced a sequential decline since the second quarter of 2002. At that time, mobile PC shipments contracted 3.7 percent after the dot.com bust flattened global demand.

In the 10 years between those two low points, the mobile PC space had always strengthened in the second quarter as shipments recovered from a normally soft start to the year. Excluding 2002 and this year, growth for every second quarter during the intervening years had ranged from 0.5 percent to as much as 6.5 percent, as shown in the attached figure. Just last year, the industry enjoyed a 3.9 percent increase for the period.

The depressed results are not confined to the second quarter alone. When the overall first half is considered, 2013 has made history as having the poorest performance since 2003, posting a harsh 11.2 percent contraction compared to the same six-month period a year ago. How much the market has fallen can be seen by the magnitude of growth attained in the previous years. Only three years ago in 2010, mobile PC shipments surged by 41.7 percent in the first half.

“Representing devices such as traditional notebook PCs as well as the new thinner ultrathin/Ultrabook laptops, the mobile PC industry on the whole is struggling to find any momentum for growth as upheavals rock the market,” said Craig Stice, senior principal analyst for compute platforms at IHS. “In particular, more nimble devices like media tablets have taken over among consumers given their ease of use and unique form factor. Meanwhile, innovation in PCs has stagnated, and the recent influx of low-cost tablets has further eaten into an already decimated mobile PC space. With such dire numbers, many are wondering whether this signifies the start of more record declines for mobile PCs, or if the industry has hit rock-bottom.”

High hopes for low costs

An infusion of lower-cost PCs that deliver higher performance but consume less power than current laptops could save the market, IHS believes. Processors like Bay Trail from Intel Corp. and Temash from rival chipmaker Advanced Micro Devices Inc. can go beyond what traditional entry-level processors have been able to provide, and PC makers are contemplating a new class of performance PCs that would incorporate the new processors at affordable prices.

Hopes also remain alive within the industry on prospects for the much more expensive ultrathin and Ultrabook PC models, where growth could still be expected if their prices come down and if consumers can get used to the new Windows 8 operating system after a rocky launch.

The PC that refreshes

With everything considered, a PC refresh buying cycle is more than likely to occur, IHS believes.

‘Despite the broad appeal of media tablets, the devices won’t be able to fully replace PCs, and consumers will continue to need the computational power of personal computers,” Stice said. “If a new low-cost PC offering strong performance can become available on the market and meet consumer expectations, then PCs could be set for more growth—not like the glory days of the 2000s—but growth nonetheless.”

A year to forget

Despite this, 2013 is very likely a write-off at this point. Even with growth expected to occur in the second half, it’s too late given the depressed first-half results that any positive expansion could occur in both the mobile PC segment and the overall PC market.

A full downturn is projected for total PC shipments in 2013, which would make this the second consecutive year of decline, after the contraction of the market last year for the first time since 2001.

At the end of 2012, memory products and foundries accounted for a combined 54% of the IC industry’s installed monthly capacity of 14,497K wafers (200mm-equivalent wafers), according to data in IC Insights’ Global Wafer Capacity 2013 report (Figure 1).  Logic represented 12.4 percent, Microcomponents (MPU, MCU, DSP) represented 10.3 percent, and Analog devices accounted for 9.6 percent of capacity.  The “other” segment is comprised mainly of capacity used in the fabrication of optoelectronic, sensor, and discrete (O-S-D) devices as well as some R&D functions in fabs that are otherwise used primarily for the volume production of IC products.

 

Large-scale production of DRAM and flash memory helped drive installed capacity for all memory to 36.1 percent of installed capacity in December 2012, while the growing foundry segment represented 27.5 percent of capacity.  In terms of sales, virtually all pure-play foundry business is in the fabrication of logic and mixed-signal ICs. Memory product wafers accounted for only about one percent of total pure-play foundry sales in 2012.

Figure 2 shows that on a regional basis, capacity for analog products is fairly evenly distributed among Japan, Europe, and the Americas regions.  In memory, capacity is held mainly by South Korea, Taiwan, and Japan. The largest portion of logic capacity is located in Japan, with the Americas, South Korea, and Europe holding smaller, but still sizeable, shares.  The Americas region is tops in microcomponent capacity due mostly to high-volume MPU production from Intel.  In foundry, Taiwan is by far the largest shareholder of capacity having about 48 percent of the world’s capacity dedicated of foundry work.  China also has a large amount of foundry capacity, with SMIC being responsible for most of that.

SEMI honored 14 industry leaders for their outstanding accomplishments in developing standards for the microelectronics and related industries. The SEMI Standards awards were announced at a reception held during SEMICON West 2013.

The 2013 SEMI International Standards Excellence Award, inspired by Karel Urbanek, is the most prestigious award in the SEMI Standards Program. Yesterday, it was awarded to Dr. Larry Hartsough of UA Associates.  Hartsough has been actively involved in SEMI Standards for over 20 years, serving in a variety of leadership positions. With over 30 years’ experience in the industry in the areas of thin-film deposition, equipment design and plasma processing of materials, he was instrumental in the development of cluster tool and 300mm interface Standards for semiconductor equipment. Additionally, Hartsough’s expertise in patent litigation was invaluable in guiding the Physical Interfaces and Carriers Committee on intellectual property issues. Long-term, committed leaders like Hartsough provide continuity and excellence to the SEMI Standards Program. The Award recognizes the leadership of Karel Urbanek, a SEMI Board of Directors member who was a key figure in the successful globalization the Standards Program.

In addition, the recipients of four major North American SEMI Standards awards were announced:

The Merit Award recognizes Standards Program Member major contributions to the semiconductor, PV, and related industries through the SEMI Standards Program.  Award winners typically take on a very complex problem at the task force level, gain industry support, and drive the project to completion. This year, seven Program Members were presented with the Merit Award for their contributions to the semiconductor, PV, 3D-IC, and HB-LED industries: 

  • Contribution to the PV Industry: Existing SEMI test methods did not provide the ability to measure a broad range of trace elemental impurities in silicon feedstock for solar cells. Through the International PV Analytical Test Methods Task Force, Hugh Gotts (Air Liquide Electronics U.S.) led the development of SEMI PV49-0613, Test Method for the Measurement of Elemental Impurity Concentrations in Silicon Feedstock for Silicon Solar Cells by Bulk Digestion, Inductively Coupled-Plasma Mass Spectrometry.
  • Contribution to the HB-LED Industry: The 150mm sapphire wafers used for manufacturing HB-LED devices are thicker than standard silicon wafers used in the semiconductor industry— making it difficult to use the same cassettes and standards. SEMI HB-LED Equipment Automation Task Force leaders, Jeff Felipe (Entegris) and Daniel Babbs (Brooks Automation) led the development of SEMI HB2-0613, Specification for 150mm Open Plastic and Metal Wafer Cassettes Intended for Use for Manufacturing HB-LED Devices. This cassette standard also enables standardization of load ports and transport systems, resulting in both direct and indirect cost savings throughout the whole supply chain.
  • Contributions to the 3DS-IC Industry: Establishing common understanding and precise communication between stakeholders is important in any manufacturing supply chain, including 3DS-IC. North America 3DS-IC Inspection & Metrology Task Force leaders, David Read (NIST) and Victor Vartanian (SEMATECH), led the successful development of the first 3DS-IC standard published by SEMI, SEMI 3D1-0912: Terminology for Through Silicon Via Geometrical Metrology. It provides consistent terminology for metrology issues important to through silicon vias (TSV), including: pitch, top CD, top diameter, top area, and more. Read and Vartanian were also responsible for the successful development of two other 3DS-IC SEMI Standards — SEMI 3D4 (Bonded Wafer Stack Metrology) and SEMI 3D5 (TSV Metrology).
  • Ilona Schmidt (Corning) was the key developer of SEMI 3D2-0113, Specification for Glass Carrier Wafers for 3DS-IC Applications.  SEMI 3D2 describes dimensional, thermal, and wafer preparation characteristics for glass starting material that will be used as carrier wafers in a temporary bonded state.
  • Contribution to the Semiconductor Industry: Manufacturing equipment is complex, which makes it susceptible to operating errors due to electromagnetic interference (EMI).  SEMI E33 provides recommendations to help assure that manufacturing equipment will operate reliably without failures caused by electromagnetic interference (EMI).  This desired characteristic is generally known as electromagnetic compatibility (EMC). Last year SEMI E33 went through an extensive revision led by technical expert Vladimir Kraz (BestESD Technical Services).

The Leadership Award recognizes Program Members’ outstanding leadership in guiding the SEMI Standards Program.  Since the formation of the HB-LED Technical Committee in late 2010, Julie Chao (Silian Sapphire) and David Joyce (GT Advanced Technologies) have led the Wafer Task Force in defining the physical geometry of wafers used in HB-LED manufacturing.  Their efforts resulted in SEMI HB1-0113, Specifications for Sapphire Wafers Intended for Use for Manufacturing High Brightness-Light Emitting Diode Devices— SEMI’s first HB-LED standard. As task force leaders, Chao and Joyce fostered industry collaboration, travelling to global SEMI events and attracting new key stakeholders, ensuring global input and consensus.

The Honor Award, given to an individual who has demonstrated long-standing dedication to the advancement of SEMI Standards, recognized Richard Allen (NIST/SEMATECH). From his involvement in the Microlithography/Micropatterning Committee to his current leadership in the 3DS-IC and MEMS/NEMS Committees, Allen has been a long-standing and active participant in the SEMI Standards Program.  He joined the 3DS-IC committee shortly after it was formed in late 2010 as serves as committee chairman. He also leads the Bonded Wafer Stacks Task Force, Inspection & Metrology Task Force and Thin Wafer Handling Task Force). His contributions have been instrumental in the publication of four SEMI 3DS-IC Standards to date.

The Corporate Device Member Award recognizes the participation of the user community. This year, three Program Members were presented with the Corporate Device Member Award for their contributions to EHS and 3DS-IC. This year’s Corporate Device Member Awards were presented to Paul Schwab (Texas Instruments), Urmi Ray (Qualcomm), and Raghunandan Chaware (Xilinx).  The award is presented to individuals from device manufacturers.

As co-leader of the S8 Ergonomics Task Force, Paul Schwab (Texas Instruments) provided end-user perspective in the revision of SEMI S8, Safety Guideline for Ergonomics Engineering of Semiconductor Manufacturing Equipment. Schwab significantly improved the Supplier Ergonomics Success Criteria (SESC) checklist criteria, making the Document easier to use by the industry.

Another example of the importance of end-user input was in the development of SEMI’s third 3DS-IC Standard – SEMI 3D3-0613, Guide for Multiwafer Transport and Storage Containers for 300mm, Thin Silicon Wafers on Tape Frames. North America 3DS-IC Thin Wafer Handling Task Force Leaders Urmi Ray (Qualcomm) and Raghunandan Chaware (Xilinx) played integral roles in the development of SEMI 3D3-0613, providing vital end-user perspective for shipping thin wafers on tape frames so that they arrive undamaged at their final destination.

The SEMI Standards Program, established in 1973, covers all aspects of microelectronics process equipment and materials, from wafer manufacturing to test, assembly and packaging, in addition to the manufacture of photovoltaics, flat panel displays and micro-electromechanical systems (MEMS). Over 3,700 volunteers worldwide participate in the program, which is made up of 23 global technical committees. Visit www.semi.org/standards  for more information about SEMI Standards.

 

 

At Leti Day during SEMICON West, Leti Lithography Program Manager Serge Tedesco highlighted different lithography options for advanced technology nodes. Dr. Tedesco suggested that an “optical forever” solution using 193nm immersion lithography in combination with a pitch-multiplication strategy could well provide lithography solutions to very advanced nodes on the industry’s technology roadmap.

Nevertheless, this option will face cost issues, and maskless lithography (ML2) and directed self assembly (DSA) could be very effective as complementary techniques that provide significant cost reductions on some critical levels.

To support their development, Leti created two industrial programs, IMAGINE for ML2, and IDeAL for DSA. Tedesco presented the roadmaps and technical status for both programs, which include large consortiums of industrial partners: IMAGINE around MAPPER Lithography tools, and IDeAL around Arkema’s block copolymer materials for DSA.

Tedesco also noted that Leti’s goal with both programs is to set up the necessary infrastructure to support the industry’s transition toward these complementary technologies.

Biography Dr Serge Tedesco:

Serge Tedesco joined CEA-Leti in Grenoble to take charge of e-Beam lithography, and consequently all advanced lithography activities. Since 2003 he has managed CEA-Leti’s lithography strategy and programs as lithography program manager. Dr. Tedesco has authored or co-authored more than 110 papers in the field of lithography and is a program committee member of the major International lithography conferences. He has been involved in numerous European projects, both as project leader and expert.

CEA-Leti and EV Group (EVG) have launched a three-year common lab to optimize temporary- and permanent-bonding technologies related to 3D TSV integration and all direct bonding heterostructures. 

The lab, which continues more than 10 years of collaboration between the two organizations, is focusing on hardware, software and process development.

“Temporary and permanent bonding equipment and process solutions are key product offerings for EVG,” said Markus Wimplinger, EVG’s corporate technology development and IP director. “This project leverages CEA-Leti’s global leadership in wafer-bonding research and EVG’s unparalleled expertise in developing wafer bonding equipment and process technology.”

“Like all common labs that Leti creates with its partners, this project is designed to produce specific, practical solutions that address current and future market requirements,” said Laurent Malier, CEA-Leti CEO. “This collaboration is targeting results that will make 3D TSV integration more efficient and cost effective and open new areas of wafer bonding using covalent bonding at room temperature.”

“Bringing these approaches to high-volume manufacturing with reliable wafer bonding requires innovative fabrication processes,” said Fabrice Geiger, head of Leti’s Silicon Technology division. “The new equipment and process technology developed within the common lab will allow exciting possibilities, especially for heterogeneous materials stacks, that require very low-temperature wafer bonding.”

Leti is an institute of CEA, a French research-and-technology organization with activities in energy, IT, healthcare, defence and security. Leti is focused on creating value and innovation through technology transfer to its industrial partners. It specializes in nanotechnologies and their applications, from wireless devices and systems, to biology, healthcare and photonics. NEMS and MEMS are at the core of its activities. CEA-Leti operates 8,000-m² of clean room space on 200mm and 300mm wafer platforms. It employs 1,700 scientists and engineers including 320 Ph.D. students and 200 assignees from partner companies. CEA-Leti owns more than 2,200 patent families.

EV Group (EVG) is a supplier of equipment and process solutions for the manufacture of semiconductors, microelectromechanical systems (MEMS), compound semiconductors, power devices, and nanotechnology devices.  Key products include wafer bonding, thin-wafer processing, lithography/nanoimprint lithography (NIL) and metrology equipment, as well as photoresist coaters, cleaners and inspection systems.  Founded in 1980, EV Group services and supports an elaborate network of global customers and partners all over the world.

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SEMICON West 2013 included a robust set of technical and marketing presentations on the general theme of developing new semiconductor devices in the session “Lab to Fab: From R&D to High Volume Manufacturing” held 1:30-3:30PM on July 9. Ably moderated by Paula Doe, the session included presentations on modeling, experimenting, and prototyping new materials and structures such that they can profitably moved into high-volume manufacturing (HVM). Two of the presentations that described not just technologies but new fundamental methodologies for R&D came from Coventor and Intermolecular, small innovative companies based in Silicon Valley.

Dr. David Fried, CTO of Coventor, presented how the company’s “SEMulator3D” software modeling product based on “voxels” allows for advanced physics-based modeling of unit-processes, integrated-processes, device structures, and even device electrical parameters. The modeling starts with unit-processes such as depositions, etches, and epitaxial growth at the nanometer-scale. However, unlike TCAD and other device models, this software can also extend across length scales to provide full-wafer maps of physical parameters.

Fried explained how the model is built on data extracted from publicly available leading device information, such as the cross-section SEMs in Intel’s seminal IEDM paper on 22nm finFETs. The model is “behavioral” since it can predict the effects of changes in dynamic process conditions, and can therefore be used to do “virtual fabrication” of targeted devices. “You can do some interesting explorations,” explained Fried, “like what if you had a defect on a fin that was used to grow an epi-layer?” He showed how the complex interactions of different growth rates in different crystalline directions on 3D structures could be predicted by the software, and that the predicted structural shifts  appear to match the SEM cross-sections shown in the literature.

This modeling software can thus be used as a “virtual metrology” tool that can mimic real in-fab metrology. It can replace slow out-of-fab destructive characterization, and can provide local virtual measurements of structural parameters. It can be used to study the effects of incoming geometric parameters as well as process variations on the final structure. For example, the Cu cross-section area of a BEOL interconnect layer can be predicted, in contrast to unit-process models/controls that merely create wafer-uniformity-maps of  Etch, Cu-barrier/seed PVD, Cu-ECD, Cu-CMP, and other process steps.

Combinatorial R&D

Dr. Raj Jammy, Sr. VP & GM Semiconductor Group, Intermolecular, Inc.—most recently a SEMATECH VP—discussed the need for new ways of doing R&D now that the integration of new materials dominates device enhancements. As semiconductor technology has evolved to smaller and smaller device geometries, the number of new materials used on CMOS chips continues to increase. Consequently, the cost of discovering and integrating new materials into complex devices structures continues to increase.

New materials are needed for 3D FinFETs (alternate-channel materials), 3D Flash Memories and ReRAM (storage cells), and 3D packaging (through-silicon vias and through-mold vias), and all  use complex processes with unpredictable interactions. Developing and optimizing these new materials leads to high costs for R&D and even higher costs to integrate into HVM.

Intermolecular has created High Productivity Combinatorial (HPC™) tools for PVD, CVD, ALD, and wet-processing steps that allow for multiple site-isolated experiments to be done on a single 300mm wafer. When combined with throughput-match characterization tools using an automated database into what the company terms an application-specific “HPC workflow,” everything from an initial design-of-experiments (DOE) to full HVM integration can be done in 3-6 months instead of the 3-5 years needed by conventional R&D approaches.

HPC workflows can accelerate R&D in the early stages of materials exploration such that an entire cycle-of-learning can occur in just 4 hours. HPC workflows can also be used with short-loop flows through a customer’s fab to allow for a 3-4 week cycle-of-learning.

As an example of this methodology’s ability to accelerate learning, Jammy showed how hundreds of experimental parameters had to be explored in developing a germanium (Ge) MOS cap for CMOS integration. Variations in the substrate, surface cleaning, High-K stack, metal electrode, and post-treatment all play significant roles in determining the final device parameters. All these factors had to be co-optimized iteratively, and the project was accomplished in <3 months.

IMI started in 2004 with SanDisk and ATMI, and has since added Guardian Corp., Toshiba, IBM, First Solar, GlobalFoundries, Epistar, Micron as customers.

 

When Ajit Manocha, GlobalFoundries CEO, polled his audience during his keynote address on Tuesday at SEMICON West 2013, nearly 60 percent of the audience believed that the biggest challenge facing the semiconductor industry was the economy. However, during his presentation, Manocha seemed to suggest otherwise.

The technology business is booming, according to Manocha, who shared with SEMICON attendees that the mobile business is forecast to be double the size of the PC market in 2016. The mobile business drives many new requirements, said Manocha, including power, performance and features, higher data rates, high resolution multicore processors and thinner form factors.

This incredible growth is driving new dynamics, said Manocha, and pushing the industry to the new technology node each year, which is presenting the industry with what Manocha deems the Big Five Challenges. Manocha believes these challenges are: cost, device architectures, lithography and EUV, packaging and the 450mm wafer transition.

Cost, said Manocha, continues to be the underlying challenge of the entire industy, because, without focusing on wafer cost, even in good times, a company can enter into what he called “profitless prosperity.” Unfortunately, with the introduction of a new technology node each year, advanced technology costs are rapidly rising.

“Fab cost alone escalates 40 percent year after year,” said Manocha.

To keep wafer costs down, what Manocha believes the industry needs for success is a new foundry model altogether. His model, which he calls Foundry 2.0, hinges on industry collaboration rather than wafer price competition. By encouraging the industry to work together on products and meet the same goals, the industry can see a faster rate of change and tap into global R&D talent.

“The best solutions rarely originate from an insultated team,” he said. “It’s critical that we understand what customers need.”

SEMI recognizes GLOBALFOUNDRIES CEO

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SEMI today announced the results of its annual Board of Directors elections. Bertrand Loy, president and CEO of Entegris, Kyu Dong Sung, CEO of EO Technics, and Xinchao Wang, chairman of JCET, were elected as new directors to the SEMI International Board of Directors. The re-election of existing board members was announced, in addition to new leadership appointments. André-Jacques Auberton-Hervé, chairman, CEO and president of Soitec Group, will serve as SEMI chairman and Yong Han Lee, chairman of Wonik, as SEMI vice-chairman.

Auberton-Hervé succeeds Doug Neugold, chairman, CEO and president of ATMI, who served as SEMI chairman for the last two years. The leadership appointments and elected board members’ tenure becomes effective at the annual SEMI membership meeting, to be held Wednesday, July 10, during the SEMICON West 2013 and Intersolar North America expositions in San Francisco, California.

“Our industry congratulates the newly-elected members of the SEMI International Board of Directors,” said Denny McGuirk, president and CEO of SEMI. “We also very much appreciate the continued service of re-elected members and board leadership.”

In accordance with the association’s by-laws, the following five board members were re-elected for a two-year term:  André-Jacques Auberton-Hervé, chairman, CEO and president, Soitec Group;  David B. Miller, president, DuPont Electronics and Communications; Michael R. Splinter, chairman and CEO, Applied Materials Inc.; Ho-Ming Tong, general manager and chief R&D officer, group R&D, ASE Group;  and Kazuo Ushida, managing director, senior executive officer and president of Precision Equipment Co., Nikon Corporation.

SEMI’s 21 voting directors and 11 emeritus directors represent companies from Europe, China, Japan, Korea, North America, and Taiwan, reflecting the global scope of the association’s activities. SEMI directors are elected by the general membership as voting members of the board and can serve a total of four two-year terms.